US5998739A - Stepped configured circuit board - Google Patents
Stepped configured circuit board Download PDFInfo
- Publication number
- US5998739A US5998739A US08/554,427 US55442795A US5998739A US 5998739 A US5998739 A US 5998739A US 55442795 A US55442795 A US 55442795A US 5998739 A US5998739 A US 5998739A
- Authority
- US
- United States
- Prior art keywords
- conductor
- palladium
- circuit board
- metal
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/26—Cleaning or polishing of the conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/07—Electric details
- H05K2201/0753—Insulation
- H05K2201/0761—Insulation resistance, e.g. of the surface of the PCB between the conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
- H05K2203/0779—Treatments involving liquids, e.g. plating, rinsing characterised by the specific liquids involved
- H05K2203/0786—Using an aqueous solution, e.g. for cleaning or during drilling of holes
- H05K2203/0796—Oxidant in aqueous solution, e.g. permanganate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/002—Etching of the substrate by chemical or physical means by liquid chemical etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
- Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer
Definitions
- the present invention relates to a circuit board and a fabrication method therefor, and more particularly to a circuit board such as multilayer wiring printed circuit board, in which undesirable effects due to residual catalytic metals, such as palladium, used in the production of the circuit board, are eliminated.
- the first is a method called the subtractive method.
- a metal foil is formed on the surface of an insulating material and then an etching resist corresponding to the circuit is formed on the metal foil. Then the unnecessary part of the metal foil is removed by wet etching, thereby forming the circuit board.
- the second method involves forming a circuit by etching after forming a conductor on the surface of an insulating material by sputtering.
- the third is called the additive method. In this method, the surfaces of an insulating material other than those intended to carry the circuit, after treating with palladium, are covered with a plating-resistant resist and then a conductor is deposited on the portion not covered with the plating-resistant resist.
- the technique used involves treating the surface of an insulating material with palladium, depositing a thin conducting layer on the whole surface of the insulating material by electroless plating and then forming a conductor circuit by etching.
- electroplating is performed to increase the thickness of the conducting layer.
- palladium acts as a catalyst in electroless plating and is effective for easily forming a conductor layer.
- palladium is extremely difficult to dissolve in a normal etching solution and remains after etching in devices having electroless plated and electroplated conductors.
- oxidation of the substrate causes carbon-containing components in the resin of the substrate surface to be oxidized into CO 2 .
- the catalytic metal such as palladium
- the present invention provides a circuit board comprising an insulating material substrate and a conductor circuit thereon extending horizontally along a first major surface of said substrate, said conductor circuit comprising: a conductor layer made of a first metal element, a layer of said insulating material on which a second metal element is adsorbed, and a layer of said insulating material on which said second metal element is not adsorbed, wherein said second metal element is more noble than said conductor layer.
- the present invention further provides another circuit board comprising an insulating substrate and a conductor circuit formed thereon extending horizontally along the surface of said substrate, said conductor circuit comprising a conductor layer, a layer of said insulating material on which palladium is adsorbed, and a layer of said insulating material on which palladium is not adsorbed.
- a method for fabricating a circuit board comprising the steps of providing an adsorbed layer of a first metal element on an insulating material substrate, providing a conductor layer of a second metal element on said adsorbed layer and forming a conductor circuit by etching, and removing said first metal element contained in said adsorbed layer together with part of said insulating material substrate by oxidation treatment of the surface of said insulating material substrate, thereby forming said conductor circuit.
- the present invention further provides another method for fabricating a circuit board comprising the steps of providing an adsorbed layer of palladium on an insulating material substrate, providing a conductor layer on said palladium adsorbed layer and forming a conductor circuit by etching, and removing the part of said insulating material substrate containing said palladium adsorbed layer by oxidation treatment of the surface of said insulating material substrate, thereby forming said conductor circuit.
- FIGS. 1a through 1e illustrate one embodiment of the inventive method for fabricating a circuit board according to the present invention.
- the following numbers represent the following elements:
- FIG. 1 illustrates one embodiment of the inventive method for fabricating a circuit board according to the present invention.
- FIG. 1(a) shows a substrate 10 having a palladium adsorbed layer 1 formed thereon.
- the insulating material constituting substrate 10 not only thermosetting resins, such as, e.g., epoxy resin, phenol resin, polyimide and polyester and thermoplastic resins, such as, e.g., flouroresin, polyethylene, polyether sulfone and polyether imide can be used, but also a composite material composed of a thermosetting or thermoplastic resin and paper or glass unwoven fabrics can also be used.
- a substrate 10 formed from one of these insulating materials and having a palladium adsorbed layer 1 thereon is formed by soaking substrate 10 in a palladium chloride solution.
- palladium may be adsorbed on the surface of an insulating material in an interposed state by previously dispersing palladium into the insulating material.
- This palladium, adsorbed onto a resin normally exists in the form of a very thin layer on the surface of the resin and functions as a catalyst in electroless plating.
- a copper plated conductor layer 2 is formed on palladium adsorbed layer 1 by electroless plating.
- a conductor layer obtained by electroplating an electroless plated surface, as desired, may be used.
- a photoresist layer 3 is formed on conductor layer 2, and thereafter unnecessary portions of the copper plated layer 2 are dissolved and removed by using an etching solution to form a circuit.
- an etching solution to form a circuit.
- photosensitive dry films, photosensitive liquid resists, photosensitive electrodeposition resists, nonphotosensitive screen printing resists and the like, for example, can be used as the resist.
- cupric chloride, ferric chloride, a mixed solution of sulfuric acid and hydrogen peroxide and the like can be sued as the etching solution.
- a conductor circuit is formed on the surface of a substrate 10 comprising an insulating material as shown in FIG. 1(d).
- a conductor layer made of copper or the like palladium deposited on the surface of the insulating material underneath the metal to be removed is itself removed somewhat together with the conductor layer removed by the etching operation.
- part of palladium 1a cannot be removed by the etching operation and remains adsorbed on the resin of the substrate 10.
- the surface of the substrate after etching as shown in FIG. 1(d), is subjected to an oxidation treatment.
- the oxidation treatment includes a peranganate treatment, plasma treatment, ozone treatment, and the like.
- oxidation treatment the surface other than that covered with the photoresist layer 3 of the substrate 10 is removed and simultaneously palladium 1a remaining on the surface of the substrate 10 is also removed.
- This fabrication method is effective for the treatment to a substrate of, e.g., multilayer wiring printed circuit board.
- the adsorbed resin surface of palladium remaining on the substrate (circuit board) on which a circuit is formed is oxidation treated.
- permanganate treatment, plasma treatment, ozone treatment, or the like can be used as a means for oxidation treatment. From the standpoint of palladium removal efficiency, permanganate treatment and plasma treatment are preferable.
- a swelling agent swells the surface of an insulating material, which swelling effect is effective for the removal of a resin surface layer portion in the following oxidation treatment.
- a reagent composed of, e.g., diethylene glycol-n-butyl ether, anionic surfactant and sodium hydroxide is preferably used.
- the swelling agent is warmed to 60 to 80° C. and the soaking time is preferably 3 to 10 min. More preferably, the substrate is soaked at 75 to 80° C. for about 7 min.
- the circuit board After soaking in the swelling agent, the circuit board is washed in water and thereafter the permanganate treatment is performed.
- a resin etching solution composed of, e.g., potassium permanganate, sodium hydroxide, and sodium persulfate, is used.
- the circuit board is soaked in the permanganate solution warmed to 65 to 85° C., preferably at 70 to 85° C., for 3 to 15 min., preferably for about 10 min. Thereafter, the circuit board is washed with water, then soaked for 5 to 7 min. in a neutralizer heated to 43 to 51° C. for neutralization, and further washed in water.
- Another oxidation treatment for circuit boards that is effective in accordance with the invention is plasma treatment.
- the circuit board is kept in the interior of an enclosed vessel at a vacuum of 0.1 to 10 Torr, preferably 0.1 to 0.5 Torr.
- the surface of the circuit board is oxidized by flowing a mixed gas of oxygen and freon gases in this vessel.
- the mixing rate of freon gas in the mixed gas is 0 to 50%, preferably 3 to 20%, and the flow rate of the mixed gas into the vessel is 0.3 to 21/min, while the treating time is 1 to 15 min, preferably 3 to 7 min.
- treatment with ozone may be used.
- FIG. 1(e) shows a section of a circuit board after oxidation treatment.
- the portion of the resin surface of substrate 10 other than that carrying the conductor circuit is removed by the oxidation treatment.
- these portions of the surface of substrate 10 form stepped parts 5 different in vertical dimension than the insulating portions of substrate not carrying a metal layer.
- copper is especially useful as the metal element forming conductor layer 2.
- a metal element other than copper can be used for forming conductor layer 2.
- palladium has been shown as an example of a metal element having a catalytic action for forming conductor layer 2 from copper
- a metal element other than palladium having catalytic action to the metal element constituting the conductor layer can be used.
- the catalytic metal element, such as palladium, used in forming the conductor layer needs to be more noble than the metal element constituting the conductor layer in the etching solution for etching the conductor layer.
- a circuit board obtained by the inventive fabrication method has a conductor circuit extending horizontally along the surface of an insulating material substrate 10 and this conductor circuit comprises a conductor layer 2, an adsorbed insulating material layer of a catalytic metal element, such as palladium 1 (this insulating material layer is integrated with the substrate 10 comprising an insulating material), and a not adsorbed insulating material layer of a catalytic metal element, such as palladium 1 (the insulating material layer whose surface is removed by oxidation treatment).
- a catalytic metal element such as palladium 1
- a substrate, having a circuit formed by etching a plated copper on the whole outermost surface thereof with cupric chloride was soaked in an electroless copper plating solution (Cuposit 252: Siplay Far East Co., Ltd.) for 24 hr.
- a substrate having a circuit formed thereon by etching a plated copper layer on the whole outermost surface thereof with cupric chloride was treated with a swelling agent (Circuposit MLB conditioner 211: Siplay Far East Co., Ltd.) warmed at 70° C. for 5 min and washed with water.
- a resin etching solution potassium permanganate solution, Circuposit MLB promoter 213, Siplay Far East Co., Ltd.
- the substrate was soaked in a neutralizer (sulfuric acid, Circuposit MLB neutralizer 216, Siplay Far East Co., Ltd.) warmed at 45° C. for 6 min and then sufficiently washed in water.
- electroless copper plating solution Cuposit 252, Siplay Far East Co., Ltd.
- Comparative Example Copper was etched and copper was deposited on the surface of the epoxy resin in exposed areas between segments of the circuit.
- Embodiment 1 The surface of the epoxy resin between segments of the circuit is identical to a state before electroless copper plating and no deposit of copper was observed.
- Embodiment 2 The surface of the epoxy resin between segments of the copper circuit is identical to a state before electroless copper plating and no deposit of copper was observed.
- the present invention can prevent the generation of a short circuit attributable to the deposit of a metal under catalytic action of this palladium or the like.
Abstract
Description
______________________________________ Number Element ______________________________________ 1 Palladium adsorbedlayer 1a Remaining palladium adsorbedlayer 2 Copper platedlayer 3Photoresist layer 5 Stepped parts different in vertical dimension from thecorresponding resin layer 10 Substrate ______________________________________
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/047,765 US6048465A (en) | 1995-11-06 | 1998-03-25 | Circuit board and fabrication method thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6325145A JP2760952B2 (en) | 1994-12-27 | 1994-12-27 | Circuit board manufacturing method |
JP6-325145 | 1994-12-27 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/047,765 Division US6048465A (en) | 1995-11-06 | 1998-03-25 | Circuit board and fabrication method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
US5998739A true US5998739A (en) | 1999-12-07 |
Family
ID=18173553
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/554,427 Expired - Lifetime US5998739A (en) | 1994-12-27 | 1995-11-06 | Stepped configured circuit board |
Country Status (2)
Country | Link |
---|---|
US (1) | US5998739A (en) |
JP (1) | JP2760952B2 (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030213616A1 (en) * | 2002-05-16 | 2003-11-20 | Junpei Kusukawa | Printed wiring board and electronic device using the same |
US20050241850A1 (en) * | 2004-04-29 | 2005-11-03 | International Business Machines Corporation | Method and structures for implementing customizable dielectric printed circuit card traces |
US20060134914A1 (en) * | 2004-12-21 | 2006-06-22 | 3M Innovative Properties Company | Flexible circuits and method of making same |
US20060191707A1 (en) * | 2001-03-29 | 2006-08-31 | Ngk Insulators, Ltd. | Circuit board and method for producing the same |
US20070101571A1 (en) * | 2003-12-05 | 2007-05-10 | Mitsui Mining & Smelting Co., Ltd. | Printed wiring board, its manufacturing method and circuit device |
US20070111401A1 (en) * | 2003-12-05 | 2007-05-17 | Mitsui Mining & Smelting Co., Ltd | Printed wiring board, its manufacturing method, and circuit device |
US20070246249A1 (en) * | 2003-11-27 | 2007-10-25 | Takeyoshi Kano | Metal Pattern Forming Methd, Metal Pattern Obtained by the Same, Printed Wiring Board, Conductive Film Forming Method, and Conductive Film Obtained by the Same |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6674017B1 (en) | 1998-12-24 | 2004-01-06 | Ngk Spark Plug Co., Ltd. | Multilayer-wiring substrate and method for fabricating same |
JP4770909B2 (en) * | 2001-11-06 | 2011-09-14 | 大日本印刷株式会社 | Method for manufacturing conductive pattern forming body |
JP3881614B2 (en) | 2002-05-20 | 2007-02-14 | 株式会社大和化成研究所 | Circuit pattern forming method |
US7749684B2 (en) | 2002-08-28 | 2010-07-06 | Dai Nippon Printing Co., Ltd. | Method for manufacturing conductive pattern forming body |
JP4709813B2 (en) * | 2003-12-05 | 2011-06-29 | 三井金属鉱業株式会社 | Printed wiring board, circuit device, and printed wiring board manufacturing method |
JP2009010336A (en) * | 2007-05-25 | 2009-01-15 | Fujifilm Corp | Wiring pattern forming method, wiring pattern, and wiring board |
JP4743254B2 (en) * | 2008-10-24 | 2011-08-10 | 大日本印刷株式会社 | Method for manufacturing conductive pattern forming body |
JP5691527B2 (en) * | 2010-01-07 | 2015-04-01 | 日立化成株式会社 | Wiring board surface treatment method and wiring board treated by this surface treatment method |
KR102429398B1 (en) * | 2020-01-13 | 2022-08-04 | 와이엠티 주식회사 | Apparatus for treating pre-dip solution and electroless plating of copper using the same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4853277A (en) * | 1986-09-19 | 1989-08-01 | Firan Corporation | Method for producing circuit boards with deposited metal patterns and circuit boards produced thereby |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3110415C2 (en) * | 1981-03-18 | 1983-08-18 | Ruwel-Werke Spezialfabrik für Leiterplatten GmbH, 4170 Geldern | Process for the manufacture of printed circuit boards |
JPS59200489A (en) * | 1983-04-28 | 1984-11-13 | 株式会社日立製作所 | Method of producing printed board |
JPS6345887A (en) * | 1986-08-13 | 1988-02-26 | キヤノン株式会社 | Manufacture of printed wiring board |
JPH02144987A (en) * | 1988-11-26 | 1990-06-04 | Sumitomo Metal Mining Co Ltd | Manufacture of printed wiring board |
JPH0317390A (en) * | 1989-06-15 | 1991-01-25 | Mitsubishi Heavy Ind Ltd | Shield type excavator |
JP2640285B2 (en) * | 1990-06-13 | 1997-08-13 | 金井 宏之 | Steel cord for reinforcing rubber products |
JPH03254179A (en) * | 1990-03-05 | 1991-11-13 | Hitachi Chem Co Ltd | Manufacture of wiring board |
JP3005868B2 (en) * | 1990-06-25 | 2000-02-07 | 株式会社石井鐵工所 | Gas release method and gas release structure of low temperature storage tank safety valve |
JPH04186893A (en) * | 1990-11-21 | 1992-07-03 | Sumitomo Metal Mining Co Ltd | Manufacture of circuit wiring board |
JP2733375B2 (en) * | 1990-11-30 | 1998-03-30 | イビデン株式会社 | Printed wiring board and method of manufacturing the same |
-
1994
- 1994-12-27 JP JP6325145A patent/JP2760952B2/en not_active Expired - Fee Related
-
1995
- 1995-11-06 US US08/554,427 patent/US5998739A/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4853277A (en) * | 1986-09-19 | 1989-08-01 | Firan Corporation | Method for producing circuit boards with deposited metal patterns and circuit boards produced thereby |
Cited By (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060191707A1 (en) * | 2001-03-29 | 2006-08-31 | Ngk Insulators, Ltd. | Circuit board and method for producing the same |
US7355127B2 (en) * | 2002-05-16 | 2008-04-08 | Renesas Technology Corporation | Printed wiring board and electronic device using the same |
US20030213616A1 (en) * | 2002-05-16 | 2003-11-20 | Junpei Kusukawa | Printed wiring board and electronic device using the same |
US20070246249A1 (en) * | 2003-11-27 | 2007-10-25 | Takeyoshi Kano | Metal Pattern Forming Methd, Metal Pattern Obtained by the Same, Printed Wiring Board, Conductive Film Forming Method, and Conductive Film Obtained by the Same |
US8252364B2 (en) * | 2003-11-27 | 2012-08-28 | Fujifilm Corporation | Metal pattern forming method, metal pattern obtained by the same, printed wiring board, conductive film forming method, and conductive film obtained by the same |
US20110088934A1 (en) * | 2003-11-27 | 2011-04-21 | Fujifilm Corporation | Metal pattern forming method, metal pattern obtained by the same, printed wiring board, conductive film forming method, and conductive film obtained by the same |
KR100720662B1 (en) * | 2003-12-05 | 2007-05-21 | 미쓰이 긴조꾸 고교 가부시키가이샤 | Printed wiring board and its manufacturing method |
US20070111401A1 (en) * | 2003-12-05 | 2007-05-17 | Mitsui Mining & Smelting Co., Ltd | Printed wiring board, its manufacturing method, and circuit device |
US20070101571A1 (en) * | 2003-12-05 | 2007-05-10 | Mitsui Mining & Smelting Co., Ltd. | Printed wiring board, its manufacturing method and circuit device |
TWI397963B (en) * | 2003-12-05 | 2013-06-01 | Printed wiring board, its preparation and circuit device | |
US7523548B2 (en) | 2003-12-05 | 2009-04-28 | Mitsui Mining & Smelting Co., Ltd. | Method for producing a printed circuit board |
US7495177B2 (en) | 2003-12-05 | 2009-02-24 | Mitsui Mining & Smelting Co., Ltd. | Printed wiring board, its manufacturing method, and circuit device |
US20060288570A1 (en) * | 2004-04-29 | 2006-12-28 | International Business Machines Corporation | Method and structures for implementing customizable dielectric printed circuit card traces |
US20050241850A1 (en) * | 2004-04-29 | 2005-11-03 | International Business Machines Corporation | Method and structures for implementing customizable dielectric printed circuit card traces |
US7197818B2 (en) | 2004-04-29 | 2007-04-03 | International Business Machines Corporation | Method and structures for implementing customizable dielectric printed circuit card traces |
US7129417B2 (en) * | 2004-04-29 | 2006-10-31 | International Business Machines Corporation | Method and structures for implementing customizable dielectric printed circuit card traces |
US7364666B2 (en) | 2004-12-21 | 2008-04-29 | 3M Innovative Properties Company | Flexible circuits and method of making same |
WO2006068903A1 (en) * | 2004-12-21 | 2006-06-29 | 3M Innovative Properties Company | Flexible circuits and method of making same |
US20060134914A1 (en) * | 2004-12-21 | 2006-06-22 | 3M Innovative Properties Company | Flexible circuits and method of making same |
Also Published As
Publication number | Publication date |
---|---|
JP2760952B2 (en) | 1998-06-04 |
JPH08186351A (en) | 1996-07-16 |
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