JPS59200489A - Method of producing printed board - Google Patents
Method of producing printed boardInfo
- Publication number
- JPS59200489A JPS59200489A JP7407983A JP7407983A JPS59200489A JP S59200489 A JPS59200489 A JP S59200489A JP 7407983 A JP7407983 A JP 7407983A JP 7407983 A JP7407983 A JP 7407983A JP S59200489 A JPS59200489 A JP S59200489A
- Authority
- JP
- Japan
- Prior art keywords
- printed board
- manufacturing
- plating
- minutes
- catalyst
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、絶縁板上に化学めっきだけで導体回路を形成
するプリント板の製法に係り、特に、導体回路間の電気
絶縁抵抗が十分に犬さく・プリント板の製造方法に関す
る。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method for manufacturing a printed circuit board in which conductor circuits are formed on an insulating board only by chemical plating, and in particular, the present invention relates to a method for manufacturing a printed circuit board in which conductor circuits are formed on an insulating board by chemical plating alone. Concerning the manufacturing method of boards and printed boards.
従来より、絶縁板上に化学めっきだけで導体回路を形成
するプリント板の製造方法はフルアディティブ法として
知られている。その１つの方法として、絶縁板の全表面
に化学めっきのための触媒を付着させ、次いで、回路形
成部以外をめっきレジストでマスクして化学めっきを行
い、回路を形成する方法がある。ところが、この方法で
プリント板を製造する場合、化学めっきがつかない部分
があってつきむらが生じたり、導体回路間の電気抵抗が
低かったりする問題が発生することがある。特に、吸湿
時に電気絶縁抵抗が低くなるという問題がある。Conventionally, a method for manufacturing printed circuit boards in which conductor circuits are formed on an insulating board only by chemical plating has been known as a full additive method. One method is to attach a catalyst for chemical plating to the entire surface of the insulating plate, and then mask areas other than the circuit formation portion with a plating resist and perform chemical plating to form a circuit. However, when manufacturing printed circuit boards using this method, problems may occur such as areas not being coated with chemical plating, resulting in uneven plating, and low electrical resistance between conductor circuits. In particular, there is a problem that the electrical insulation resistance decreases when moisture is absorbed.
本発明は、上述した従来技術の欠点をなくし、電気絶縁
抵抗が十分に太き（、且つ、つきむらなどのないプリン
ト板の製造方法を提供することを目的とする。It is an object of the present invention to eliminate the drawbacks of the prior art described above and to provide a method for manufacturing a printed board with sufficiently large electrical insulation resistance (and without unevenness or the like).
すなわち、本発明を概説すれば、本発明はプリント板の
製造方法の発明であって、絶縁基板表面に化学めっきの
ための触媒を付与する工程（ＡＪ、回路形成部分以外の
部分をめっきレジスト皮膜でマスクする工程（ＢＪ及び
化学めっきにより導体回路を形成する工程（ＯＪの各工
程を包含する１層以上のプリント板を製造する方法にお
いて、該工程（ＯＪの後に、該めっきレジスト皮膜を除
去し、次いで、露出している絶縁基板表面の残存触媒を
除去する工程を付加することを特徴とする。That is, to summarize the present invention, the present invention is an invention of a method for manufacturing a printed board, which includes a step of applying a catalyst for chemical plating to the surface of an insulating substrate (AJ, plating resist film on parts other than circuit forming parts). In a method for manufacturing a printed board with one or more layers including each step of masking (BJ) and forming a conductor circuit by chemical plating (OJ), the plating resist film is removed after the step (OJ). Then, a step of removing the remaining catalyst on the exposed surface of the insulating substrate is added.
本発明者等は電気絶縁抵抗が低かったり、っきむらが生
じたりすることについて種種検討した。その結果、これ
らの問題は化学めっきのための触媒、例えばパラジウム
などの絶縁板への付着量に関係があることを見出した。The inventors of the present invention have conducted various studies on the problems of low electrical insulation resistance and uneven coating. As a result, it was found that these problems are related to the amount of catalyst for chemical plating, such as palladium, attached to the insulating plate.
すなわち、触媒の付着量が少ない場合は十分な化学めっ
きが行われず、つきむらが発生する。ところが、つきむ
らが発生しないように触媒付着魚を多くすると、今度は
導体回路間の絶縁抵抗が小さくなる。この問題はプリン
ト板を吸湿させる吸湿試験のときに顕著となることがわ
かった。電気絶縁抵抗の低下はプリント板にとって大き
な問題である。本発明は上述した状況にかんがみてなさ
れたものである。化学めっきは一般的には化学鋼めっき
が好適である。以上述べた工程を経ることにより、プリ
ント板ができる。また、必要に応じて、スルーホールを
形成する場合は、接着剤層を形成した後で、ドリルある
いはパンチングによって孔をあける。That is, when the amount of catalyst deposited is small, sufficient chemical plating is not performed and uneven plating occurs. However, if the number of catalyst-attached fish is increased to prevent unevenness, the insulation resistance between the conductor circuits becomes smaller. It has been found that this problem becomes more noticeable during moisture absorption tests in which printed boards absorb moisture. A decrease in electrical insulation resistance is a major problem for printed boards. The present invention has been made in view of the above-mentioned situation. Chemical steel plating is generally suitable for chemical plating. By going through the steps described above, a printed board is produced. Further, if a through hole is to be formed as required, the hole is made by drilling or punching after forming the adhesive layer.
化学めっきを終了した後、該めっきレジスト（マスキン
グ材〕を除去する。例えば、塩化メチレン等により除去
する。これだけでは、接着剤表面に付与した化学めっき
のための触媒、例えばパラジウムを除去することができ
ないので。After finishing chemical plating, the plating resist (masking material) is removed.For example, it is removed with methylene chloride, etc.This alone cannot remove the catalyst for chemical plating, such as palladium, applied to the adhesive surface. Because I can't.
触媒を除去するための処理を行う。例えば、硝酸、過＃
Ｌ酸アンモニウム、塩化第二鉄、塩化第二銅、塩酸、過
酸化水素等の水溶液が作業性を考慮すると好適である。Perform treatment to remove the catalyst. For example, nitric acid,
Aqueous solutions of ammonium L-acid, ferric chloride, cupric chloride, hydrochloric acid, hydrogen peroxide, etc. are suitable in view of workability.
触媒除去条件は薬品の種類、濃度、温度、時間等を適宜
選択するごとにより決められる。これにより、導体回路
間の電気抵抗を高くすることができる。特に、吸湿時の
電気抵抗を大きくすることができる。このような処理を
行ったプリント基板は適宜、積層接着し、多層プリント
板にすることも可能である。The catalyst removal conditions are determined by appropriately selecting the type of chemical, concentration, temperature, time, etc. Thereby, the electrical resistance between the conductor circuits can be increased. In particular, the electrical resistance during moisture absorption can be increased. Printed circuit boards subjected to such treatment can be laminated and bonded as appropriate to form a multilayer printed board.
以下、本発明を実施例により更に詳細に説明するが、本
発明はこれに限定されない。EXAMPLES Hereinafter, the present invention will be explained in more detail with reference to Examples, but the present invention is not limited thereto.
実施例
厚さ０．８ｍのガラスエポキシ積層板（日立化成工業社
製、ＬＩ＆６７Ｎ）Ｋフェノール変性ニトリルゴム系の
熱硬化性接着剤を７０−コート法で塗布し、１−５ＤＣ
で６０分間加熱して半硬化させた。次いでもう一方の面
にも上記接着剤を同様の方法で塗布し、１７０Ｃで９０
分加熱して上記接着剤層をほぼ硬化させ、上記積層板の
両面に厚さ約３０μｍの接着剤層を形成した。Example: A glass epoxy laminate with a thickness of 0.8 m (manufactured by Hitachi Chemical Co., Ltd., LI & 67N) was coated with a thermosetting adhesive based on K phenol-modified nitrile rubber using the 70-coat method.
It was heated for 60 minutes to semi-cure it. Next, apply the above adhesive to the other side in the same manner and heat it at 170C for 90 minutes.
The adhesive layer was almost cured by heating for 30 minutes, and adhesive layers with a thickness of about 30 μm were formed on both sides of the laminate.
次に必要個所にドリルにより孔をあけ、クロム酸混液（
０ｒｂ３６０ 、ｌ濃硫酸２２０−を水で薄めて全体を
１４にする）に４５ｔｌ’で７分間浸漬して、上記接着
剤表面を粗化した。次に５分間水洗し、塩酸（３，６％
）に５分間浸漬した。Next, drill holes in the required locations and use a chromic acid mixture (
The adhesive surface was roughened by immersing it in 45 tl' for 7 minutes in 0rb360, 1 concentrated sulfuric acid 220-1 diluted with water to make a total of 14. Next, wash with water for 5 minutes and use hydrochloric acid (3.6%).
) for 5 minutes.
引続き、２分間水洗し、−１３の水酸化ナトリウム水溶
液に５分間浸漬し、更に２分間水洗した。次に塩酸（１
８％）に１分間浸漬した俊、塩化パラジウムと塩化第一
すずを含む増感剤（日立化成工業社製Ｈ５１０１Ｂ）に
１０分間浸漬し、化学めっきの触媒を付与した。更忙２
分間水洗後、塩酸（５，６％）Ｋ５分間浸漬し、次いで
２分間水洗した。この基板を１０００で２０分間乾燥し
た後、ドライタイプのホトレジスト（チオコール：ダイ
ナケム社製ラミナーＧＴ）を両面にラミネートした。次
いで、導体回路部分以外に紫外線を照射し、クロロセン
で現像を行い、回路及びスルーホール部のホトレジスト
を除去した。１５０Ｃ１３０分間加熱乾燥後、下記組成
の化学鋼めっき液に７２Ｇで１０時間浸漬し、約３０μ
ｍの厚さの銅を析出させ、プリント板を作成した。Subsequently, it was washed with water for 2 minutes, immersed in a -13 sodium hydroxide aqueous solution for 5 minutes, and further washed with water for 2 minutes. Next, hydrochloric acid (1
8%) for 1 minute, and immersed for 10 minutes in a sensitizer containing palladium chloride and stannous chloride (H5101B manufactured by Hitachi Chemical Co., Ltd.) to provide a chemical plating catalyst. More busy 2
After washing with water for a minute, it was immersed in hydrochloric acid (5.6%) for 5 minutes, and then washed with water for 2 minutes. After drying this substrate at 1000C for 20 minutes, dry type photoresist (Thiocol: Laminar GT manufactured by Dynachem) was laminated on both sides. Next, areas other than the conductive circuit portion were irradiated with ultraviolet rays and developed with chlorocene to remove the photoresist in the circuit and through-hole portions. After heating and drying at 150C for 130 minutes, it was immersed in a chemical steel plating solution with the following composition at 72G for 10 hours to give a surface of approximately 30μ
A printed board was prepared by depositing copper with a thickness of m.
回路部分以外のホトレジストを除去した。次いで、硝酸
（１０％）に１分間、室温で浸漬し、接着剤層に残存し
ていた触媒を除去した。５分間水洗した後、１６０Ｃで
４０分間加熱乾燥してプリント板を完成させた。The photoresist other than the circuit area was removed. Next, the adhesive layer was immersed in nitric acid (10%) for 1 minute at room temperature to remove the catalyst remaining in the adhesive layer. After washing with water for 5 minutes, the printed board was dried by heating at 160C for 40 minutes.
上述した実施例で（ａ）化学銅めっき後、単に水洗し、
１６０Ｃで４０分間加熱したもの、（ｂＪホトレジスト
を除去まで行って１６０Ｃで４０分間加熱したもの、並
びに＜Ｃ）最終工程まで行ったものについて、プリント
板上に形成した。電気絶縁抵抗測定のための（し形）く
ターン（ＡＳＴＭに基づいたパターン）を使用し、両電
極間に直流５００ｖを印加し、１分後の抵抗値を測定し
た。引続き、４０Ｃで湿度９０％の雰囲気中に９６時間
放置して吸湿させた後、同一（し形）くターンの電気絶
縁抵抗を上述した方法と同一方法で測定した。その結果
を第１表に示す◇第１表
ｇｔ表から明らかなように、本発明による（０）は従来
例（ａ）、（ｂ）に比べて、初期、差びに吸湿後におい
ても電気絶縁抵抗値は太き（、特に吸湿後においてその
季が著しい。In the above example, (a) simply washing with water after chemical copper plating,
The following were formed on printed boards: one heated at 160C for 40 minutes, one heated at 160C for 40 minutes after removal of the bJ photoresist, and <C) one heated until the final step. Using a rectangular pattern (pattern based on ASTM) for measuring electrical insulation resistance, 500 V of direct current was applied between both electrodes, and the resistance value was measured after 1 minute. Subsequently, it was left in an atmosphere of 90% humidity at 40C for 96 hours to absorb moisture, and then the electrical insulation resistance of the same (rectangular) turns was measured by the same method as described above. The results are shown in Table 1 ◇ As is clear from Table 1 gt, (0) according to the present invention has better electrical insulation than the conventional examples (a) and (b) both at the initial stage and after moisture absorption. The resistance value is large (particularly noticeable after moisture absorption.
本発明は、高密度で微細なパターンが要求される多層プ
リント板の製法に適用すると特に効果的である。The present invention is particularly effective when applied to a method for manufacturing multilayer printed boards that requires high-density and fine patterns.
すなわち、パターン間隔がかなり狭い場合にも電気絶縁
抵抗値が大きく、吸湿時でも抵抗値の下がり方が少ない
という極めて顕著な効果をもっている。That is, the electrical insulation resistance value is large even when the pattern spacing is quite narrow, and the resistance value decreases little even when moisture is absorbed, which is a very remarkable effect.
特許出願人 株式会社 日文製作所 代理人中本 宏Patent applicant: Nichibun Seisakusho Co., Ltd. Agent Hiroshi Nakamoto
Claims (1)
る工程（ＡＪ 、回路形成部分以外の部分をめっきレジ
スト皮膜でマスクする工程（Ｂ）及び化学めっきにより
導体回路を形成する工程ｔｃ）の各工程を包含する１層
以上のプリント板を製造する方法において、該工程Ｃｏ
）の後に、該めっきレジスト皮膜を除去し、次いで、露
出している絶縁基板表面の残存触媒を除去する工程を付
加することを特徴とするプリント板の製造方法。 ２、 該工程（ＡＪの絶縁基板が、接着剤層を形成する
工程及び接着剤表面を粗化する工程を含む方法で得た絶
縁基板である特許請求の範囲第１項記載のプリント板の
製造方法。 ３４ 該めっきレジストが１元硬化型のものである特
許請求の範囲第１項記載のプリント板の製造方法。 ４、 該プリント板が多層プリント板であり、１層のプ
リント板を多層化積層接着して得たものである特許請求
の範囲第１項記載のプリント板の製造方法。[Claims] A step of applying a catalyst for chemical plating to the surface of the t am substrate (AJ), a step (B) of masking parts other than the circuit forming part with a plating resist film, and forming a conductor circuit by chemical plating. In the method for manufacturing a printed board of one or more layers including each step of step tc), the step Co
1. A method for manufacturing a printed board, which comprises adding a step of removing the plating resist film and then removing the remaining catalyst on the exposed surface of the insulating substrate after step ). 2. Manufacturing a printed board according to claim 1, wherein the AJ insulating substrate is an insulating substrate obtained by a method including the steps of forming an adhesive layer and roughening the surface of the adhesive. Method. 34. The method for manufacturing a printed board according to claim 1, wherein the plating resist is of a single-curing type. 4. The printed board is a multilayer printed board, and the single layer printed board is multilayered. A method for manufacturing a printed board according to claim 1, which is obtained by laminating and bonding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7407983A JPS59200489A (en) | 1983-04-28 | 1983-04-28 | Method of producing printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7407983A JPS59200489A (en) | 1983-04-28 | 1983-04-28 | Method of producing printed board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59200489A true JPS59200489A (en) | 1984-11-13 |
Family
ID=13536798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7407983A Pending JPS59200489A (en) | 1983-04-28 | 1983-04-28 | Method of producing printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59200489A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02144987A (en) * | 1988-11-26 | 1990-06-04 | Sumitomo Metal Mining Co Ltd | Manufacture of printed wiring board |
| JPH08186351A (en) * | 1994-12-27 | 1996-07-16 | Internatl Business Mach Corp <Ibm> | Circuit board and its preparation |
| WO2020130101A1 (en) * | 2018-12-20 | 2020-06-25 | 日立化成株式会社 | Wiring board and production method for same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5091760A (en) * | 1973-12-18 | 1975-07-22 | ||
| JPS5231539A (en) * | 1975-09-03 | 1977-03-10 | Wahei Inoue | Device for removing overflowing water by utilizing force of water in main stream of river |
| JPS5759395A (en) * | 1980-09-26 | 1982-04-09 | Hitachi Chemical Co Ltd | Method of producing printed circuit board |
-
1983
- 1983-04-28 JP JP7407983A patent/JPS59200489A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5091760A (en) * | 1973-12-18 | 1975-07-22 | ||
| JPS5231539A (en) * | 1975-09-03 | 1977-03-10 | Wahei Inoue | Device for removing overflowing water by utilizing force of water in main stream of river |
| JPS5759395A (en) * | 1980-09-26 | 1982-04-09 | Hitachi Chemical Co Ltd | Method of producing printed circuit board |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02144987A (en) * | 1988-11-26 | 1990-06-04 | Sumitomo Metal Mining Co Ltd | Manufacture of printed wiring board |
| JPH08186351A (en) * | 1994-12-27 | 1996-07-16 | Internatl Business Mach Corp <Ibm> | Circuit board and its preparation |
| WO2020130101A1 (en) * | 2018-12-20 | 2020-06-25 | 日立化成株式会社 | Wiring board and production method for same |
| JPWO2020130101A1 (en) * | 2018-12-20 | 2021-11-04 | 昭和電工マテリアルズ株式会社 | Wiring board and its manufacturing method |
| US11979990B2 (en) | 2018-12-20 | 2024-05-07 | Resonac Corporation | Wiring board and method for manufacturing the same |
| US12004305B2 (en) | 2018-12-20 | 2024-06-04 | Resonac Corporation | Wiring board and production method for same |
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