US20160322491A1 - Semiconductor Devices and Methods for Forming a Semiconductor Device - Google Patents

Semiconductor Devices and Methods for Forming a Semiconductor Device Download PDF

Info

Publication number
US20160322491A1
US20160322491A1 US15/142,211 US201615142211A US2016322491A1 US 20160322491 A1 US20160322491 A1 US 20160322491A1 US 201615142211 A US201615142211 A US 201615142211A US 2016322491 A1 US2016322491 A1 US 2016322491A1
Authority
US
United States
Prior art keywords
region
semiconductor device
doping region
semiconductor
output capacitance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US15/142,211
Other languages
English (en)
Inventor
Franz Hirler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies Austria AG
Original Assignee
Infineon Technologies Austria AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies Austria AG filed Critical Infineon Technologies Austria AG
Assigned to INFINEON TECHNOLOGIES AUSTRIA AG reassignment INFINEON TECHNOLOGIES AUSTRIA AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HIRLER, FRANZ
Publication of US20160322491A1 publication Critical patent/US20160322491A1/en
Priority to US16/210,624 priority Critical patent/US10770578B2/en
Priority to US16/985,758 priority patent/US11515414B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0882—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]

Definitions

  • Embodiments relate to capacitance related modifications of implementation of semiconductor devices and in particular to semiconductor devices and methods for forming semiconductor devices.
  • compensation devices are n- or p-channel metal oxide semiconductor field-effect transistors, diodes, insulated gate bipolar transistors (IGBT), thyristors or other components.
  • Compensation devices may be based on mutual compensation of a charge of n- and p-doped areas in the drift region of the transistor. The areas are spatially arranged such that the line integral over the doping along a line running vertical to the p-n-junction remains below the material-specific breakdown charge (approximately 2 ⁇ 10 12 cm ⁇ 2 for lightly doped silicon).
  • p- and n-pillars or plates may be arranged in pairs.
  • C oss C ds +C gd
  • C gd gate-drain capacitance
  • very low switching losses may be enabled, since the energy in the output capacitance E oss may be low, however, on the other hand leading to extreme switching edges and—in systems with not sufficiently small parasitics as L s (parasitic inductance) or external C gd —portions—to ringing and EMI (electromagnetic interference). It is desired to reduce the ringing and/or EMI, for example.
  • Some embodiments relate to a semiconductor device comprising an output capacitance characteristic with at least one output capacitance maximum located at a voltage larger than 5% of a breakdown voltage of the semiconductor device.
  • the output capacitance maximum is larger than 1.2 times an output capacitance at an output capacitance minimum located at a voltage between the voltage at the output capacitance maximum and 5% of a breakdown voltage of the semiconductor device.
  • Some embodiments relate to a semiconductor device comprising a switchable electrical structure implemented on a semiconductor die.
  • the semiconductor die comprises a first doping region of a first conductivity type within a semiconductor substrate.
  • the first doping region is arranged within the semiconductor substrate so that the first doping region floats during at least a part of a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure until a depletion zone reaches the first doping region.
  • At least a part of free charge carriers existing within the first doping region are removed from the first doping region as soon as the depletion zone reaches the first doping region.
  • the semiconductor die comprises a feedback path configured to enable a reflow of charge carriers during transition from the off-state of the switchable electrical structure to the on-state of the switchable electrical structure.
  • the feedback path is configured to block a flow of charge carriers through the feedback path during at least a part of a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure.
  • Some embodiments relate to a semiconductor device comprising a semiconductor substrate comprising a cell region laterally surrounded by an edge termination region.
  • the edge termination region is configured to support a maximal operating voltage difference applied to the semiconductor device during normal operation between the cell region and an edge of the semiconductor substrate.
  • the semiconductor substrate comprises a first doping region located at an area within the edge termination region comprising between 20% and 80% of the maximal operating voltage difference if the maximal operating voltage difference is applied to the semiconductor device.
  • the first doping region is electrically connected by an electrically conductive structure inside or outside the semiconductor substrate to a capacitance increasing structure located within a region of the edge termination region comprising voltage difference of at least 90% of the maximal operating voltage difference to a region within the cell region.
  • FIG. 1 shows a schematic illustration of a semiconductor device with a possible schematic output capacitance characteristic
  • FIG. 2 shows a schematic illustration of an output capacitance characteristic of a semiconductor device
  • FIG. 3 shows a schematic illustration of a semiconductor device with a doping region causing an output capacitance maximum
  • FIG. 4 shows a schematic illustration of a semiconductor device with a capacitance increasing structure
  • FIG. 5 shows a schematic illustration of a semiconductor device with another capacitance increasing structure
  • FIG. 6 a shows a schematic illustration of a semiconductor device during a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure
  • FIG. 6 b shows a schematic illustration of the semiconductor device of FIG. 6 a during a transition from an off-state of the switchable electrical structure to an on-state of the switchable electrical structure;
  • FIG. 7 shows a schematic illustration of a semiconductor device with a capacitive structure
  • FIG. 8 shows a flow chart for forming a semiconductor device
  • FIG. 9 shows a flow chart for forming another semiconductor device.
  • FIG. 1 shows a semiconductor device according to an embodiment.
  • the semiconductor device 100 comprises an output capacitance characteristic with at least one output capacitance maximum C max located at a voltage 102 larger than 5% of a breakdown voltage V BD of the semiconductor device 100 .
  • the output capacitance maximum C max is larger than 1.2 times an output capacitance at an output capacitance minimum C min located at a voltage 104 between the voltage 102 at the output capacitance maximum C max and 5% of a breakdown voltage V BD of the semiconductor device 100 .
  • the edge steepness of switching edges of the semiconductor device may be reduced due to the locally increased output capacitance, for example. In this way, ringing and/or EMI may be reduced.
  • the output capacitance characteristic may represent the course of a capacitance of the semiconductor device 100 versus a voltage applied to two terminals (e.g. externally accessible terminals) of the semiconductor device 100 .
  • the output capacitance of the output capacitance characteristic of the semiconductor device 100 may be a drain-source capacitance C ds , a gate-drain capacitance C gd or an overall output capacitance represented by a sum of the drain-source capacitance C ds and the gate-drain capacitance C gd of a transistor arrangement implemented by the semiconductor device 100 .
  • the output capacitance maximum C max may be a local maximum of the output capacitance characteristic located above 5% (or above 10% or above 20%) of the breakdown voltage V BD of the semiconductor device 100 .
  • the output capacitance characteristic may comprise more than one local maximum located above 5% of the breakdown voltage V BD of the semiconductor device 100 .
  • the output capacitance maximum C max may be located at a voltage between 20% and 80% of the breakdown voltage V BD of the semiconductor device 100 .
  • the output capacitance maximum C max may be measured by sweeping an applied voltage from 0V to a nominal voltage or the breakdown voltage of the semiconductor device and measuring the current.
  • the output capacitance maximum C max may be difficult to measure with an AC capacitance measurement, since the applied voltage may be varied over a small voltage range during the measurement only so that the effect of the output capacitance maximum C max may be too small when integrating over several voltage oscillations, since the effect of the output capacitance maximum C max may only occur during the first oscillation, if the voltage range of the oscillation during the measurement is too low.
  • the breakdown voltage V BD of the semiconductor device 100 may be defined by a maximum voltage difference that can be applied to the semiconductor device 100 without damaging the device.
  • the breakdown voltage V BD or blocking voltage of the semiconductor device 100 may be a parameter defined in the datasheet of the semiconductor device.
  • the breakdown voltage of a power field effect transistor may be a maximally allowed drain source voltage in an off-state of the transistor (e.g. gate source voltage equal or close to 0).
  • the semiconductor device 100 may comprise a breakdown voltage V BD of more than more than 10V (e.g. a breakdown voltage of 10 V, 20 V or 50V) 100 V (e.g. a breakdown voltage of 200 V, 300 V, 400V or 500V) or more than 500 V (e.g. a breakdown voltage of 600 V, 700 V, 800V or 1000V) or more than 1000 V (e.g. a breakdown voltage of 1200 V, 1500 V, 1700V or 2000V).
  • 10V e.g. a breakdown voltage of 10 V, 20 V or 50V
  • the output capacitance maximum C max is larger than 1.2 (e.g. or larger than 1.5 times or larger than 2 times) the output capacitance minimum C min . In other words, the output capacitance maximum C max is larger than 120% (e.g. or larger than 150% or larger than 200%) of the output capacitance minimum C min .
  • the output capacitance minimum C min is a capacitance minimum located between the output capacitance maximum C max and 5% of a breakdown voltage V BD of the semiconductor device 100 .
  • the at least one output capacitance minimum C min may be located at a voltage arbitrarily close to 5% of the breakdown voltage V BD (e.g.
  • the output capacitance minimum C min may be located somewhere between the output capacitance maximum C max and 5% of a breakdown voltage V BD of the semiconductor device 100 .
  • the output capacitance maximum C max may be located in a proximity of a nominal operating voltage of an application using the semiconductor device 100
  • the nominal operating voltage of an application using the semiconductor device 100 may be between 40% and 80% of the breakdown voltage V BD of the semiconductor device 100 .
  • the output capacitance maximum C max may be located at a voltage so that an output capacitance of at least 90% of the output capacitance maximum C max occurs at the nominal operating voltage.
  • the output capacitance maximum C max may be located slightly above the nominal operating voltage (e.g. between 5% and 20% of the nominal operating voltage above the nominal operating voltage).
  • FIG. 2 shows an example of an output capacitance characteristic represented by the course 210 of the drain-source capacitance C ds and the course 220 of a gate-drain capacitance C gd of a semiconductor device.
  • an output capacitance maximum C max is implemented at the drain-source capacitance C ds while the gate-drain capacitance C gd of a semiconductor device is implemented without distinctive maximum.
  • FIG. 2 shows a possible dynamic course of capacitance.
  • the output capacitance characteristic comprises a hysteresis loop portion with different output capacitances for increasing voltage and decreasing voltage.
  • a course of the output capacitance characteristic for increasing voltage comprises the output capacitance maximum C max while a course of the output capacitance characteristic for decreasing voltage comprises no or a significantly lower (e.g. less than 1.1 times the output capacitance at the output capacitance minimum) output capacitance maximum at the voltage of the output capacitance maximum C max for increasing voltage.
  • the output capacitance maximum C max for increasing voltage occurs repeatedly during running through the loop, for example.
  • the output capacitance characteristic may comprise a second output capacitance maximum located at a voltage larger than 5% of a breakdown voltage V BD of the semiconductor device 100 .
  • the second output capacitance maximum may be larger than 1.2 times the output capacitance at the output capacitance minimum located at a voltage between the voltage at the first output capacitance maximum and 5% of a breakdown voltage of the semiconductor device. Ringing or EMI may be reduced at more than one voltage by implementing a semiconductor device with more than one output capacitance maximum, for example.
  • the semiconductor device 100 may be any electrical device (e.g. diode, transistor, circuit) comprising a semiconductor substrate or semiconductor die implementing an electrical functionality.
  • the semiconductor substrate of the semiconductor device 100 may be a silicon substrate, a silicon carbide substrate, a gallium arsenide substrate or a gallium nitride substrate or gallium nitride/aluminum gallium nitride on silicon, for example.
  • the semiconductor device 100 may be a power semiconductor device with a breakdown voltage V BD of more than 100 V.
  • the output capacitance maximum C max may be implemented or caused by various structural measures or structures of the semiconductor device 100 .
  • the semiconductor device 100 may comprise a switchable electrical structure implemented on a semiconductor die 100 .
  • the switchable electrical structure may be one or more field effect transistors, one or more bipolar transistors, one or more insulated gate bipolar transistors which are switchable by applying a corresponding gate voltage or base voltage to the transistor or one or more diodes which are switchable between a forward mode and a reverse (or blocking) mode by an externally applied alternating voltage.
  • the semiconductor die of the semiconductor device 100 may comprise a first doping region of a first conductivity type (e.g. p-doped or n-doped) within a semiconductor substrate.
  • the first doping region may be arranged within the semiconductor substrate so that the first doping region floats during at least a part of a transition from an on-state (e.g. conducting state or forward state) of the switchable electrical structure to an off-state (e.g. non-conducting state or blocking state) of the switchable electrical structure until a depletion zone reaches the first doping region.
  • At least a part of free charge carriers existing within the first doping region may be removed from the first doping region as soon as the depletion zone reaches the first doping region.
  • the first doping region is a region within the semiconductor substrate bordered by a region of the second conductivity type and optionally by a surface of the semiconductor substrate.
  • a region comprising the first conductivity type may be a p-doped region (e.g. caused by incorporating aluminum ions or boron ions) or an n-doped region (e.g. caused by incorporating nitrogen ions, phosphor ions or arsenic ions). Consequently, the second conductivity type indicates an opposite n-doped region or p-doped region.
  • the first conductivity type may indicate a p-doping and the second conductivity type may indicate an n-doping or vice-versa.
  • the first doping region may also be called floating doping region or output capacitance adapting doping region.
  • the first doping region may be a floating doping region with at least one pn-junction between the first doping region and a structure providing a defined potential during operation of the semiconductor device 100 .
  • the first doping region may be connected to a structure providing a defined potential during operation of the semiconductor device 100 through a switchable connecting structure so that the first doping region floats during at least a part of a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure.
  • the switchable connecting structure may be a junction field effect structure reaching a depleted state before the first doping region reaches a depleted state.
  • the switchable electrical structure is configured to reach a non-conductive state during switch-off of the switchable electrical structure before the first doping region is depleted (e.g. before more than 50% of the free charge carriers existing within the first doping region in an on-state of the switchable electrical structure have been removed from the first doping region).
  • the first doping structure is connected to a structure providing a defined potential in an on-state of the switchable electrical structure and is floating after the switchable connecting structure cuts off the connection to the structure providing a defined potential during the transition from the on-state of the switchable electrical structure to the off-state of the switchable electrical structure.
  • a voltage drop over the semiconductor device 100 increases.
  • the depletion zone of a blocking pn-junction of the switchable electrical structure may grow during the increase of the voltage drop and may move towards the first doping region.
  • the first doping region may be located at a position within the semiconductor substrate so that a depletion zone of a blocking pn-junction reaches the first doping region during switch-off of the switchable electrical structure. At the time, the depletion zone reaches the first doping region, free charge carriers may be removed from the first doping region through the depletion zone. In this way, the output capacitance of the semiconductor device 100 may be increased when the depletion zone reaches the first doping region. For example, the output capacitance maximum is caused by the removal of free charge carriers from the first doping region due to the depletion zone reaching the first doping region.
  • the voltage at which the first doping region is reached by the depletion zone may be set or defined by a distance between the first doping region and the blocking pn-junction and/or a doping distribution (e.g. doping concentration and/or different regions of different conductivity type) between the first doping region and the blocking pn-junction. In this way, an output capacitance maximum may be implemented at a desired voltage.
  • a doping distribution e.g. doping concentration and/or different regions of different conductivity type
  • the semiconductor substrate may comprise a cell region laterally surrounded by an edge termination region.
  • the cell region may be region of the semiconductor substrate providing more than 90% of a current through the semiconductor substrate in an on-state of the switchable electrical structure.
  • the edge termination region may be located between an edge of the semiconductor substrate and the cell region in order to support or block or reduce or dissipate a maximal voltage applied to the cell region laterally towards the edge of the semiconductor substrate.
  • the semiconductor substrate may comprise more than one cell region and the an edge termination region may be arranged between two neighboring cell regions.
  • the first doping region may be located within the edge termination region.
  • a depletion region growing from the cell region towards the edge of the semiconductor substrate may reach the first doping region at a desired voltage during increasing the voltage applied to the cell region, for example.
  • the first doping region may be located at a lateral distance (e.g. in a top view of the semiconductor substrate) from a border between the cell region and the edge termination region and/or from an edge of the semiconductor substrate of more than 20% (or more than 30% or more than 40%) of a minimal distance between an edge of the semiconductor substrate and a border between the cell region and the edge termination region.
  • the first doping region may be located below a gate pad, for example.
  • the first doping region may be located within an edge termination region arranged between two neighboring cell regions.
  • a maximal operating voltage difference applied to the semiconductor device during normal operation may occur between a region (e.g. source region) of the cell region and an edge of the semiconductor substrate.
  • the maximal operating voltage difference may be a source-drain voltage of a power field effect transistor in an off-state of the power field effect transistor.
  • the semiconductor substrate may comprises the first doping region located at an area within the edge termination region comprising between 20% and 80% of the maximal operating voltage difference if the maximal operating voltage difference is applied to the semiconductor device.
  • the semiconductor die of the semiconductor device 100 may comprise a feedback path configured to enable a reflow of charge carriers during transition from the off-state of the switchable electrical structure to the on-state of the switchable electrical structure. Further, the feedback path may be configured to block a flow of charge carriers through the feedback path during at least a part of a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure. A reflow of charge carriers to the first doping region may be enabled by the feedback path so that free charge carriers can be repeatedly removed from the first doping region during the switch-off of the switchable electrical structure.
  • the feedback path may comprise a diode structure configured to block a flow of charge carriers through the feedback path during at least a part of a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure (e.g. FIG. 3 ).
  • the feedback path may comprise a second doping region of the first conductivity type configured to be depleted before the depletion zone reaches the first doping region (e.g. FIG. 4 or 5 ).
  • the feedback path may comprise a transistor configured to block a flow of charge carriers through the feedback path during at least a part of a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure.
  • the semiconductor device may comprise a semiconductor die including a power semiconductor transistor arrangement comprising the output capacitance characteristic.
  • the power semiconductor transistor arrangement may comprise a plurality of field effect transistor cells or a plurality of insulated gate bipolar transistor cells, for example.
  • the power semiconductor transistor arrangement may be a vertical power semiconductor transistor arrangement.
  • the vertical power semiconductor transistor arrangement may comprise a source electrode structure (e.g. source metal structure) at a front side semiconductor die and a drain electrode structure (e.g. back side metallization) at a back side of the semiconductor die.
  • the semiconductor die may comprise a first connection interface (e.g. gate pad and/or gate metal structure) connected to a gate structure (e.g. poly silicon gate) of the power semiconductor transistor arrangement, a second connection interface (e.g. source pad and/or source metallization) connected to a source structure (e.g. source doping regions within the semiconductor substrate) of the power semiconductor transistor arrangement and a third connection interface (e.g. drain pad or back side drain metallization) connected to a drain structure (e.g. drain doping region within the semiconductor substrate) of the power semiconductor transistor arrangement.
  • a first connection interface e.g. gate pad and/or gate metal structure
  • a gate structure e.g. poly silicon gate
  • second connection interface e.g. source pad and/or source metallization
  • source structure e.g. source doping regions within the semiconductor substrate
  • a third connection interface e.g. drain pad or back side drain metallization
  • the output capacitance characteristic represents a drain-source capacitance between the second connection interface and the third connection interface of the power semiconductor transistor arrangement, a gate-drain capacitance between the first connection interface and the third connection interface of the power semiconductor transistor arrangement or a sum of the drain-source capacitance of the power semiconductor transistor arrangement and the gate-drain capacitance of the power semiconductor transistor arrangement.
  • the power semiconductor transistor arrangement may be a compensation or superjunction transistor arrangement.
  • the power semiconductor transistor arrangement comprises a plurality of cell compensation regions extend into a semiconductor substrate within a cell region of the semiconductor substrate.
  • one or more drift regions may be located adjacent to the plurality of cell compensation regions separating neighboring cell compensation regions of the plurality of cell compensation regions from each other.
  • the cell compensation regions of the plurality of cell compensation regions may comprise the first conductivity type and the one or more drift regions may comprise the second conductivity type.
  • the plurality of cell compensation regions may extend from a front side surface of the semiconductor substrate into a depth of more than 10 ⁇ m (or more than 20 ⁇ m or more than 50 ⁇ m).
  • the cell compensation regions may be pillar-shaped, column-shaped or strip-shaped.
  • the plurality of cell compensation regions may be regions of the semiconductor substrate comprising a stripe-shape in a top view of the semiconductor substrate of the semiconductor device 100 .
  • a stripe-shape may be a geometry extending in a first lateral direction significantly farther than in an orthogonal second lateral direction.
  • the cell compensation regions may comprise a lateral length of more than 10 ⁇ (or more than 50 ⁇ or more than 100 ⁇ ) a lateral width of a cell compensation region of the plurality of cell compensation regions.
  • the lateral length of the cell compensation region may be the largest extension along the front side surface of the semiconductor substrate and a lateral width of the cell compensation region may be a shortest dimension of the stripe-shaped cell compensation region.
  • the plurality of cell compensation regions may comprise a vertical extension larger than the lateral width and shorter than the lateral length.
  • Compensation devices may be based on mutual compensation of at least a part of the charge of n- and p-doped areas in the drift region of the vertical power semiconductor transistor arrangement.
  • p-and n-pillars or plates one or more drift regions and plurality of cell compensation regions
  • the cell compensation regions of the plurality of cell compensation regions may comprise a laterally summed number of dopants per unit area of the first conductivity type deviating from a laterally summed number of dopants per unit area of the second conductivity type comprised by the one or more drift region by less than +/ ⁇ 25% of the laterally summed number of dopants per unit area of the first conductivity type comprised by the cell compensation regions within the cell region.
  • a strip-shaped cell compensation region of the plurality of strip-shaped cell compensation regions comprises a laterally summed number of dopants per unit area of the first conductivity type (p or n) deviating from half of a laterally summed number of dopants per unit area of the second conductivity type (n or p) comprised by two strip-shaped drift regions located adjacent to opposite sides of the strip-shaped cell compensation region by less than +/ ⁇ 25% (or less than 15%, less than +/ ⁇ 10%, less than +/ ⁇ 5%, less than 2% or less than 1%) of the laterally summed number of dopants per unit area of the first conductivity type comprised by the strip-shaped cell compensation region.
  • the lateral summed number of dopants per unit area may be substantially constant or may vary for different depths.
  • the lateral summed number of dopants per unit area may be equal or proportional to a number of free charge carriers within a strip-shaped cell compensation region or a strip-shaped drift region to be compensated in a particular depth, for example.
  • the first doping region mentioned above may be located within an edge termination region of the semiconductor substrate and may comprise a number of doping atoms larger than 5 times (or larger than 10 times or larger than 50 times) a number of doping atoms within one cell compensation region of the plurality of cell compensation regions or within one edge termination compensation region of a plurality of edge termination compensation regions located within the edge termination region.
  • the first doping region may comprise substantially the same doping concentration as the cell compensation regions, but may occupy a significantly larger part of the semiconductor substrate.
  • the first doping region may comprise a doping concentration significantly larger (e.g. 5 times larger or 10 times larger) than a doping concentration (e.g. average or maximal doping concentration) of the cell compensation regions. In this way, the contribution of the first doping region to the output capacitance of the semiconductor device 100 may be larger than a contribution of a cell compensation region or an edge termination compensation region.
  • the first doping region may be formed simultaneously with the plurality of compensation structures by a mutual implant process, deposition process or growth process.
  • FIG. 3 shows a schematic cross section of a part of a semiconductor device according to an embodiment.
  • the semiconductor device 300 comprises a compensation or superjunction field effect transistor arrangement.
  • the transistor arrangement comprises a plurality of transistor cells within a cell region of a semiconductor substrate of the semiconductor device 300 .
  • Each transistor cell comprises a source region 332 of the second conductivity type (e.g. highly n-doped) in contact with a source electrode structure 330 at a surface of the semiconductor substrate.
  • each transistor cell comprises a body region 334 of the first conductivity type located between the source region 332 of the transistor cell and a drift region 338 of the second conductivity type (e.g. lightly n-doped).
  • the body region 334 of the transistor cell may be also in contact with the source electrode structure 330 at the surface of the semiconductor substrate. Further, a cell compensation region 336 of the first conductivity type extends from the body region 334 vertically into the semiconductor substrate. Additionally, a gate 344 is arranged in proximity of the body region 334 in order to control a conduction state (e.g. conducting or non-conducting state) of a channel through the body region 334 . Alternatively, the gates may be implemented as trench gates.
  • the gate 334 is connected to a gate electrode structure 340 (e.g. a gate ring laterally surrounding the source electrode structure).
  • the gate electrode structure 340 may comprise a gate field plate 342 arranged at a border between the cell region and the edge termination region.
  • the semiconductor substrate comprises a drain region 362 (e.g. highly n-doped) located at a backside of the semiconductor substrate in contact with a drain electrode structure 360 (e.g. back side metallization).
  • a front side drain electrode structure 350 is arranged in proximity to an edge of the semiconductor substrate. Close to the edge of the semiconductor substrate, the drain electrode structure 350 is in contact with a region of the semiconductor substrate comprising the second conductivity type.
  • a plurality of edge termination compensation regions 370 of the first conductivity type may be arranged within the edge termination region of the semiconductor substrate.
  • the plurality of edge termination compensation regions 370 may be buried regions within the semiconductor substrate.
  • the plurality of edge termination compensation regions 370 may be electrically connected (e.g. directly or through a body region of a transistor cell) to the source electrode structure 330 by a laterally extending doping region 372 of the first conductivity type located at an end of the plurality of edge termination compensation regions 370 close to a front side surface of the semiconductor substrate.
  • a first doping region 310 is located within the semiconductor substrate.
  • the first doping region 310 is implemented without ohmic path to a structure (e.g. source or drain) providing a defined potential. At least a part of free charge carriers existing within the first doping region 310 are removed from the first doping region 310 as soon as a depletion zone of the body-drain pn-junction reaches the first doping region during switch-off of the transistor arrangement of the semiconductor device 300 .
  • the first doping region 310 is connected to the source electrode structure through a feedback path 320 comprising at least one pn-junction (e.g. implemented by a diode structure).
  • an external diode may be connected to the feedback path or a diode structure may be implemented within a poly-silicon layer of the semiconductor device outside the semiconductor substrate.
  • the feedback path 320 enables a reflow of charge carriers during transition from the off-state to the on-state of the transistor arrangement and blocks a flow of charge carriers through the feedback path during at least a part of a transition from the on-state to the off-state of the transistor arrangement, for example.
  • the output capacitance C oss (and/or C gd ) may be increased at designated voltage ranges, which may depend on the application.
  • the dynamic output capacitance may be increased in a predefined voltage range by suitable interconnecting p-columns (e.g. edge termination compensation regions of the first conductivity type) at the edge (e.g. FIG. 2 ).
  • suitable interconnecting p-columns e.g. edge termination compensation regions of the first conductivity type
  • Dynamically may mean that the capacitance (maximum) may occur during an increase of the voltage only, if the voltage starts at negative or small positive source-drain voltages V ds (some Volts) and not at decreasing voltages, for example.
  • single pillars 310 may be arranged separated from a laterally extending p-region 372 at an edge with p-pillars (and/or n-pillars), which are substantially all connected to the source region through the laterally extending p-region 372 , for example.
  • These may be several pillars which are connected to each other within or outside the semiconductor substrate (e.g. shown in FIG. 3 ).
  • the distance from the depletion zone generating pn-junction e.g.
  • a diode 322 may be implemented as discharge-device (e.g. FIG. 3 ) which may nearly completely discharge the floating p-region being at negative voltage (e.g. ⁇ 20V to ⁇ 40V) during switch-on.
  • the contacting of the floating p-region may be implemented in the third dimension at the semiconductor surface, for example.
  • FIG. 3 may show an example of a semiconductor device 300 with compensated edge.
  • FIG. 3 may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more embodiments described above (e.g. FIG. 1 ) or below (e.g. FIGS. 3-9 ).
  • FIG. 4 shows a schematic cross section of a part of a semiconductor device according to an embodiment.
  • the implementation of the semiconductor device 400 is similar to the implementation of the semiconductor shown in FIG. 3 .
  • the first doping region 310 is connected to the source electrode structure through a feedback path 420 within the semiconductor substrate.
  • the feedback path 420 comprises a second doping region of the first conductivity type (e.g. lightly doped) configured to be depleted before the depletion zone reaches the first doping region.
  • the feedback path 420 may comprise a junction field effect transistor like structure.
  • the second doping region comprises a dimension and/or a doping concentration so that the second doping region is depleted very early during the switch-off of the transistor arrangement.
  • the second doping region may be a shallow doping region at the surface or close to the surface of the semiconductor substrate (e.g. with a depth of less than 10% of a depth of a cell compensation region). Additionally or alternatively, the second doping region may comprise a doping dose of less than 2* 10 12 cm ⁇ 2 (or less than 5* 10 11 cm ⁇ 2 ).
  • the first doping region 310 is connected to a capacitance increasing structure through an electrically conductive structure 414 .
  • the number of free charge carriers removable through the depletion region reaching the first doping region 310 may be significantly increased. Therefore, a more pronounced output capacitance maximum may be obtained.
  • the capacitance increasing structure may be implemented by at least one other doping region 412 comprising the first conductivity type.
  • an additional compensation doping region of the second conductivity type may be located adjacent to the first doping region to enable a partial compensation, for example.
  • the first doping region 310 may be located at an area within the edge termination region comprising between 20% and 80% of the maximal operating voltage difference if the maximal operating voltage difference is applied to the semiconductor device.
  • the first doping region 310 is electrically connected by the electrically conductive structure 414 inside or outside the semiconductor substrate to the capacitance increasing structure located within a region of the edge termination region comprising a voltage difference of at least 90% of the maximal operating voltage difference to a region within the cell region.
  • a portion of the semiconductor substrate within the edge termination region which is located adjacent to the drain region 362 may represent an intrinsic semiconductor region without doping or with very low doping (e.g. no doping, lightly n-doped or very lightly p-doped).
  • FIG. 4 may show an embodiment with intrinsic edge.
  • the edge region may be lightly n-doped or close to intrinsic.
  • P-pillars may be arranged at suitable distances which may be locally compensated by n-pillars (middle of edge) or uncompensated (similar to p-ring-edges, for example, column 370 between drain electrode structure and first doping region). These columns may be connected to the source contacts by p-regions 420 which can be depleted.
  • the p-regions 420 which can be depleted may be depleted at very low voltages (e.g. ⁇ 10V or ⁇ 5V) so that very few pillar charges may flow off through the still (at the beginning of the increase) conducting regions during increase of V ds .
  • the charge remaining after depletion (of the p-regions 420 ) may flow off as soon as the depletion zone hits the pillar (first doping region).
  • two dynamic maxima one for the first doping region and one for the column 370 between drain electrode structure and first doping region
  • the connecting p-region may be discharged during switch-on so that the pillars (first doping region and the column 370 between drain electrode structure and first doping region) can be discharged subsequently.
  • the p-pillar 310 which is controlled by the depletion zone may be connected with further pillars (e.g. outside the voltage bearing edge) to increase the capacitance. This may be implemented geometrically in the third dimension or by additional p-regions or by metallic or other connections.
  • FIG. 4 may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more embodiments described above (e.g. FIG. 1 or 3 ) or below (e.g. FIGS. 5-9 ).
  • FIG. 5 shows a schematic top view of a part of a semiconductor device according to an embodiment.
  • the implementation of the semiconductor device 500 is similar to the implementation of the semiconductor shown in FIG. 4 .
  • the feedback path 550 is implemented close to an edge of the semiconductor substrate.
  • the semiconductor substrate comprises an edge termination region 520 located laterally between a cell region 510 and an edge of the semiconductor substrate.
  • the edge termination region 520 may comprise an edge region 530 being a region of the edge termination region comprising voltage difference of at least 90% of the maximal operating voltage difference to a region within the cell region.
  • a voltage occurring in the semiconductor substrate within the edge region with respect to the source potential may deviate from the drain voltage by less than 10% of a maximal source drain voltage applied to the semiconductor device 500 , for example.
  • the feedback path may comprise parts with a geometry substantially equal to a geometry of the cell compensation structures 336 .
  • the feedback path comprises at least one second doping region 540 of the first conductivity type (e.g. lightly doped) configured to be depleted before the depletion zone reaches the first doping region.
  • the second doping region 540 comprises a dimension and/or a doping concentration so that the second doping region 540 is depleted very early during the switch-off of the transistor arrangement.
  • the second doping region 540 may comprise a lateral width of less than 50% (or less than 30% or less than 20%) of a lateral width of a cell compensation region and/or may comprise a vertical depth of less than 20% (or less than 10%) of a vertical depth of a cell compensation region.
  • FIG. 5 may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more embodiments described above (e.g. FIGS. 1-4 ) or below (e.g. FIGS. 6-9 ).
  • FIGS. 6A and 6B show schematic cross sections of a part of a semiconductor device according to an embodiment.
  • the semiconductor device 600 comprises a switchable electrical structure 620 implemented on a semiconductor die.
  • the semiconductor die comprises a first doping region 630 of a first conductivity type within a semiconductor substrate 610 .
  • the first doping region 630 is arranged within the semiconductor substrate 610 so that the first doping region 630 floats during at least a part of a transition from an on-state of the switchable electrical structure 620 to an off-state of the switchable electrical structure 620 until a depletion zone 640 reaches the first doping region 630 .
  • the semiconductor die comprises a feedback path 650 configured to enable a reflow of charge carriers during transition from the off-state of the switchable electrical structure 620 to the on-state of the switchable electrical structure 620 (see arrow in FIG. 6B ).
  • the feedback path 650 is configured to block a flow of charge carriers through the feedback path 650 during at least a part of a transition from an on-state of the switchable electrical structure 620 to an off-state of the switchable electrical structure 620 .
  • the output capacitance may be adapted by implementing the first doping region. For example, an output capacitance maximum may be implemented at a desired voltage. In this way, ringing and/or EMI may be reduced.
  • the output capacitance may be increased at the region of low voltages at which the output capacitance strongly decreases for increasing voltage (e.g. at voltages between 25V and 50V in FIG. 2 ). By increasing the output capacitance in this region, the smoothness of switching may be improved.
  • FIGS. 6A and 6B may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more embodiments described above (e.g. FIGS. 1-5 ) or below (e.g. FIGS. 7-9 ).
  • FIG. 7 shows a schematic cross section of a part of a semiconductor device according to an embodiment.
  • the semiconductor device 700 comprises a semiconductor substrate 710 comprising a cell region 720 laterally surrounded by an edge termination region 730 .
  • the edge termination region 730 is configured to support or block a maximal operating voltage difference applied to the semiconductor device 700 during normal operation between the cell region 720 and an edge of the semiconductor substrate.
  • the semiconductor substrate 710 comprises a first doping region 740 located at an area within the edge termination region 730 comprising between 20% and 80% of the maximal operating voltage difference if the maximal operating voltage difference is applied to the semiconductor device 700 .
  • the first doping region 740 is electrically connected by an electrically conductive structure 750 inside or outside the semiconductor substrate 710 to a capacitance increasing structure 760 located within a region of the edge termination region 730 comprising a voltage difference of at least 90% of the maximal operating voltage difference to a region (e.g. source region) within the cell region 720 .
  • a doping region with high capacitance may be implemented at desired position within the edge termination region, although only limited space may be available at the desired position.
  • the structure built by the first doping region 740 , the capacitance increasing structure 760 and the electrically conductive structure 750 connecting the first doping region 740 and the capacitance increasing structure 760 may be electrically floating or at least floating during a part of a transition of the semiconductor device from an on-state to an off-state.
  • the capacitance increasing structure 760 may be implemented by at least one second doping region comprising a conductivity type opposite to a conductivity type of semiconductor material of the semiconductor substrate surrounding the at least one second doping region or is implemented by at least one trench filled with electrically conductive material electrically insulated from the semiconductor substrate by an insulation layer within the trench.
  • FIG. 7 may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more embodiments described above (e.g. FIGS. 1-6 ) or below (e.g. FIGS. 8-9 ).
  • FIG. 8 shows a flow chart for forming a semiconductor device according to an embodiment.
  • the method 800 comprises forming 810 a semiconductor device comprising an output capacitance characteristic with at least one output capacitance maximum located at a voltage larger than 5% of a breakdown voltage of the semiconductor device.
  • the output capacitance maximum is larger than 1.2 times an output capacitance at an output capacitance minimum located at a voltage between the voltage at the output capacitance maximum and 5% of a breakdown voltage of the semiconductor device.
  • FIG. 8 may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more embodiments described above (e.g. FIGS. 1-7 ) or below (e.g. FIG. 9 ).
  • FIG. 9 shows a flow chart for forming semiconductor device comprising a switchable electrical structure implemented on a semiconductor die according to an embodiment.
  • the method 900 comprises forming 910 a first doping region of a first conductivity type within a semiconductor substrate.
  • the first doping region is arranged within the semiconductor substrate so that the first doping region floats during at least a part of a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure until a depletion zone reaches the first doping region.
  • At least a part of free charge carriers existing within the first doping region are removed from the first doping region as soon as the depletion zone reaches the first doping region.
  • the method comprises forming 920 a feedback path configured to enable a reflow of charge carriers during transition from the off-state of the switchable electrical structure to the on-state of the switchable electrical structure.
  • the feedback path is configured to block a flow of charge carriers through the feedback path during at least a part of a transition from an on-state of the switchable electrical structure to an off-state of the switchable electrical structure.
  • the structure built by the first doping region, the capacitance increasing structure 760 and the electrically conductive structure may be implemented as shown in FIG. 4 .
  • the structure built by the first doping region, the capacitance increasing structure 760 and the electrically conductive structure may be a doping region extending from the edge termination region comprising between 20% and 80% of the maximal operating voltage difference to the region of the edge termination region comprising a voltage difference of at least 90% of the maximal operating voltage difference to the region within the cell region.
  • the electrically conductive structure may be implemented inside the semiconductor substrate.
  • FIG. 9 may comprise one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more embodiments described above (e.g. FIGS. 1-7 ).
  • Some embodiments relate to a method for forming a semiconductor device comprising a semiconductor substrate comprising a cell region laterally surrounded by an edge termination region.
  • the edge termination region is configured to support or bear a maximal operating voltage difference applied to the semiconductor device during normal operation between the cell region and an edge of the semiconductor substrate.
  • the semiconductor substrate comprises a first doping region located at an area within the edge termination region comprising between 20% and 80% of the maximal operating voltage difference if the maximal operating voltage difference is applied to the semiconductor device.
  • the first doping region is electrically connected by an electrically conductive structure inside or outside the semiconductor substrate to a capacitance increasing structure located within a region of the edge termination region comprising a voltage difference of at least 90% of the maximal operating voltage difference to a region within the cell region.
  • a superjunction transistor with dynamic capacitance maximum at C oss may be provided by implementing single pillars (e.g. at the edge or below the gate pad) which may be charged as soon as the depletion zone hits the pillars at a threshold voltage and may be discharged during switch-on of the CoolMOSTM by a discharge device (e.g. diode).
  • a discharge device e.g. diode
  • floating pillars may be discharged by holes injected by the body diode.
  • the discharge device may be implemented by early deplete-able p-regions outside the edge pillars and connect floating pillars with connected pillars there.
  • the p-regions may be near-surface regions or very small implemented p-pillars (or small spots).
  • a JFET junction field effect transistor
  • the deplete-able p-regions may implement a kind of JFET.
  • Floating p-pillars may be located below the gate pad as well.
  • a shallow p-region may be used which may be connected to (capacitance) p-pillars or dielectric (trench-) capacitances (e.g. outside the edge or edge termination region).
  • the gates may be implemented as trench gates. The proposed concept may be applicable to non-superjunction transistors as well.
  • a semiconductor device may comprise a breakdown voltage of more than 10 V (e.g. between 100 V and 10000 V or more than 200 V, more than 500 V or more than 1000 V).
  • Example embodiments may further provide a computer program having a program code for performing one of the above methods, when the computer program is executed on a computer or processor.
  • a person of skill in the art would readily recognize that acts of various above-described methods may be performed by programmed computers.
  • some example embodiments are also intended to cover program storage devices, e.g., digital data storage media, which are machine or computer readable and encode machine-executable or computer-executable programs of instructions, wherein the instructions perform some or all of the acts of the above-described methods.
  • the program storage devices may be, e.g., digital memories, magnetic storage media such as magnetic disks and magnetic tapes, hard drives, or optically readable digital data storage media.
  • any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the disclosure.
  • any flow charts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.
  • each claim may stand on its own as a separate embodiment. While each claim may stand on its own as a separate embodiment, it is to be noted that—although a dependent claim may refer in the claims to a specific combination with one or more other claims—other embodiments may also include a combination of the dependent claim with the subject matter of each other dependent or independent claim. Such combinations are proposed herein unless it is stated that a specific combination is not intended. Furthermore, it is intended to include also features of a claim to any other independent claim even if this claim is not directly made dependent to the independent claim.
  • a single act may include or may be broken into multiple sub acts. Such sub acts may be included and part of the disclosure of this single act unless explicitly excluded.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
US15/142,211 2015-04-30 2016-04-29 Semiconductor Devices and Methods for Forming a Semiconductor Device Abandoned US20160322491A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US16/210,624 US10770578B2 (en) 2015-04-30 2018-12-05 Semiconductor devices and methods for forming a semiconductor device
US16/985,758 US11515414B2 (en) 2015-04-30 2020-08-05 Semiconductor devices and methods for forming a semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102015106707.2A DE102015106707A1 (de) 2015-04-30 2015-04-30 Halbleiterbauelemente und Verfahren zum Bilden eines Halbleiterbauelements
DE102015106707.2 2015-04-30

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/210,624 Continuation US10770578B2 (en) 2015-04-30 2018-12-05 Semiconductor devices and methods for forming a semiconductor device

Publications (1)

Publication Number Publication Date
US20160322491A1 true US20160322491A1 (en) 2016-11-03

Family

ID=57135458

Family Applications (3)

Application Number Title Priority Date Filing Date
US15/142,211 Abandoned US20160322491A1 (en) 2015-04-30 2016-04-29 Semiconductor Devices and Methods for Forming a Semiconductor Device
US16/210,624 Active US10770578B2 (en) 2015-04-30 2018-12-05 Semiconductor devices and methods for forming a semiconductor device
US16/985,758 Active 2036-05-27 US11515414B2 (en) 2015-04-30 2020-08-05 Semiconductor devices and methods for forming a semiconductor device

Family Applications After (2)

Application Number Title Priority Date Filing Date
US16/210,624 Active US10770578B2 (en) 2015-04-30 2018-12-05 Semiconductor devices and methods for forming a semiconductor device
US16/985,758 Active 2036-05-27 US11515414B2 (en) 2015-04-30 2020-08-05 Semiconductor devices and methods for forming a semiconductor device

Country Status (3)

Country Link
US (3) US20160322491A1 (de)
CN (1) CN106098744A (de)
DE (1) DE102015106707A1 (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190393334A1 (en) * 2018-06-26 2019-12-26 Infineon Technologies Dresden GmbH & Co. KG Method for Producing a Semiconductor Arrangement
DE102018010349B4 (de) 2018-06-26 2024-06-27 Infineon Technologies Dresden GmbH & Co. KG Halbleiterbauelement

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3719848A1 (de) 2019-04-03 2020-10-07 Infineon Technologies Dresden GmbH & Co . KG Halbleiterbauelement

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110220992A1 (en) * 2010-03-15 2011-09-15 Renesas Electronics Corporation Semiconductor device
WO2015098237A1 (ja) * 2013-12-27 2015-07-02 トヨタ自動車株式会社 縦型半導体装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4774580B2 (ja) * 1999-08-23 2011-09-14 富士電機株式会社 超接合半導体素子
DE10100802C1 (de) * 2001-01-10 2002-08-22 Infineon Technologies Ag Halbleiterbauelement mit hoher Avalanchefestigkeit und dessen Herstellungsverfahren
DE102005023026B4 (de) 2005-05-13 2016-06-16 Infineon Technologies Ag Leistungshalbleiterbauelement mit Plattenkondensator-Struktur
JP4189415B2 (ja) * 2006-06-30 2008-12-03 株式会社東芝 半導体装置
DE102006047489B9 (de) * 2006-10-05 2013-01-17 Infineon Technologies Austria Ag Halbleiterbauelement
JP5196766B2 (ja) * 2006-11-20 2013-05-15 株式会社東芝 半導体装置
US7977737B2 (en) 2008-03-06 2011-07-12 Infineon Technologies Austria Ag Semiconductor device having additional capacitance to inherent gate-drain or inherent drain-source capacitance
US7973359B2 (en) 2008-08-19 2011-07-05 Infineon Technologies Austria Ag Semiconductor device with a charge carrier compensation structure and process
US8482029B2 (en) * 2011-05-27 2013-07-09 Infineon Technologies Austria Ag Semiconductor device and integrated circuit including the semiconductor device
WO2013008543A1 (ja) * 2011-07-14 2013-01-17 富士電機株式会社 高耐圧半導体装置
JP5999748B2 (ja) * 2011-08-12 2016-09-28 ルネサスエレクトロニクス株式会社 パワーｍｏｓｆｅｔ、ｉｇｂｔおよびパワーダイオード
JP6197294B2 (ja) * 2013-01-16 2017-09-20 富士電機株式会社 半導体素子
US8946817B2 (en) * 2013-04-15 2015-02-03 Infineon Technologies Austria Ag Semiconductor device with compensation regions
US10770758B2 (en) * 2015-10-21 2020-09-08 Lg Chem, Ltd. Cable-type secondary battery including winding core having guide portions

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110220992A1 (en) * 2010-03-15 2011-09-15 Renesas Electronics Corporation Semiconductor device
WO2015098237A1 (ja) * 2013-12-27 2015-07-02 トヨタ自動車株式会社 縦型半導体装置
JP2015126192A (ja) * 2013-12-27 2015-07-06 株式会社豊田中央研究所 縦型半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190393334A1 (en) * 2018-06-26 2019-12-26 Infineon Technologies Dresden GmbH & Co. KG Method for Producing a Semiconductor Arrangement
US10971620B2 (en) * 2018-06-26 2021-04-06 Infineon Technologies Dresden GmbH & Co. KG Method for producing a semiconductor arrangement
DE102018010349B4 (de) 2018-06-26 2024-06-27 Infineon Technologies Dresden GmbH & Co. KG Halbleiterbauelement

Also Published As

Publication number Publication date
US11515414B2 (en) 2022-11-29
DE102015106707A1 (de) 2016-11-03
US10770578B2 (en) 2020-09-08
US20200365723A1 (en) 2020-11-19
CN106098744A (zh) 2016-11-09
US20190115467A1 (en) 2019-04-18

Similar Documents

Publication Publication Date Title
US10157983B2 (en) Vertical power MOS-gated device with high dopant concentration N-well below P-well and with floating P-islands
US9093522B1 (en) Vertical power MOSFET with planar channel and vertical field plate
US9490250B2 (en) Half-bridge circuit with a low-side transistor and a level shifter transistor integrated in a common semiconductor body
US11515414B2 (en) Semiconductor devices and methods for forming a semiconductor device
US10886396B2 (en) Transistor structures having a deep recessed P+ junction and methods for making same
CN108899370B (zh) 集成电阻区的vdmos器件
US8247874B2 (en) Depletion MOS transistor and charging arrangement
US10354992B2 (en) Semiconductor devices and methods for forming a semiconductor device
US10217830B2 (en) Semiconductor device having trenches with enlarged width regions
JPWO2011039888A1 (ja) 半導体装置
US11101375B2 (en) Semiconductor device and method of controlling same
US20120286323A1 (en) Semiconductor component with improved softness
US9704954B2 (en) Semiconductor device and a method for forming a semiconductor device
KR20150061202A (ko) 전력 반도체 소자
KR101539880B1 (ko) 전력 반도체 소자
US10096704B2 (en) Semiconductor device having a non-depletable doping region
JP6627452B2 (ja) 半導体装置
KR20150069117A (ko) 전력 반도체 소자
KR102004768B1 (ko) 전력 반도체 소자
KR20160016520A (ko) 반도체 장치
KR20150061972A (ko) 전력 반도체 소자
KR20180057404A (ko) 전력 반도체 소자 및 그 제조방법

Legal Events

Date Code Title Description
AS Assignment

Owner name: INFINEON TECHNOLOGIES AUSTRIA AG, AUSTRIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HIRLER, FRANZ;REEL/FRAME:038630/0542

Effective date: 20160517

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO PAY ISSUE FEE