US20130328105A1 - Narrow active cell ie type trench gate igbt and a method for manufacturing a narrow active cell ie type trench gate igbt - Google Patents

Narrow active cell ie type trench gate igbt and a method for manufacturing a narrow active cell ie type trench gate igbt Download PDF

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US20130328105A1
US20130328105A1 US13/903,068 US201313903068A US2013328105A1 US 20130328105 A1 US20130328105 A1 US 20130328105A1 US 201313903068 A US201313903068 A US 201313903068A US 2013328105 A1 US2013328105 A1 US 2013328105A1
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Hitoshi Matsuura
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Renesas Electronics Corp
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Renesas Electronics Corp
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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    • H—ELECTRICITY
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    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths

Definitions

  • the present invention relates to a semiconductor device (or a semiconductor integrated circuit device), and a method for manufacturing a semiconductor device (or a semiconductor integrated circuit device). More particularly, it relates to a technology effectively applicable to an IGBT device technology and a method for manufacturing an IGBT.
  • Patent Document 1 Japanese Unexamined Patent Publication No. Hei 11 (1999)-345969 (Patent Document 1) relates to an equal-width active cell IE (Injection Enhance) type IGBT (Integrated Gate Bipolar Transistor) having equidistant trenches.
  • This document discloses therein a device structure in which an N+ type emitter region is finely divided along the longitudinal direction by P+ body contact regions (so-called “active cell two-dimensional thinned-out structure”).
  • Patent Document 2 Japanese Unexamined Patent Publication No. 2005-294649 relates to a wide active cell IE type IGBT in which the trench interval in an active cell region is larger than the trench interval in an inactive cell region.
  • This document discloses therein a technology of arranging a floating P type region extending to the trench bottom ends on the opposite sides under the inactive cell region. Incidentally, in this document, after trench formation, the floating P type region is introduced simultaneously with the P type body region.
  • an equal-width active cell IE type IGBT In an equal-width active cell IE type IGBT, a wide active cell IE type IGBT, or the like, the trench widths in an active cell region and an inactive cell region are equal to each other, or the trench width in the inactive cell region is narrower. For this reason, it is possible to ensure the breakdown voltage relatively easily. However, with such a structure, an attempt to enhance the IE effect unfavorably further complicates the structure, and causes other problems.
  • the summary of one embodiment of the present invention is a narrow active cell IE type IGBT which has an active cell two-dimensional thinned-out structure, and in which there is not arranged a body contact region in a cross section orthogonal to the substrate surface, passing through the emitter region, and orthogonal to the trenches on the opposite sides.
  • the IE effect can be enhanced while avoiding excessive complication of the device structure.
  • FIG. 1 is a top schematic layout view of a cell region and its periphery of a narrow active cell IE type trench gate IGBT device chip for illustrating the outline of the device structure in a narrow active cell IE type trench gate IGBT of main embodiments (including modified examples) of the present invention;
  • FIG. 2 is a device schematic cross-sectional view corresponding to an A-A′ cross section of a cell region end cut-out region R 1 of FIG. 1 ;
  • FIG. 3 is a device schematic cross-sectional view corresponding to a B-B′ cross section of a cell region internal cut-out region R 2 of FIG. 1 ;
  • FIG. 4 is an enlarged top view of a linear unit cell region and its periphery R 5 of FIG. 1 in accordance with one embodiment of the present invention
  • FIG. 5 is an overall top view (roughly corresponding to FIG. 1 , but close to a more specific configuration) of the narrow active cell IE type trench gate IGBT device chip of the one embodiment (also common to other embodiments and respective modified examples) of the present invention;
  • FIG. 6 is an enlarged top view of a portion corresponding to the cell region internal cut-out region R 3 of FIG. 5 for illustrating the device structure of the one embodiment (an active section dispersed structure in an active cell two-dimensional thinned-out structure) of the present invention
  • FIG. 7 is a device cross-sectional view corresponding to a C-C′ cross section of FIG. 6 ;
  • FIG. 8 is a device cross-sectional view corresponding to a D-D′ cross section of FIG. 6 ;
  • FIG. 9 is a device cross-sectional view corresponding to an E-E′ cross section of FIG. 6 ;
  • FIG. 10 is a device cross-sectional view in a manufacturing step (hole barrier region introduction step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 11 is a device cross-sectional view in a manufacturing step (P type floating region introduction step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 12 is a device cross-sectional view in a manufacturing step (trench processing hard mask deposition step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 13 is a device cross-sectional view in a manufacturing step (trench hard mask processing step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 14 is a device cross-sectional view in a manufacturing step (trench processing step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 15 is a device cross-sectional view in a manufacturing step (trench processing hard mask removing step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 16 is a device cross-sectional view in a manufacturing step (drive-in diffusion and gate oxidation step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 17 is a device cross-sectional view in a manufacturing step (gate polysilicon etching back step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 18 is a device cross-sectional view in a manufacturing step (P type body region and N+ type emitter region introduction step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 19 is a device cross-sectional view in a manufacturing step (P+ type body contact region and P+ type buried body contact region introduction step) corresponding to FIG. 8 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 20 is a device cross-sectional view in a manufacturing step (interlayer insulation film deposition step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 21 is a device cross-sectional view in a manufacturing step (contact hole formation step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 22 is a device cross-sectional view in a manufacturing step (surface metal deposition step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 23 is a device cross-sectional view in a manufacturing step (back surface girding and back surface impurity introduction step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 24 is a device cross-sectional view in a manufacturing step (back surface metal electrode formation step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention
  • FIG. 25 is a local detailed cross-sectional view of the device back surface for a detailed description on the back surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention, or for illustrating the device structure and the manufacturing method of a modified example (aluminum-doped structure);
  • FIG. 26 is an enlarged top view corresponding to FIG. 6 , for illustrating Modified Example 1 (N+ type surface floating region & P+ type surface floating region addition structure) regarding the surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention;
  • FIG. 27 is a device cross-sectional view corresponding to a F-F′ cross section of FIG. 26 ;
  • FIG. 28 is a device cross-sectional view corresponding to a G-G′ cross section of FIG. 26 ;
  • FIG. 29 is a device cross-sectional view corresponding to the C-C′ cross section of FIG. 6 corresponding to FIG. 7 for illustrating Modified Example 2 (simplified active cell structure) regarding the surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention;
  • FIG. 30 is a device schematic cross-sectional view of the A-A′ cross section of the cell region end cut-out region R 1 of FIG. 1 corresponding to FIG. 2 for illustrating Modified Example (hole collector cell addition structure) regarding the surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention;
  • FIG. 31 is an enlarged top view of the linear unit cell region and its periphery R 5 of FIG. 1 for illustrating Modified Example 3 (hole collector cell addition structure) regarding the surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention;
  • FIG. 32 is an enlarged top view corresponding to FIG. 6 for illustrating Modified Example 3 (hole collector cell addition structure) regarding the surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention
  • FIG. 33 is a device cross-sectional view corresponding to a H-H′ cross section of FIG. 32 ;
  • FIG. 34 is a device cross-sectional view corresponding to a J-J′ cross section of FIG. 32 ;
  • FIG. 35 is a device cross-sectional view corresponding to a K-K′ cross section of FIG. 32 ;
  • FIG. 36 is an enlarged top view of the linear unit cell region and its periphery R 5 of FIG. 1 for illustrating the outline of the device structure of the one embodiment of the present invention.
  • a narrow active cell IE type trench gate IGBT includes:
  • a metal emitter electrode arranged over the first main surface of the silicon type semiconductor substrate, and electrically coupled to the emitter region and the body contact region.
  • the body contact region is arranged over almost the entire region of the each inactive section.
  • the narrow active cell IE type trench gate IGBT according to the item 1 or 2 further includes:
  • the narrow active cell IE type trench gate IGBT according to any one of the items 1 to 3, further includes:
  • the narrow active cell IE type trench gate IGBT according to any one of the items 1 to 4, further includes:
  • the interval between the trenches on the opposite sides of the each linear active cell region is 0.35 micrometer or less.
  • the width in the longitudinal direction of the each active section is 0.5 micrometer or less.
  • the narrow active cell IE type trench gate IGBT according to any one of the items 1 to 7, further includes:
  • the narrow active cell IE type trench gate IGBT according to any one of the items 1 to 8, further includes:
  • the narrow active cell IE type trench gate IGBT according to any one of the items 1 to 9, further includes:
  • the narrow active cell IE type trench gate IGBT according to any one of the items 1 to 10, further includes:
  • a portion of the metal collector electrode in contact with the aluminum doped region is a back surface metal film including aluminum as a main component.
  • a method for manufacturing a narrow active cell IE type trench gate IGBT which includes:
  • drift region having a first conductivity type, arranged from the inside to the first main surface in almost the entire region of the silicon type semiconductor wafer;
  • a metal emitter electrode arranged over the first main surface of the silicon type semiconductor wafer, and electrically coupled to the emitter region and the body contact region.
  • the method includes the following steps:
  • the method for manufacturing a narrow active cell IE type trench gate IGBT according to the item 12, further includes a step of:
  • the step (x1) is also used for introducing second conductivity type impurities for forming a floating field ring arranged in the peripheral outside of the IGBT cell region.
  • the method for manufacturing a narrow active cell IE type trench gate IGBT according to any one of the items 12 to 14, further includes a step of:
  • step (x7) after the step (x5), introducing first conductivity type impurities for forming the emitter region.
  • the method for manufacturing a narrow active cell IE type trench gate IGBT according to the item 15, further includes a step of:
  • the embodiment may be described in a plurality of divided sections for convenience, if required. However, unless otherwise specified, these are not independent of each other, but are respective portions of a single example, or are in a relation such that one is details of a part, a modified example, or the like of a part or the whole of the other. Further, in principle, description on the similar portions is not repeated. Furthermore, respective structural elements in embodiments are not essential, unless otherwise specified, and except when they are theoretically limited to the numbers, and unless otherwise apparent from the context.
  • semiconductor device used in the present invention embraces, mainly, various transistors (active elements) alone, or the one obtained by integrating resistors, capacitors, and the like around them as the center over a semiconductor chip or the like (for example, single crystal silicon substrate), and the one obtained by packaging semiconductor chips and the like.
  • representative examples of the various transistors may include MOSFETs (Metal Insulator Semiconductor Field Effect Transistors) typified by MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).
  • representative examples of the various single transistors may include power MOSFETs and IGBTs (Insulated Gate Bipolar Transistors). These are generally classified into power semiconductor devices, which include therein, other than power MOSFETs and IGBTs, bipolar power transistors, thyristors, power diodes, and the like.
  • the power MOSFET is a double diffused vertical power MOSFET including a source electrode at the front surface, and a drain electrode at the back surface.
  • the double diffused vertical power MOSFETs can be mainly classified into two kinds. The first is a planar gate type mainly described in embodiments, and the second is a trench gate type such as U-MOSFET.
  • the power MOSFETs includes, other than these, LD-MOSFETs (lateral-diffused MOSFETs).
  • X including A for the material, composition, or the like does not exclude the one including an element other than A as a main structural element unless otherwise specified and unless otherwise apparent from the context.
  • the term is used to embrace “X including A as a main component”, and the like.
  • silicon member or the like herein used is not limited to pure silicon but also embraces a SiGe alloy, other multinary alloys containing silicon as a main component, and other members containing additives, and the like.
  • silicon oxide film “silicon oxide type insulation film”, and the like are used to embrace insulation films including not only relatively pure undoped silicon dioxide, but also other silicon oxides as main components.
  • impurity-doped silicon oxide type insulation films such as TEOS-based silicon oxide, PSG (phosphorus silicate glass), and BPSG (borophosphosilicate glass) are also silicon oxide films.
  • coating type films such as SOG (Spin On Glass) and NSC (nano-clustering silica) are also silicon oxide films or silicon oxide type insulation films.
  • a low-k insulation film such as FSG (fluorosilicate glass), SiOC (Silicon Oxicarbide), carbon-doped silicon oxide, or OSG (organosilicate glass) is also similarly a silicon oxide film or a silicon oxide type insulation film.
  • FSG fluorosilicate glass
  • SiOC Sicon Oxicarbide
  • OSG organosilicate glass
  • silica type low-k insulation films obtained by introducing holes into the same members as these (porous type insulation films, the “porous” herein used also embraces molecular porous) are also silicon oxide films or silicon oxide type insulation films
  • silicon type insulation films which are commonly used along with silicon oxide type insulator films in the field of semiconductors include silicon nitride type insulation films.
  • Materials belonging to such a group include SiN, SiCN, SiNH, SiCNH, or the like.
  • the term “silicon nitride” herein used embraces both SiN and SiNH unless otherwise specified.
  • each numerical value may be a numerical value of more than the specific numerical value, or may be a numerical value of less than the specific numerical value.
  • wafer herein used generally refers to a single crystal silicon wafer over which a semiconductor device (which may be a semiconductor integrated circuit device or an electronic device) is to be formed. However, it is naturally understood that the term also embraces a composite wafer of insulation substrate such as an epitaxial wafer, a SOI substrate, or a LCD glass substrate, and a semiconductor layer or the like.
  • IGBTs are largely classified into a planar gate type and a trench gate type.
  • the trench gate type IGBT has a relatively lower ON resistance.
  • an IE type trench gate IGBT or “active cell thinned-out type trench gate IGBT”) utilizing the IE (Injection Enhancement) effect.
  • the IE type trench gate IGBT has the following structure: in the cell region, active cells actually coupled to an emitter electrode, and inactive cells having P type floating regions are arranged alternately, or in the form of the teeth of a comb, thereby to facilitate the accumulation of holes on the device main surface side (emitter side) of a semiconductor substrate.
  • the P type floating region is not essential.
  • the presence of a P type floating region i.e., a P type deep floating region having a depth enough to cover the lower ends of the trenches on the opposite sides provides a merit of facilitating breakdown voltage design.
  • the first is an intrinsic active cell which actually has an N+ emitter region, and in which a trench gate electrode is electrically coupled to a metal gate electrode (specifically, a linear active cell region).
  • the second is a pseud active cell which does not have an N+ emitter region, and in which a trench gate electrode is electrically coupled to a metal emitter electrode (specifically, a linear hole collector cell region).
  • the term in which the width of the main active cell is narrower than the width of the main inactive cell is referred to as a “narrow active cell IE type trench gate IGBT”. More generally, the term refers to the one in which the pitch between the trenches (the distance between the trench centers) of the active cell is narrower than the pitch between trenches of the inactive cell.
  • the direction crossing the trench gate is referred to as a “width direction of the cell” and the direction of extension (longitudinal direction) of the trench gate (linear gate portion) orthogonal thereto is referred to as a “length direction of the cell”.
  • the present invention mainly deals with the “linear unit cell region” (including, for example, the linear active cell region and the linear inactive cell region).
  • the linear unit cell regions are arrayed in a periodically repeating manner in the inside region of the semiconductor chip, to form a “cell formation region”, i.e., an “IGBT cell region”.
  • a cell peripheral junction region Around the cell region, generally, there is arranged a cell peripheral junction region. Further, therearound, a floating field ring or a field limiting ring, and the like are arranged, thereby to form a termination structure.
  • a floating field ring or field limiting ring refers to the following.
  • the term refers to an impurity region or an impurity region group arranged apart from a P type body region (P type well region) in the front surface (device surface) of the drift region, having the same conductivity type as that, and the similar concentration to that (which is a concentration enough to prevent full depletion when the main junction is applied with a reverse voltage), and surrounding the cell region in one-fold or multi-fold (e.g., about 10-fold) rings.
  • the field plate is a conductor film pattern coupled to the floating field ring, and refers to a portion which extends over the front surface (device surface) of the drift region via an insulation film, and surrounds the cell region in a ring.
  • the linear unit cell region as a periodical element forming the cell region refers to the following, for example, in the example of FIG. 5 .
  • the one in which half-width linear inactive cell regions are arranged on the opposite sides of the linear active cell region as the center is rationally treated as a set.
  • the linear inactive cell regions are individually described, they are inconveniently separated to opposite sides. For this reason, in that case, a specific integral portion is referred to as a linear inactive cell region.
  • a “contact substrate trench” commonly used for implementing an “ultra-narrow active region” is not formed, but a contact trench is formed in the interlayer insulation film over a flat substrate surface.
  • the term “ultra-narrow active region” refers to the one having a distance between the inner sides of the trenches on the opposite sides of the active cell region, namely, a width of the active region between trenches of 0.35 micrometer or less.
  • the one having a width in the longitudinal direction of the active section (referred to as an “active section width”) of 0.5 micrometer or less is referred to as an “ultra-narrow active section”.
  • hatching or the like may be omitted even in cross section when it rather complicates the drawing, or when it is apparently distinct from the gap.
  • the background outline may be omitted.
  • hatching may be added in order to clearly demonstrate that the part is not a gap.
  • first when one is referred to as “first”, and the other is referred to as “second”, or the like, they may be exemplified correspondingly in accordance with representative embodiments. However, it is naturally understood that, for example, even the term “first” is not limited to the exemplified alternatives.
  • FIGS. 2 and 3 in order to ensure the simplicity of the wide area view, the structure of some impurity region is shown in a largely simplified form (for the detailed structure, see, e.g., FIG. 4 ).
  • FIG. 1 is a top schematic layout view of a cell region and its periphery of a narrow active cell IE type trench gate IGBT device chip for illustrating the outline of the device structure in a narrow active cell IE type trench gate IGBT of main embodiments (including modified examples) of the present invention.
  • FIG. 2 is a device schematic cross-sectional view corresponding to an A-A′ cross section of a cell region end cut-out region R 1 of FIG. 1 .
  • FIG. 3 is a device schematic cross-sectional view corresponding to a B-B′ cross section of a cell region internal cut-out region R 2 of FIG. 1 .
  • FIG. 4 is an enlarged top view of a linear unit cell region and its periphery R 5 of FIG. 1 in accordance with one embodiment of the present invention. Based on these, a description will be given to the outline of the device structure in the narrow active cell IE type trench gate IGBT in the main embodiment (including a modified example).
  • FIG. 1 shows the top view of the inside region (the portion inside a guard ring or the like which is the outermost part of the termination structure, i.e., the main part of a chip 2 ) of the IE type trench gate IGBT which is the main object of the present invention.
  • the main part of the internal region of the chip 2 semiconductor substrate
  • IGBT cell region 10 In the outer circumferential part of the cell region 10 , a ring-shaped and P type cell peripheral junction region 35 is arranged in such a manner as to surround this.
  • a single or a plurality of ring-shaped and P type floating field rings 36 are arranged at an interval, and form a termination structure for the cell region 10 together with the cell peripheral junction region 35 , a guard ring 4 (see FIG. 5 ), and the like.
  • a large number of linear unit cell regions 40 are spread.
  • the end regions thereof there are arranged a pair of or more (for one side, one row or about several rows) of dummy cell regions 34 (linear dummy cell regions).
  • FIG. 2 shows the A-A′ cross section of the cell region end cut-out region R 1 of FIG. 1 .
  • the semiconductor region in this example, silicon single crystal region
  • the back surface 1 b the back side main surface or the second main surface of the semiconductor substrate
  • a P+ type collector region 18 Over the surface, there is arranged a metal collector electrode 17 .
  • an N ⁇ type drift region 20 first conductivity type drift region
  • the P+ type collector region 18 second conductivity type collector region
  • trench gate electrodes 14 are embedded via a gate insulation film 22 , respectively.
  • the trench gate electrodes 14 are coupled via a metal gate wire 7 to a metal gate electrode 5 (see FIG. 5 ).
  • the trenches 21 perform a function of defining respective regions.
  • a dummy cell region 34 is defined from opposite sides thereof by a pair of trenches 21 .
  • One trench 21 of these defines the cell region 10 and the cell peripheral junction region 35 .
  • the cell peripheral junction region 35 is coupled via a P+ type body contact region 25 p to a metal emitter electrode 8 .
  • the thickness of the gate insulation film 22 at any portion of the trench is assumed to be roughly equal (however, it is not excluded that, if required, a given portion is different in thickness from other portions).
  • an emitter contact is established in the cell peripheral junction region 35 and the dummy cell region 34 .
  • the degree of freedom for design is improved.
  • a P type floating field ring 36 In the semiconductor region on the front surface side 1 a of the N ⁇ type drift region 20 outside the cell peripheral junction region 35 , there is arranged a P type floating field ring 36 . Over the front surface 1 a , a field plate 4 is arranged, and is coupled via a P+ type body contact region 25 r to the floating field ring 36 .
  • the dummy cell region 34 is basically equal in both structure and size to the linear active cell region 40 a except for not having an N+ type emitter region 12 .
  • a P+ type body contact region 25 d arranged in the front surface of the P type body region 15 is coupled to the metal emitter electrode 8 .
  • the linear unit cell region 40 as the unit cell includes the linear active cell region 40 a , and half-width linear inactive cell regions 40 i on the opposite sides thereof. However, specifically, it can be seen that full-width linear inactive cell region 40 i is arranged between the adjacent linear active cell regions 40 a (see FIG. 4 ).
  • the P type body region 15 In the semiconductor surface region on the front side main surface 1 a (first main surface) side of the semiconductor substrate of the linear active cell region 40 a , there is arranged the P type body region 15 . In the front surface thereof, there are arranged an N+ type emitter region 12 (first conductivity type emitter region) and a P+ type body contact region 25 . The N+ type emitter region 12 and the P+ type body contact region 25 are coupled to the metal emitter electrode 8 . In the linear active cell region 40 a , in the N ⁇ type drift region 20 under the P type body region 15 , there is arranged an N type hole barrier region 24 .
  • the N type hole barrier region 24 when the N type hole barrier region 24 is arranged, in principle, from the two-dimensional viewpoint, it is arranged in almost the entire region of the linear active cell region 40 a . Incidentally, it is naturally understood that this is not essential, and can also be partially arranged, if required.
  • the P type body region 15 is arranged in the front side main surface 1 a (first main surface) side semiconductor surface region of the semiconductor substrate in the linear inactive cell region 40 i .
  • the P type body region 15 is arranged in the underlying N ⁇ type drift region 20 .
  • a P type floating region 16 (second conductivity type floating region) covering the lower ends of the trenches 21 on the opposite sides, and deeper than them.
  • the layout is adjusted in order to optimize the characteristics such as the gate capacity, ON voltage, and switching characteristics, there is no fear of the reduction of the breakdown voltage, and the degree of freedom for design can be ensured.
  • the concentration of the N type hole barrier region 24 is increased for optimization, similarly, there is almost no effect on the breakdown voltage. As a result of this, it becomes possible to effectively enhance or control the hole accumulation effect.
  • the IE type trench gate IGBT there is not formed a contact from the emitter electrode 8 to the P type floating region 16 .
  • the width Wa of the linear active cell region 40 a is set narrower than the width Wi of the linear inactive cell region 40 i .
  • this is referred to as a “narrow active cell type unit cell”.
  • a device having the narrow active cell type unit cell will be specifically described.
  • the present invention is not limited thereto. It is naturally understood that the present invention is also applicable to a device having a “non-narrow active cell type unit cell”.
  • the linear active cell regions 40 a and the linear inactive cell regions 40 i are alternately arrayed to form the linear unit cell region 40 .
  • This configuration is referred to as an “alternate array system” in the present invention.
  • an alternate array system in the present invention.
  • a description will be given on the premise of the alternate array system.
  • the “non-alternate array system” is also acceptable.
  • FIG. 2 a description was given to the main part exemplarily including respective portions of various embodiments of the present invention. However, in the following description, these are divided into structural elements such as a cell part (cross-sectional or planar structure), and a cell peripheral part to be described. However, these are not individually independent of one another. As shown in FIG. 2 , various modified examples substitute for respective structural elements to form the main part. This is not limited to FIG. 2 , and can also apply to the subsequent FIG. 3 .
  • FIG. 2 alternative array system
  • the one obtained by substituting every other active cell with a hole collector cell is the structure shown in FIG. 30 or the like.
  • the same substitution can also be carried out in the non-alternate array system as in FIG. 3 .
  • FIG. 3 shows a specific example of the linear unit cell region 40 of the non-alternate array system.
  • the number of the linear inactive cell regions 401 to be inserted in between the adjacent linear active cell regions 40 a is one.
  • the number of the linear inactive sub-cell regions 40 is (device element corresponding to the linear inactive cell region 40 i of FIG. 2 ) to be inserted in between the adjacent linear active cell regions 40 a is plural.
  • the width Wa of the linear active cell region 40 a is set narrower than the width Wis of the linear inactive sub-cell region 40 is.
  • this is referred to as a “narrow active cell type unit cell”.
  • the definition of the narrow active cell type unit cell is done not by the width Wi of the linear inactive cell region 40 i but by the width Wis of the linear inactive sub-cell region 40 is.
  • the number (which will be hereinafter referred to as an “insertion number”) of the linear inactive sub-cell regions 40 is to be inserted in between the adjacent linear active cell regions 40 a is not required to be constant, but may be changed between one and several according to the place.
  • the insertion number may be set plural.
  • the merit of the alternate array system is as follows: the number of trenches is small, and hence the planar structure can be relatively simplified. Further, there is also a merit of preventing an inadvertent increase in gate capacity.
  • the merit of the non-alternate array system resides in that the width Wi of the relatively wider linear inactive cell region can be set without making the gate capacity too small, and without reducing the breakdown voltage. The overall design optimization may become difficult with a too small gate capacity according to the application or the gate drive conditions. For this reason, it is effective to ensure the adjustable means as device design, if required.
  • FIG. 4 shows one example of the detailed planar structure of the linear unit cell region main part and its peripheral cut-out region R 5 of FIG. 1 .
  • active sections 40 aa having a given length are arranged at a given interval, between which there is an inactive section 40 ai not including the N+ type emitter region 12 arranged therein. Namely, some portions in the length direction of the linear active cell region 40 a locally and dispersively become the active sections 40 aa . A further description will be given.
  • the active section 40 aa in almost the entire surface thereof, there is arranged the N+ type emitter region 12 .
  • inactive section 40 ai in almost the entire surface thereof, there are arranged a P+ type body contact region 25 and a P+ type buried body contact region 55 .
  • the linear inactive cell region 40 i in almost the entire surface thereof, there are arranged the P type body region 15 and the P type floating region 16 (second conductivity type floating region).
  • being distributed with a given length at a given interval means “being periodical”.
  • being substantially periodical corresponds to the local and dispersive distribution.
  • being local and dispersive is “being wider than that” and does not necessarily mean “being periodical or quasi-periodical”.
  • the chip size is 3 to 15 millimeters square.
  • the chip size largely varies according to the assumed current value.
  • a description will be given by taking a chip 4 millimeters long, and 5.2 millimeters wide as an example.
  • a description will be given by assuming the breakdown voltage of the device as, for example, about 1200 volts.
  • FIG. 5 is an overall top view (roughly corresponding to FIG. 1 , but close to a more specific configuration) of the narrow active cell IE type trench gate IGBT device chip of the one embodiment (also common to other embodiments and respective modified examples) of the present invention.
  • FIG. 6 is an enlarged top view of a portion corresponding to the cell region internal cut-out region R 3 of FIG. 5 for illustrating the device structure of the one embodiment (an active section dispersed structure in an active cell two-dimensional thinned-out structure) of the present invention.
  • FIG. 7 is a device cross-sectional view corresponding to a C-C′ cross section of FIG. 6 .
  • FIG. 8 is a device cross-sectional view corresponding to a D-D′ cross section of FIG. 6 .
  • FIG. 9 is a device cross-sectional view corresponding to an E-E′ cross section of FIG. 6 . Based on these, a description will be given to the device structure of the narrow active cell IE type trench gate IGBT in one embodiment (P type deep floating & hole barrier combination structure) of the present invention.
  • a ring-shaped guard ring 3 formed of, for example, an aluminum type wiring layer.
  • ring-shaped field plates 4 formed of, for example, the same aluminum type wiring layer as the previous one coupled to a ring-shaped floating field ring or the like.
  • the cell region 10 Inside the field plate 4 (floating field ring 36 ), and in the main part of the inside region of the top surface 1 a of the chip 2 , there is arranged the cell region 10 .
  • the top of the cell region 10 is covered to the vicinity of the outside thereof with a metal emitter electrode 8 formed of, for example, the same aluminum type wiring layer as the previous one.
  • the central part of the metal emitter electrode 8 becomes a metal emitter pad 9 to be coupled with a bonding wire or the like.
  • a metal gate wire 7 formed of, for example, the same aluminum type wiring layer as the previous one.
  • the metal gate wire 7 is coupled to the metal gate electrode 5 formed of, for example, the same aluminum type wiring layer as the previous one.
  • the central part of the metal gate electrode 5 becomes a gate pad 6 to be coupled with a bonding wire or the like.
  • FIG. 6 shows an enlarged planar layout of the cell region internal cut-out region R 3 of FIG. 5 (mainly showing the layout of the surface region of the semiconductor substrate).
  • the N+ type emitter region 12 is not formed over almost the full length of the linear active cell region 40 a .
  • the linear active cell region 40 a is almost periodically divided in the length direction thereof into active sections 40 aa each including the N+ type emitter region 12 formed therein, and inactive sections 40 ai each not including the N+ type emitter region 12 formed therein. Namely, the N+ type emitter region 12 is arranged over almost the entire surface in the active section 40 aa of the linear active cell region 40 a .
  • the P+ type body contact region 25 is arranged over almost the entire surface in the inactive section 40 ai of the linear active cell region 40 a .
  • the P type body region 15 and the P type floating region 16 are arranged over almost the entire surface thereof.
  • FIG. 7 shows the C-C′ cross section of FIG. 6 .
  • a P+ type collector region 18 and an N type field stop region 19 are formed in such a manner as to be vertically in contact with each other.
  • a metal collector electrode 17 Over the back surface 1 b of the semiconductor chip 2 , there is formed a metal collector electrode 17 .
  • the N ⁇ type drift region 20 (the semiconductor region on the front surface side of the semiconductor substrate) on the front surface 1 a (first main surface) side of the semiconductor chip 2 in the linear active cell region 40 a , there are arranged an N type hole barrier region 24 , a P type body region 15 , and an N+ type emitter region 12 sequentially from the bottom. Further, over the front surface 1 a of the semiconductor chip 2 , there is formed an interlayer insulation film 26 . In the interlayer insulation film 26 portion in the linear active cell region 40 a , there is formed a contact trench 11 (or contact hole). The N+ type emitter region 12 is coupled via the contact trench 11 and the like to the metal emitter electrode 8 arranged over the interlayer insulation film 26 .
  • the presence of the N type hole barrier region 24 is arbitrary. However, the N type hole barrier region 24 is present, and thereby acts as a hole barrier. In addition, the presence thereof has an effect of preventing the P type floating region 16 from undesirably expanding toward the linear active cell region 40 a side even when the width of the linear active cell region 40 a becomes very narrow. Further, the disposition of the N type hole barrier region 24 has a merit capable of implementing a sufficient IE effect even when the depth of the trench is not very large (e.g., about 3 micrometers). Further, there is also an effect capable of largely reducing the range of characteristic fluctuation with respect to the variation in trench depth.
  • the N type hole barrier region 24 is a barrier region for inhibiting holes from flowing into the path from the N ⁇ type drift region 20 to the N+ type emitter region 12 .
  • the impurity concentration thereof is, for example, lower than that of the N+ type emitter region 12 , and higher than that of the N ⁇ type drift region 20 .
  • the presence of the N type hole barrier region 24 can effectively inhibit the holes accumulated in the linear inactive cell region 40 i from entering into the emitter path (the path from the N ⁇ type drift region 20 toward the P+ type body contact region 25 ) in the linear active cell region 40 a .
  • the N type hole barrier region 24 is locally arranged only in the active cell region 40 a . This prevents an unnecessary increase in discharge resistance of holes at the time of switching-off, which prevents degradation of the switching characteristics.
  • a P type floating region 16 and a P type body region 15 are arranged sequentially from the bottom.
  • the depth of the P type floating region 16 is set larger than the depth of the trench 21 , and is distributed in such a manner as to cover the lower end of the trench 21 . In this manner, it is possible to effectively prevent the concentration of the electric field intensity to the lower end of the trench 21 in the off state.
  • FIG. 8 shows the D-D′ cross section of FIG. 6 .
  • this cross section is different from FIG. 7 in that the P+ type body contact region 25 is arranged over the front surface of the P type body region 15 in the linear active cell region 40 a , and in that a P+ type buried body contact region 55 is arranged in contact with the bottom in a superposed manner.
  • other portions are entirely the same as in FIG. 7 .
  • FIG. 9 shows the E-E′ cross section of FIG. 6 .
  • a P+ type collector region 18 and an N type field stop region 19 are formed in such a manner as to be vertically in contact with each other.
  • a metal collector electrode 17 Over the back surface 1 b of the semiconductor chip 2 , there is formed a metal collector electrode 17 .
  • the N type hole barrier region 24 , the P type body region 15 , and the N+ type emitter region 12 are arranged sequentially from the bottom.
  • the N type hole barrier region 24 , the P type body region 15 , the P+ type buried body contact region 55 , and the P+ type body contact region 25 are arranged sequentially from the bottom.
  • the contact trench 11 over the front surface 1 a of the semiconductor chip 2 , there is formed the contact trench 11 (or a contact hole).
  • the N+ type emitter region 12 and the P+ type body contact region 25 are coupled via the contact trench 11 and the like to the metal emitter electrode 8 .
  • the width Wa of the linear active cell region is about 1.0 micrometer
  • the width Wi of the linear inactive cell region is about 2.5 micrometers
  • the width Wa of the linear active cell region is desirably narrower than the width Wi of the linear inactive cell region, and the value of “Wi/Wa” is in particular preferably within the range of, for example, 2 to 3).
  • the contact width is about 1.0 micrometer; the trench width is about 0.7 micrometer (in particular preferably 0.8 micrometer or less); the trench depth is about 3 micrometers; the depth of the N+ type emitter region 12 is about 0.6 micrometer; and the depth of the P type body region 15 (channel region) is about 1.2 micrometers.
  • the depth of the P type floating region 16 is about 4.5 micrometers; the thickness of the N type field stop region 19 is about 1.5 micrometers; the thickness of the P+ type collector region is about 0.5 micrometer; and the thickness of the semiconductor substrate 2 is about 120 micrometers (herein, an example of a breakdown voltage of about 1200 volts is shown). Incidentally, the thickness of the semiconductor substrate 2 highly depends upon the breakdown voltage.
  • the thickness is, for example, about 70 micrometers. With a breakdown voltage of 400 volts, the thickness is, for example, about 40 micrometers. Further, the recess depth in the top surface of the trench gate electrode 14 is, for example, about 0.4 micrometer, and the distance between the opposite-side trenches in the linear active cell region 40 a (the distance between the inner sides of the trenches) is, for example, about 0.3 micrometer. The thickness of the P+ type body contact region 25 is, for example, about 0.4 micrometer; and the thickness of the P+ type buried body contact region is, for example, about 0.5 micrometer.
  • the width of the active section 40 aa in the linear active cell region 40 a is, for example, about 0.4 micrometer. Although the width of the inactive section 40 ai highly depends upon the value of the required saturation current, it is, for example, about 10 micrometers. Whereas, the resistivity of the N ⁇ type drift region 20 is, for example, about 70 ⁇ cm.
  • the width of the active section 40 aa is preferably 0.5 micrometer or less.
  • the running distance of the hole passing through the P type body region 15 under the N+ type emitter region 12 is estimated as 0.25 micrometer or less, and is at an unproblematic level in view of the latch-up resistance.
  • FIG. 10 is a device cross-sectional view in a manufacturing step (hole barrier region introduction step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 11 is a device cross-sectional view in a manufacturing step (P type floating region introduction step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 12 is a device cross-sectional view in a manufacturing step (trench processing hard mask deposition step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 13 is a device cross-sectional view in a manufacturing step (trench hard mask processing step) corresponding to FIG.
  • FIG. 14 is a device cross-sectional view in a manufacturing step (trench processing step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 15 is a device cross-sectional view in a manufacturing step (trench processing hard mask removing step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 16 is a device cross-sectional view in a manufacturing step (drive-in diffusion and gate oxidation step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 14 is a device cross-sectional view in a manufacturing step (trench processing step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 15 is a device cross-sectional view in a manufacturing step (trench processing hard mask removing step) corresponding to FIG.
  • FIG. 17 is a device cross-sectional view in a manufacturing step (gate polysilicon etching back step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 18 is a device cross-sectional view in a manufacturing step (P type body region and N+ type emitter region introduction step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 19 is a device cross-sectional view in a manufacturing step (P+ type body contact region and P+ type buried body contact region introduction step) corresponding to FIG. 8 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 18 is a device cross-sectional view in a manufacturing step (P type body region and N+ type emitter region introduction step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 19 is a
  • FIG. 20 is a device cross-sectional view in a manufacturing step (interlayer insulation film deposition step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 21 is a device cross-sectional view in a manufacturing step (contact hole formation step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 22 is a device cross-sectional view in a manufacturing step (surface metal deposition step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 21 is a device cross-sectional view in a manufacturing step (contact hole formation step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 22 is a device cross-sectional view in a manufacturing step (surface metal deposition step) corresponding to FIG. 7 for illustrating a manufacturing method
  • FIG. 23 is a device cross-sectional view in a manufacturing step (back surface girding and back surface impurity introduction step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention.
  • FIG. 24 is a device cross-sectional view in a manufacturing step (back surface metal electrode formation step) corresponding to FIG. 7 for illustrating a manufacturing method corresponding to the device structure of the one embodiment of the present invention. Based on these, a description will be give to the main manufacturing process corresponding to the method for manufacturing the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention.
  • a 200-diameter wafer (which may be each wafer with various diameters such as a diameter of 150, a diameter of 100, a diameter of 300, and a diameter of 450) of N ⁇ type silicon single crystal (e.g., phosphorus concentration: about 2 ⁇ 10 14 /cm 3 ).
  • N ⁇ type silicon single crystal e.g., phosphorus concentration: about 2 ⁇ 10 14 /cm 3
  • a wafer by a FZ (Floating Zone) method is most preferable.
  • a wafer by a CZ (Czochralski) method is also acceptable. This is because the wafer by the FZ method more readily provides a high-resistance wafer with a relatively higher quality, and more stable concentration.
  • annealing of a CZ crystal at around 450 degrees centigrade generates thermal donors. This unfavorably results in an increase in substantial N type impurity capacity. Therefore, in this case, among the CZ crystals, those by the MCZ (Magnetic Field Applied CZ) method, having a relatively lower oxygen concentration are preferably used.
  • the MCZ crystals the crystals by, particularly, the HMCZ (Horizontal MCZ) method, the CMCZ (Cusp MCZ) method, and the like are particularly preferable.
  • the oxygen concentration of the low oxygen MCZ crystal is generally about from 3 ⁇ 10 17 /cm 3 to 7 ⁇ 10 17 /cm 3 .
  • the oxygen concentration of the FZ (Floating Zone) crystal is generally about 1 ⁇ 10 16 /m 3
  • the oxygen concentration of a general CZ crystal not using the magnetic field is generally about 1 ⁇ 10 18 /cm 3 .
  • the crystals by the CZ method enables device design commonly allowable as a product. This is due to the following: for the IGBT enhanced in IE effect, the overall hole distribution is relatively flat in the ON state for the front surface-side hole accumulation effect; accordingly, even when a variation is caused in crystal resistivity, the effect exerted on the switching loss is small.
  • the range of the resistivity of the high resistance CZ crystal particularly suitable to an IGBT is the range from about 20 ⁇ cm to about 85 ⁇ cm, for example, when the breakdown voltage is assumed to be within the range of from about 600 volts to 1200 volts.
  • the CZ crystal has a merit of high mechanical strength and high thermal distortion resistance as distinct from the FZ crystal low in oxygen concentration. Further, as compared with the FZ crystal, the CZ crystal also has a merit of relative ease in increase in diameter of the wafer. Further, with an increase in diameter, the importance of the problem of the thermal stress increases. Accordingly, use of the CZ crystal is more advantageous from the viewpoint of the countermeasure against thermal stress.
  • Application of the structure of the present invention enables the FZ crystal and the CZ crystal to be used properly according to the situation.
  • an N type hole barrier region introducing resist film 31 is formed by coating or the like, and is patterned by general lithography. Using the patterned N type hole barrier region introducing resist film 31 as a mask, for example, by ion implantation, N type impurities are introduced into a semiconductor substrate is (N ⁇ type single crystal silicon substrate) on the front surface 1 a (first main surface) side of the semiconductor wafer 1 , thereby to form an N type hole barrier region 24 .
  • the resist film 31 which has become unnecessary is removed by ashing or the like.
  • the introduction of the N type hole barrier region 24 before the formation of the trench is advantageous for controlling the depth and the expansion in the lateral direction.
  • a P type floating region introducing resist film 37 is formed by coating or the like, and is patterned by general lithography.
  • P type impurities are introduced into the semiconductor substrate is on the front surface 1 a (first main surface) side of the semiconductor wafer 1 , thereby to form a P type floating region 16 .
  • the ion implantation conditions at this step the following can be shown as preferable ones: for example, ion species: boron, dose amount: about 3.5 ⁇ 10 13 /cm 2 , and implantation energy: about 75 KeV.
  • the resist film 37 which has become unnecessary is removed by ashing or the like.
  • activation annealing or the like is carried out (e.g., 900 degrees centigrade, about 30 minutes).
  • the introduction of the P type floating region 16 before the formation of the trench is advantageous for controlling the depth and the expansion in the lateral direction.
  • the timings of introduction of the N type hole barrier region 24 and the P type floating region 16 are reversible.
  • a trench forming hard mask film 32 such as a silicon oxide type insulation film (e.g., with a thickness of about 450 nm).
  • a trench hard mask film processing resist film 33 is formed by coating or the like, and is patterned by general lithography. Using the patterned trench hard mask film processing resist film 33 as a mask, for example, by dry etching, the trench forming hard mask film 32 is patterned. Then, the resist film 33 which has become unnecessary is removed by ashing or the like.
  • a trench 21 is formed by anisotropic dry etching.
  • the gas type for the anisotropic dry etching for example, Cl 2 /O 2 type gases can be shown as preferable ones.
  • the P type floating region 16 and the N type hole barrier region 24 are subjected to drive-in diffusion (e.g., 1200 degrees centigrade, about 30 minutes).
  • drive-in diffusion e.g. 1200 degrees centigrade, about 30 minutes.
  • a gate insulation film 22 (e.g., a thickness of about 120 nm).
  • a doped poly-silicon film 27 doped with phosphorus (e.g., a thickness of about 600 nm) is deposited in such a manner as to fill the trench 21 almost entirely over the front surface 1 a of the semiconductor wafer 1 over the gate insulation film 22 and the inner surface of the trench 21 by, for example, CVD.
  • CVD chemical vapor deposition
  • the polysilicon film 27 is etched back, thereby to form a trench gate electrode 14 in the trench 21 .
  • a P type body region introducing resist film 38 is formed by general lithography.
  • P type impurities are introduced into almost the entire surface of the cell region 10 , and other necessary portions, thereby to form a P type body region 15 .
  • the ion implantation conditions at this step the following can be shown as preferable ones: for example, ion species: boron, dose amount: about 2 ⁇ 10 13 /cm 2 , and implantation energy: about 250 KeV.
  • the P type body region introducing resist film 38 which has become unnecessary is removed by ashing or the like.
  • the P type body region 15 is subjected to drive-in diffusion (e.g., 1000 degrees centigrade, about 100 minutes).
  • drive-in diffusion e.g. 1000 degrees centigrade, about 100 minutes.
  • the P type body region 15 is introduced. This is effective for control of the profile and the like.
  • an N+ type emitter region introducing resist film 39 is formed by general lithography.
  • N type impurities are introduced into almost the entire surface of the top surface of the P type body region 15 in the active section 40 aa of the linear active cell region 40 a , thereby to form the N+ type emitter region 12 .
  • the trench gate electrode 14 front surface is recessed to a slightly deep position (e.g., about 0.40 micrometer) from the front surface.
  • the N+ type emitter region 12 is also required to be formed to a relatively deeper position correspondingly.
  • the following two-stage ion implantation can be shown as the preferable one: for example, ion species: phosphorus, dose amount: about 1 ⁇ 10 14 /cm 2 , and implantation energy: about 175 KeV, and in addition to these, ion species: arsenic, dose amount: about 5 ⁇ 10 15 /cm 2 , and implantation energy: about 80 KeV.
  • the N+ type emitter region introducing resist film 39 which has become unnecessary is removed by ashing or the like.
  • an introducing resist film 56 such as a P+ type body contact region is formed by general lithography.
  • introducing resist film 56 as a mask for example, by ion implantation, P type impurities are introduced into almost the entire surface of the top surface of the P type body region 15 in the inactive section 40 ai of the linear active cell region 40 a , thereby to form a P+ type body contact region 25 .
  • the ion implantation conditions at this step the following can be shown as the preferable ones: for example, ion species: BF 2 , dose amount: about 5 ⁇ 10 15 /cm 2 , and implantation energy: about 80 KeV.
  • P type impurities are introduced into almost the entire surface of the top surface of the P type body region 15 in the inactive section 40 ai of the linear active cell region 40 a , thereby to form a P+ type buried body contact region 55 .
  • the ion implantation conditions at this step the following can be shown as the preferable ones: for example, ion species: boron, dose amount: about 3 ⁇ 10 15 /cm 2 , and implantation energy: about 80 KeV.
  • the P+ type body contact region, etc., introducing resist film 56 which has become unnecessary is removed by ashing or the like.
  • the N+ type emitter region 12 , the P+ type body contact region 25 , and the P+ type buried body contact region 55 are subjected to activation annealing (e.g., 950 degrees centigrade, about 60 minutes).
  • activation annealing e.g., 950 degrees centigrade, about 60 minutes.
  • the introduction of the N+ type emitter region 12 , the P+ type body contact region 25 , and the P+ type buried body contact region 55 is carried out after drive-in diffusion of the P type body region 15 . This is effective for controlling the profiles thereof.
  • the P+ type buried body contact region 55 is not essential.
  • the presence of the P+ type buried body contact region 55 is effective for the improvement of the latch-up resistance.
  • the P+ type body contact region 25 and the P+ type buried body contact region 55 can also be formed by one-time ion implantation.
  • two-stage ion implantation controls the concentration distribution more simply, and hence is particularly suitable for the improvement of the latch-up resistance.
  • an interlayer insulation film 26 there is deposited, for example, a PSG (phosphosilicate glass) film (the thickness is, for example, about 600 nm).
  • a PSG (phosphosilicate glass) film the thickness is, for example, about 600 nm.
  • the material for the interlayer insulation film 26 may include, other than the PSG film, BPSG (borophosphosilicate glass) film, NSG (non-doped silicate glass) film, and SOG (spin-on-glass) film, or composite films thereof.
  • a contact trench forming resist film is formed by general lithography. Subsequently, for example, by anisotropic dry etching (gas type being, for example, Ar/CHF 3 /CF 4 ), there is formed a contact trench 11 (or a contact hole). Then, the resist film which has become unnecessary is removed by ashing or the like.
  • an aluminum type electrode film 8 (to be a metal emitter electrode 8 ).
  • the following procedure is carried out.
  • a TiW film e.g., a thickness of about 200 nm
  • a large portion of titanium in the TiW film moves to the silicon interface to form silicide, which contributes the improvement of the contact characteristics, but the process is complicated, and hence is not shown in the drawing).
  • an aluminum type metal film including aluminum as a main component e.g., silicon added in an amount of several percent, and the balance being aluminum
  • the metal emitter electrode 8 including an aluminum type metal film and a barrier metal film is patterned (as the gas type for dry etching, for example, Cl 2 /BCl 3 ).
  • an organic film including polyimide as a main component is coated almost entirely over the device surface 1 a of the wafer 1 .
  • an organic film including polyimide as a main component e.g., with a thickness of about 2.5 micrometers
  • the emitter pad 9 , the gate pad 6 , and the like of FIG. 5 are opened.
  • the back surface 1 b of the wafer 1 is subjected to a back grinding treatment (if required, chemical etching or the like for removing the damage of the back surface is also carried out).
  • a back grinding treatment if required, chemical etching or the like for removing the damage of the back surface is also carried out.
  • the original wafer thickness of, for example, about 800 micrometers (as the preferable range, about from 1000 to 450 micrometers) is, if required, reduced to, for example, about 200 to 30 micrometers.
  • the breakdown voltage is assumed to be about 1200 volts
  • the final thickness is about 120 micrometers.
  • N type impurities are introduced into almost the entire surface of the back surface 1 b of the semiconductor wafer 1 , for example, by ion implantation, thereby to form an N type field stop region 19 .
  • the ion implantation conditions the following can be shown as the preferable ones: for example, ion species: phosphorus, dose amount: about 7 ⁇ 10 12 /cm 2 , and implantation energy: about 350 KeV.
  • the back surface 1 b of the wafer 1 is subjected to laser annealing or the like.
  • N type impurities are introduced into almost the entire surface of the back surface 1 b of the semiconductor wafer 1 , for example, by ion implantation, thereby to form a P+ type collector region 18 .
  • the ion implantation conditions the following can be shown as the preferable ones: for example, ion species: boron, dose amount: about 1 ⁇ 10 13 /cm 2 , and implantation energy: about 40 KeV.
  • the back surface 1 b of the wafer 1 is subjected to laser annealing or the like.
  • the laser annealing conditions are optimized for the activation annealing of back surface ion implantation.
  • the crystal defects generated by the back surface ion implantation at the portion in proximity to the boundary between the N type field stop region 19 and the N ⁇ type drift region 20 can be intentionally allowed to remain.
  • the remaining crystal defects function as a local lifetime control layer, and contributes to the improvement of the trade-off characteristics of switching performance-ON voltage.
  • annealing conditions laser application conditions
  • the following can be shown as the preferable ones: for example, annealing method: laser is applied from the back surface 1 b side of the wafer 1 , wavelength: 527 nm, pulse width: about 100 ns, energy density: about 1.8 J/cm 2 , application system: 2-pulse system, delay time between both pulses: about 500 ns, and pulse overlap ratio: about 66%.
  • a metal collector electrode 17 is formed over almost the entire surface of the back surface 1 b of the semiconductor wafer 1 (for specific details, see FIG. 25 and its explanation). Then, by dicing or the like, division into the chip regions of the semiconductor wafer 1 is performed, and, if required, sealing in a package is performed, resulting in the completion of the device.
  • the IE type trench gate IGBT will be specifically described. It is naturally understood that the back surface structure is not limited to the IE type IGBT and the trench gate IGBT, but is also applicable to IGBTs in other forms, and the like.
  • FIG. 25 is a local detailed cross-sectional view of the device back surface for a detailed description on the back surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention, or for illustrating the device structure and the manufacturing method of a modified example (aluminum-doped structure). Based on this, an explanation will be given to the detailed description on the back surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention or a modified example (aluminum-doped structure).
  • FIG. 25 shows a cross-sectional enlarged view of the back side and its vicinity of the semiconductor chip 2 of FIG. 7 (a schematic view of the structure in the vicinity of the back side enlarged in the thickness direction of the chip).
  • a relatively thin P type semiconductor region (with a thickness of, for example, about 0.04 to 0.1 micrometer), namely, an aluminum doped region 30 .
  • the impurity concentration (e.g., about 1 ⁇ 10 19 /cm 3 ) is higher than the impurity concentration of the P+ type collector region 18 .
  • a metal collector electrode 17 is formed in contact with the aluminum doped region 30 over the back surface 1 b of the semiconductor substrate 2 .
  • One example thereof will be shown as the following configuration from the side closer to the semiconductor substrate 2 .
  • an aluminum back surface metal film 17 a e.g., with a thickness of about 600 nm
  • a titanium back surface metal film 17 b e.g., with a thickness of about 100 nm
  • a nickel back surface metal film 17 c e.g., with a thickness of about 600 nm
  • a gold back surface metal film 17 d e.g., with a thickness of about 100 nm.
  • the manufacturing method will be described briefly.
  • the aluminum back surface metal film 17 a , the titanium back surface metal film 17 b , the nickel back surface metal film 17 c , and the gold back surface metal film 17 d are sequentially subjected to sputtering deposition.
  • aluminum is introduced into the silicon substrate, thereby to form the aluminum doped region 30 .
  • division into chip regions of the semiconductor wafer 1 is performed, resulting in the state as shown in FIG. 7 ( FIG. 7 does not clearly show the detailed structure).
  • each embodiment of the present invention there is adopted a structure in which, in the ON state, holes are accumulated on the emitter side to promote the injection of electrons.
  • the PN diode on the back surface collector side conversely, there is adopted a diode resulting in a low injection efficiency, thereby to achieve a lower switching loss.
  • a transparent emitter in order to form the back surface diode with a low injection efficiency, it is effective to reduce the ratio of the carrier concentration “Qp” to the P+ type collector region 18 and the carrier concentration “Qn” of the N type field stop region 19 (which will be hereinafter referred to as a “carrier concentration ratio”), namely, “(Qp/Qn)”.
  • the carrier concentration “Qp” of the P+ type collector region 18 is excessively reduced, the characteristics of the back surface metal contact are deteriorated.
  • the aluminum doped region 30 higher in impurity concentration than the P+ type collector region 18 introduced from the back-surface aluminum film.
  • the carrier concentration ratio for example, about 1.5 (the range of, e.g, about 1.1 to 4) can be shown as the preferable one capable of optimizing the trade-off performance of switching performance-ON voltage performance.
  • the example described in this section is, for example, a modified example of the planar layout of FIG. 6 .
  • FIG. 26 is an enlarged top view corresponding to FIG. 6 , for illustrating Modified Example 1 (N+ type surface floating region & P+ type surface floating region addition structure) regarding the surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention.
  • FIG. 27 is a device cross-sectional view corresponding to a F-F′ cross section of FIG. 26 .
  • FIG. 28 is a device cross-sectional view corresponding to a G-G′ cross section of FIG. 26 . Based on these, a description will be given to Modified Example 1 (N+ type surface floating region & P+ type surface floating region addition structure) regarding the surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention.
  • an N+ type surface floating region 12 i (first conductivity type surface floating region) corresponding to the N+ type emitter region 12 .
  • the N+ type surface floating region 12 i is formed in the same process as that for, for example, the N+ type emitter region 12 , simultaneously.
  • the linear inactive cell region 40 i is divided into a first conductivity type floating region formation section in which the N+ type surface floating region 12 i is formed in the length direction thereof, and a first conductivity type floating region non-formation section in which the N+ type surface floating region 12 i is not formed.
  • Some of electrons injected from the MOSFET portion in the IGBT pass through the accumulation layer formed at the N type layer portion of the trench sidewall and the inversion layer formed at the P type sidewall portion, and also reach the N+ type surface floating region 12 i , to be injected into the P type floating region 16 .
  • the IGBT turns off in this state, the electrons recombine with holes remaining in the P type floating region 16 to be annihilated. As a result, it is possible to reduce the switching loss at the OFF time.
  • the regions are a P+ type surface floating region 25 i (second conductivity type surface floating region) and a P+ type buried floating region 55 i.
  • the F-F′ cross section of FIG. 26 is roughly equal to FIG. 7 , except that as shown in FIG. 27 , in the front surface 1 a of the semiconductor substrate of the active section 40 aa in the linear inactive cell region 40 i , there is arranged the N+ type surface floating region 12 i.
  • the G-G′ cross section of FIG. 26 is equal to FIG. 8 , except that as shown in FIG. 28 , also in the front surface region of the P type body region 15 in the linear inactive cell region 40 i , there are arranged a P+ type surface floating region 25 i (second conductivity type surface floating region) and a P+ type buried floating region 55 i corresponding to the P+ type body contact region 12 and the P+ type buried body contact region 55 .
  • Such a structure has a merit of forming the N+ type emitter region introducing resist film 39 and the P+ type body contact region, etc., introducing resist film 56 in a relatively simple structure crossing the trench 21 .
  • the structure has a merit of increasing the process margin in that there is eliminated the necessity of allowing the ends of the resist film patterns to extend along the trench.
  • the structure is not limited to fully crossing the linear inactive cell region 40 i . It is also acceptable that the ends of the resist film patterns of the N+ type emitter region introducing resist film 39 and the P+ type body contact region, etc., introducing resist may be formed inside the linear inactive cell region 40 i.
  • the unit cell structure described in this section is the one obtained by omitting the P type floating region 16 and the N type hole barrier region 24 in the unit cell structure in FIG. 7 .
  • FIG. 29 is a device cross-sectional view corresponding to the C-C′ cross section of FIG. 6 corresponding to FIG. 7 for illustrating Modified Example 2 (simplified active cell structure) regarding the surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention. Based on this, a description will be given to Modified Example 2 (simplified active cell structure) regarding the front surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention.
  • the P type floating region 16 and the N type hole barrier region 24 are omitted. Therefore, the hole concentration of the N ⁇ type drift region 20 portion of the linear active cell region 40 a tends to be reduced as compared with the structure of FIG. 7 .
  • the linear active cell region 40 a is sufficiently narrow, and when the depth of the trench 21 is sufficiently deep, it becomes effective to adopt the structure of FIG. 29 . Namely, it is possible to simplify the device structure and the impurity doping step. Further, there is implemented a structure advantageous in the case not for use in which importance is placed on a low ON voltage, but for use in which the switching performance is desired to be made higher.
  • FIG. 2 The example described in this section is a modified example relative to the basic device structure (mainly FIG. 2 ) described in Section 1. Therefore, other views such as FIGS. 1 , and 3 to 29 also apply to this example with corresponding changes added thereto, respectively, or as they are.
  • FIG. 30 is a device schematic cross-sectional view of the A-A′ cross section of the cell region end cut-out region R 1 of FIG. 1 corresponding to FIG. 2 for illustrating Modified Example (hole collector cell addition structure) regarding the surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention.
  • FIG. 31 is an enlarged top view of the linear unit cell region and its periphery R 5 of FIG. 1 for illustrating Modified Example (hole collector cell addition structure) regarding the surface side device structure of the narrow active cell IE type trench gate IGBT of the one embodiment of the present invention.
  • FIG. 32 is an enlarged top view corresponding to FIG.
  • FIG. 33 is a device cross-sectional view corresponding to a H-H′ cross section of FIG. 32 .
  • FIG. 34 is a device cross-sectional view corresponding to a J-J′ cross section of FIG. 32 .
  • FIG. 35 is a device cross-sectional view corresponding to a K-K′ cross section of FIG. 32 .
  • FIG. 30 shows the X-X′ cross section of the cell region end cut-out region R 1 of FIG. 1 .
  • the semiconductor region in this example, silicon single crystal region
  • the back surface 1 b the back side main surface or the second main surface of the semiconductor substrate
  • the metal collector electrode 17 Over the front surface, there is arranged the metal collector electrode 17 .
  • the N ⁇ type drift region 20 first conductivity type drift region
  • the P+ type collector region 18 forming the main part of the semiconductor substrate 2
  • the N type field stop region 19 there is arranged between the N ⁇ type drift region 20 (first conductivity type drift region) and the P+ type collector region 18 forming the main part of the semiconductor substrate 2 .
  • trench gate electrodes 14 are embedded via the gate insulation film 22 , respectively.
  • Each trench gate electrode 14 is coupled to the metal gate electrode 5 (specifically, the metal gate wire 7 ) or the emitter electrode 8 according to its function.
  • the trenches 21 perform a function of defining respective regions.
  • a dummy cell region 34 is defined from opposite sides thereof by a pair of trenches 21 .
  • One trench 21 of these defines the cell region 10 and the cell peripheral junction region 35 .
  • the cell peripheral junction region 35 is coupled via a P+ type body contact region 25 p to the metal emitter electrode 8 .
  • the thickness of the gate insulation film 22 at any portion of the trench is assumed to be roughly equal (however, it is not excluded that, if required, a given portion is different in thickness from other portions).
  • an emitter contact is established in the cell peripheral junction region 35 and the dummy cell region 34 .
  • a P type floating field ring 36 In the semiconductor region on the front surface side 1 a of the N ⁇ type drift region 20 outside the cell peripheral junction region 35 , there is arranged a P type floating field ring 36 . Over the front surface 1 a , a field plate 4 is arranged, and is coupled via a P+ type body contact region 25 r to the floating field ring 36 .
  • the dummy cell region 34 is basically equal in both structure and size to the linear active cell region 40 a except for not having an N+ type emitter region 12 .
  • a P+ type body contact region 25 d arranged in the front surface of the P type body region 15 is coupled to the metal emitter electrode 8 .
  • the dummy cell region 34 can be basically formed in the same structure as that of the hole collector cell (see FIG. 30 ).
  • the linear unit cell region 40 as the unit cell includes a linear inactive cell region 40 i , a linear active cell region 40 a on one side thereof, a linear hole collector cell region 40 c on the other side thereof, and, half-width linear inactive cell regions 40 i on opposite sides thereof.
  • the linear active cell regions 40 a and the linear hole collector cell regions 40 c are alternately arranged between the full-width linear inactive cell regions 40 i (see FIG. 31 ).
  • first linear unit cell regions 40 f and second linear unit cell regions 40 s are alternately arrayed.
  • the P type body region 15 (second conductivity type body region).
  • the N+ type emitter region 12 first conductivity type emitter region
  • a P+ type body contact region 25 is coupled to the metal emitter electrode 8 .
  • the N+ type emitter region 12 and the P+ type body contact region 25 are coupled to the metal emitter electrode 8 .
  • an N type hole barrier region 24 is arranged in the linear active cell region 40 a .
  • the trench gate electrodes 14 on the opposite sides of the linear active cell region 40 a are electrically coupled to the metal gate electrode 5 .
  • the structure of the linear hole collector cell region 40 c is different in this example only in that there is no N+ type emitter region 12 , and in that the trench gate electrodes 14 on the opposite sides thereof are coupled to the emitter electrode 8 , and, is equal in other respects including dimensions and the like to the linear active cell region 40 a.
  • the P type body region 15 is arranged in the front side main surface 1 a (first main surface) side semiconductor surface region of the semiconductor substrate in the linear inactive cell region 40 i .
  • the P type body region 15 is arranged in the underlying N ⁇ type drift region 20 .
  • a P type floating region 16 (second conductivity type floating region) covering the lower ends of the trenches 21 on the opposite sides, and deeper than them.
  • the concentration of the N type hole barrier region 24 is increased for optimization, similarly, there is no effect on the breakdown voltage. As a result of this, it becomes possible to effectively enhance the hole accumulation effect.
  • the IE type trench gate IGBT there is not formed a contact from the emitter electrode 8 to the P type floating region 16 . This is as follows: the direct hole discharge path from the P type floating region 16 to the emitter electrode 8 is blocked, which results in an increase in hole concentration of the N ⁇ type drift region 20 (N base region) under the linear active cell region 40 a ; as a result, the electron concentration to be injected from the MOSFET into the N base region in the IGBT is improved, thereby to reduce the ON resistance.
  • the width Wa of the linear active cell region 40 a and the width We of the linear hole collector cell region 40 c are set narrower than the width Wi of the linear inactive cell region 40 i .
  • this is referred to as a “narrow active cell type unit cell”.
  • a device having the narrow active cell type unit cell will be specifically described.
  • the example herein described is not limited thereto. It is naturally understood that the example is also applicable to a device having a “non-narrow active cell type unit cell”.
  • the linear active cell regions 40 a (or the linear hole collector cell regions 40 c ) and the linear inactive cell regions 40 i are alternately arrayed to form the linear unit cell region 40 .
  • This configuration is referred to as an “alternate array system” in the present invention.
  • an alternate array system in the present invention.
  • a description will be given on the premise of the alternate array system. However, it is naturally understood that the “non-alternate array system” is also acceptable.
  • FIG. 30 a description was given to the outline of embodiments of FIGS. 31 to 35 of the present invention (the main part and the peripheral part). However, in the following description, these are divided into structural elements such as a cell part (cross-sectional or planar structure), and a cell peripheral part to be described. However, it is naturally understood that these also provides the outlines to various modified examples.
  • FIG. 31 shows one example of the detailed planar structure of the linear unit cell region main part and its peripheral cut-out region R 5 of FIG. 1 .
  • active sections 40 aa having a given length are arranged at a given interval, between which there is an inactive section 40 ai not including the N+ type emitter region 12 arranged therein. Namely, some portions in the length direction of the linear active cell region 40 a locally and dispersively become the active sections 40 aa .
  • the active section 40 aa of the linear active cell region 40 a in almost the entire region thereof, there is arranged the N+ type emitter region 12 .
  • the inactive section 40 ai of the linear active cell region 40 a in almost the entire region thereof, there are arranged the P+ type body contact region 25 and the P+ type buried body contact region 55 .
  • the P+ type body contact region 25 and the P+ type buried body contact region 55 are arranged, and the N+ emitter region 12 is not arranged.
  • the P type body region 15 and the P type floating region 16 second conductivity type floating region.
  • being distributed with a given length at a given interval means “being periodical”.
  • being substantially periodical corresponds to the local and dispersive distribution.
  • being local and dispersive is “being wider than that” and does not necessarily mean “being periodical or quasi-periodical”.
  • linear active cell region 40 a and the linear inactive cell region 40 i are the same as those shown in FIGS. 4 , and 6 to 9 . Below, only the linear hole collector cell region 40 c will be described.
  • the trench buried electrodes 14 c on the opposite sides of the linear hole collector cell region 40 c are required to be coupled to the emitter potential.
  • two are coupled to each other via, for example, a buried electrode coupling part 28 of a polysilicon film at the same layer (including an intra-trench electrode 14 i in the coupling part trench 21 c ).
  • a contact part 11 c contact hole between emitter electrode—buried electrode, via which, coupling is established with the metal emitter electrode 8 .
  • the feature of the linear hole collector cell region 40 c is similar to that of the linear active cell region 40 a , but is different in that the N+ type emitter region 12 is not arranged, and in that the P+ type body contact region 25 and the P+ type buried body contact region 55 are arranged in almost the entire region except for the underlying part of the buried electrode coupling part 28 .
  • FIG. 33 shows the H-H′ cross section of FIG. 32 .
  • the cross section is similar to the cross section (linear active cell region 40 a ) of FIG. 7 .
  • the buried electrode coupling part 28 polysilicon coupling part in the overlying part. So the N+ type emitter region 12 and the P type body region 15 are not introduced. This is for the following reason: in the step of FIG. 17 , the polysilicon film 27 over the linear hole collector cell region 40 c is left; as a result, in the step of FIG. 18 , impurities are not introduced under the buried electrode coupling part 28 . This also applies to FIG.
  • the underlying part of the buried electrode coupling part 28 is in the floating state. If the P type diffusion layer is not present at all, in the OFF state, the electric field intensity concentrates to the trench bottom end, resulting in the reduction of the breakdown voltage. For this reason, into under the buried electrode coupling part 28 , the P type floating region 16 is desirably introduced.
  • the P type floating region 16 has been subjected to ion implantation at the step before the formation of the buried electrode, and hence can be arranged under the buried electrode coupling part 28 . As a result, even if the linear inactive cell region 40 i is set with any dimensions, the breakdown voltage can be ensured. This enables the design having the degree of freedom according to the product requirements.
  • FIG. 34 shows the J-J′ cross section of FIG. 32 .
  • the cross section is basically similar to FIG. 9 , but is different in that between the linear hole collector cell region 40 c and the linear inactive cell region 40 i , there are a coupling part trench 21 c and a trench buried coupling part 14 i .
  • the cross section is also different in that, for the same reason as the previous one, in the linear hole collector cell region 40 c , there are no N+ type emitter region 12 , no P+ type body contact region 25 , and no P+ type buried body contact region 55 .
  • the coupling part trench 21 c efficiently separates the P type floating region 16 from the P+ type body contact region 25 and the P+ type buried body contact region 55 coupled to the metal emitter electrode 8 .
  • FIG. 35 shows the K-K′ cross section of FIG. 32 .
  • the cross section is entirely equal to FIG. 8 , except that the trench gate electrode 14 is a trench buried electrode 14 c coupled to the emitter potential.
  • the degree of the hole accumulation effect of the surface device structure depends upon the geometrical shape and the N type hole barrier region 24 .
  • the linear active cell region 40 a and the linear hole collector cell region 40 c do not cause a significant difference for holes.
  • the hole accumulation effect is equal, and accordingly, the IE effect is also equal.
  • the linear layout is basically adopted.
  • the optimum design of the N+ type emitter region 12 is easy.
  • substantial cell shrinkage is implemented. For this reason, even when the linear hole collector cell region 40 c is arranged, optimization of the layout in the linear active cell region 40 a can ensure the saturation current required as the whole chip.
  • FIG. 36 is an enlarged top view of the linear unit cell region and its periphery R 5 of FIG. 1 for illustrating the outline of the device structure of the one embodiment of the present invention. Based on this, a description will be given to the supplementary explanation on the embodiment (including modified examples), and the consideration on the whole thereof.
  • an attempt to enhance the IE effect requires minimization of the interval between trenches.
  • a structure including substrate trenches for body contact or substrate contact trench
  • shrinkage is difficult.
  • even a decrease in width of the trench itself does not lead to the improvement of the IE effect. Rather, in order to ensure the thickness of the gate insulation film or the like, the with of the trench itself is desirably not reduced.
  • the width of the active section 40 aa is desirably as small as possible (e.g., about 0.5 micrometer or less).
  • the width of each individual active section 40 aa is made as it is, and the pitch thereof is reduced (the number is increased).
  • the width f each individual active section 40 aa is simply increased too much, not only the latch-up resistance is reduced, but also the short-circuit safe operating area is also reduced.
  • the present invention is not limited thereto.
  • the following procedure is also acceptable: a nondoped poly-silicon film is applied thereto; after deposition, necessary impurities are added by ion implantation or the like.

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US10290729B2 (en) 2019-05-14
CN108933170A (zh) 2018-12-04
US20180069108A1 (en) 2018-03-08
CN103489905A (zh) 2014-01-01
JP5979993B2 (ja) 2016-08-31
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EP2674979A2 (en) 2013-12-18
CN103489905B (zh) 2018-06-15

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