US20120103820A1 - Electrolytic copper plating solution for filling for forming microwiring of copper for ulsi - Google Patents

Electrolytic copper plating solution for filling for forming microwiring of copper for ulsi Download PDF

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Publication number
US20120103820A1
US20120103820A1 US13/378,529 US201013378529A US2012103820A1 US 20120103820 A1 US20120103820 A1 US 20120103820A1 US 201013378529 A US201013378529 A US 201013378529A US 2012103820 A1 US2012103820 A1 US 2012103820A1
Authority
US
United States
Prior art keywords
microwiring
ulsi
plating solution
copper
electrolytic copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US13/378,529
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English (en)
Inventor
Junnosuke Sekiguchi
Hirofumi Takahashi
Akihiro Aiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JX Nippon Mining and Metals Corp
Original Assignee
JX Nippon Mining and Metals Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by JX Nippon Mining and Metals Corp filed Critical JX Nippon Mining and Metals Corp
Assigned to JX NIPPON MINING & METALS CORPORATION reassignment JX NIPPON MINING & METALS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AIBA, AKIHIRO, SEKIGUCHI, JUNNOSUKE, TAKAHASHI, HIROFUMI
Publication of US20120103820A1 publication Critical patent/US20120103820A1/en
Abandoned legal-status Critical Current

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Classifications

    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00—Electroplating: Baths therefor
    • C25D3/02—Electroplating: Baths therefor from solutions
    • C25D3/38—Electroplating: Baths therefor from solutions of copper
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/06—Wires; Strips; Foils
    • C25D7/0607—Wires
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to an electrolytic copper plating solution for filling for forming microwiring of copper for ULSI.
  • Electrolytic copper plating for filling ULSI microwiring is usually carried out with sulfuric acid-based strongly acidic plating solutions (pH of 1.2 or lower). Seed layers upon plating are sputtered copper films, of which thickness in trenches/vias have become very thin due to miniaturization of wiring. Oxidation of the outermost layer of the seed layer is unavoidable because the outermost layer is atmospherically exposed prior to electrolytic plating. Accordingly, the oxidized parts of the seed layer are easily dissolved when it is immersed in a strongly acidic electrolytic plating solution leading to formation of defects on the thin seed layer. When a copper wiring layer is formed by electrolytic copper plating thereafter, the copper plating is unsatisfactorily absent in spots. Particularly, the inner wall of trenches/vias tends to have problematic voids.
  • An object of the present invention is to provide an electrolytic copper plating solution which can suppress, upon electrolytic copper plating on a copper seed layer during fabrication of ULSI copper microwiring (damascene copper wiring) having trends to further miniaturization, dissolution of the copper seed layer and accordingly can suppress occurrence of voids on the inner wall of vias/trenches.
  • the present inventors have attempted to suppress dissolution of copper seed layers upon being immersed in the plating solution by using carboxylic acids and the like instead of sulfuric acid usually used for sulfuric acid-based strongly acidic copper plating solutions and to change pH of the plating solution from conventional strong acid to around weak acid. As a result, they have found that formation of voids on the side wall of trenches which may be generated with the sulfuric acid-based strongly acidic plating solutions can be avoided with the carboxylic acid-based plating solution, thereby accomplished the present invention which solves the above-mentioned problems.
  • the present invention provides the followings:
  • formation of a copper wiring layer on a copper seed layer using the electrolytic copper plating solution of the present invention can suppress dissolution of the copper seed layer and accordingly formation of voids on the inner wall of vias/trenches.
  • the electrolytic copper plating solution for filling for forming microwiring for ULSI of the present invention has a pH of 1.8 or higher and 3.0 or lower.
  • Conventional sulfuric acid-based copper plating solutions are strongly acidic at pH 1.2 or lower.
  • the present plating solution can have a pH of 1.8 or higher and 3.0 or lower because carboxylic acid such as acetic acid is used instead of sulfuric acid.
  • pH is more preferably 2.0 or higher and 2.2 or lower.
  • pH is lower than 1.8, copper seed layers are easily dissolved due to low pH and as a result, voids are also easily formed. If pH is higher than 3.0, copper ions in the plating solution may be converted to oxides or hydroxides to cause precipitations.
  • the carboxylic acid may be any carboxylic acid that can be dissolved in the plating solution and adjust pH to the above range, and is preferably a saturated carboxylic acid having 1 or more and 4 or less carbon atoms such as formic acid, acetic acid, propionic acid, butyric acid, oxalic acid and the like, with acetic acid being particularly preferable.
  • the plating solution preferably contains the carboxylic acid at 0.01 to 2.0 mol/L and more preferably 0.2 to 1.0 mol/L.
  • the concentration of the carboxylic acid in the plating solution affects filling properties and pH such that the concentration of carboxylic acid at more than 2.0 mol/L reduces pH of the plating solution to lower than 1.8, causing increased formation of voids.
  • the concentration of carboxylic acid in the plating solution is less than 0.01 mmol/L, the plating solution has a pH of higher than 3.0, which may cause precipitations as described above.
  • the electrolytic copper plating solution of the present invention is aqueous and may comprise other components such as copper salts, chloride ions, trace additives and the like, which may be well known and are not particularly limited.
  • Copper salts may include copper sulfate, copper nitrate, copper chloride and the like, with copper sulfate being preferable.
  • the plating solution preferably contains the copper salt at 0.05 to 1.5 mol/L and more preferably 0.2 to 0.8 mol/L.
  • the plating solution preferably contains chloride ions at a concentration of 0.3 to 3.0 mmol/L and more preferably 1.0 to 2.0 mmol/L.
  • Trace additives may include promoters, inhibitors, leveling agents and the like.
  • Promoters may include bis(3-sulfopropyl)-disulfide, disodium salt, 3-mercaptopropanesulfonic acid and the like, which are preferably contained in the plating solution at 1 to 30 mg/L.
  • Inhibitors may include polyethylene glycol, polypropylene glycol, copolymers thereof and the like, which are preferably contained in the plating solution at 10 to 500 mg/L.
  • Leveling agents may include Janus Green B, polyethyleneimine, polyvinylpyrrolidone and the like, which are preferably contained in the plating solution at 0.1 to 50 mg/L.
  • Plating operations using the electrolytic copper plating solution of the present invention are preferably carried out at a bath temperature of 20 to 30° C. in view of stability of bath and deposition speed of copper.
  • the cathode current density is preferably 0.1 to 5 A/dm2.
  • a material to be plated by electrolytic copper plating is a microwiring substrate such as semiconductor wafers and is preferably a silicon substrate having ULSI microwiring such as trenches/vias onto which a copper seed layer is provided.
  • the copper seed layer may be formed by well-known methods such as sputtering and electroless plating.
  • the electrolytic copper plating solution of the present invention allows to carry out plating without voids even when the copper seed layer in trenches/vias has a thickness of 2 nm or less.
  • a silicon substrate having ULSI microwiring was subjected to electrolytic copper plating using the following plating solution.
  • the silicon substrate which is to be plated, has fine trench patterns (line width: 180 nm and depth: 500 nm) and a Cu seed layer is provided on its outermost surface by sputtering.
  • the Cu seed layer had a thinnest thickness of 2 nm in trenches.
  • Plating was carried out at 25° C. and 1 A/dm 2 for 30 seconds.
  • FIG. 1 Cross-sectional SEM observation is shown in FIG. 1 . Void was not formed at anywhere including the side wall part of trenches.
  • a silicon substrate having ULSI microwiring was subjected to electrolytic copper plating using the following plating solution.
  • the silicon substrate to be plated was the same as the one used in Example 1, in which Cu seed layer had a thinnest thickness of 2 nm in trenches.
  • Plating was carried out at 25° C. and 1 A/dm 2 for 30 seconds.
  • a silicon substrate having ULSI microwiring was subjected to electrolytic copper plating using the following plating solution.
  • the silicon substrate to be plated was the same as the one used in Example 1 except that its Cu seed layer had a thinnest thickness of 1.8 nm in trenches.
  • Plating was carried out at 25° C. and 1 A/dm 2 for 30 seconds.
  • Electrolytic copper plating was carried out in the same manner as Example 1 except that composition of the plating solution was changed as follows.
  • FIG. 2 Cross-sectional SEM observation is shown in FIG. 2 . Voids (dark shadowy parts in circles) were observed in at least some of the side wall part of trenches.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Organic Chemistry (AREA)
  • Electrochemistry (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electroplating And Plating Baths Therefor (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
US13/378,529 2009-07-01 2010-06-22 Electrolytic copper plating solution for filling for forming microwiring of copper for ulsi Abandoned US20120103820A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2009156929 2009-07-01
JP2009-156929 2009-07-01
PCT/JP2010/060545 WO2011001847A1 (ja) 2009-07-01 2010-06-22 Ｕｌｓｉ微細銅配線埋め込み用電気銅めっき液

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US13/378,529 Abandoned US20120103820A1 (en) 2009-07-01 2010-06-22 Electrolytic copper plating solution for filling for forming microwiring of copper for ulsi
US14/101,457 Abandoned US20140158546A1 (en) 2009-07-01 2013-12-10 Electrolytic copper plating solution for filling for forming microwiring of copper for ulsi

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JP (1) JP5809055B2 (ja)
TW (1) TWI412631B (ja)
WO (1) WO2011001847A1 (ja)

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JP2012092366A (ja) * 2010-10-25 2012-05-17 Imec 銅の電着方法
JP5903706B2 (ja) * 2011-08-25 2016-04-13 石原ケミカル株式会社 銅フィリング方法及び当該方法を適用した電子部品の製造方法
KR20140135007A (ko) * 2013-05-15 2014-11-25 삼성전기주식회사 인쇄회로기판용 동 도금액 조성물 및 이를 이용한 비아 홀 충전방법
JP7157749B2 (ja) 2017-08-31 2022-10-20 株式会社Adeka 電解めっき液用添加剤を含有する電解めっき液及び該電解めっき液を用いた電解めっき方法
TWI636245B (zh) * 2017-11-21 2018-09-21 財團法人金屬工業研究發展中心 金屬腐蝕監測系統及方法
US20240132453A1 (en) 2021-02-15 2024-04-25 Adeka Corporation Additive for electroplating solution, electroplating solution, electroplating method, and method of producing metal layer

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US20040256239A1 (en) * 2003-05-12 2004-12-23 Rohm And Haas Electronic Materials, L.L.C. Tin plating method

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Publication number Publication date
JP5809055B2 (ja) 2015-11-10
TWI412631B (zh) 2013-10-21
TW201107537A (en) 2011-03-01
JPWO2011001847A1 (ja) 2012-12-13
WO2011001847A1 (ja) 2011-01-06
US20140158546A1 (en) 2014-06-12

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AS Assignment

Owner name: JX NIPPON MINING & METALS CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SEKIGUCHI, JUNNOSUKE;TAKAHASHI, HIROFUMI;AIBA, AKIHIRO;REEL/FRAME:027428/0203

Effective date: 20111201

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION