US20090203209A1 - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- US20090203209A1 US20090203209A1 US12/320,346 US32034609A US2009203209A1 US 20090203209 A1 US20090203209 A1 US 20090203209A1 US 32034609 A US32034609 A US 32034609A US 2009203209 A1 US2009203209 A1 US 2009203209A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 17
- 238000005498 polishing Methods 0.000 claims description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 239000000126 substance Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims 3
- 238000009499 grossing Methods 0.000 claims 3
- 239000011159 matrix material Substances 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 238000003780 insertion Methods 0.000 abstract description 6
- 230000037431 insertion Effects 0.000 abstract description 6
- 239000011229 interlayer Substances 0.000 abstract description 6
- 238000004513 sizing Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device wherein dummy patterns are formed on a semiconductor substrate together with a wiring pattern, and to a method of manufacturing the semiconductor device.
- each of the global steps consists of a difference in film thickness at the loosest portion and the densest portion of the underlying wiring pattern.
- the global steps are different from one another according to a wiring layout. Therefore, when the global step is large in the interlayer film CMP process, the underlying wiring pattern is exposed or disappears at the loose portion of the underlying wiring pattern, and the residual step occurs due to cutting insufficiency at the dense portion of the underlying wiring pattern.
- dummy patterns which are different from an actual wiring pattern are inserted into the entire surface of a chip to set the global steps as low as possible (refer to, for example, a patent document: Japanese Unexamined Patent Publication No. 2003-140319).
- the global steps vary depending on whether the dummy patterns exist.
- the insertion of the dummy patterns provides an improvement in the global step.
- the dummy patterns may preferably be inserted to improve the global steps in this way, a disadvantage occurs in that when the pattern ratio become excessively large, EPD cannot be detected upon etching of the wiring pattern.
- the present invention therefore provides a semiconductor device which is capable of avoiding an increase in pattern ratio and allowing wiring dummy patterns to improve global steps developed by CMP upon the insertion of the dummy patterns which are different from an actual wiring pattern, and a method of manufacturing the semiconductor device.
- a semiconductor device of the present invention comprises a wiring pattern and a plurality of dummy patterns which are different from the wiring pattern, and an insulating film which is formed on the wiring pattern and the dummy patterns by a chemical vapor deposition method.
- the dummy patterns are provided with pattern non-forming regions each having a width which is filled by plus sizing of the insulating film upon formation of the insulating film.
- the pattern non-forming regions of the dummy patterns may be formed in stripe form or may be formed in character or graphical form.
- the pattern non-forming regions of the dummy patterns may preferably be shaped in character or graphical forms which are different for each dummy pattern.
- the dummy patterns may preferably be square. Also, the dummy patterns may preferably be arranged in lattice form.
- the present invention also provides a method of manufacturing a semiconductor device, which comprises the following steps of: forming a wiring pattern; forming a plurality of dummy patterns which are different from the wiring pattern together with the wiring pattern; and forming an insulating film on the wiring pattern and the dummy patterns by a chemical vapor deposition method.
- the dummy patterns are formed so as to be provided with pattern non-forming regions each having a width which is filled by plus sizing of the insulating film upon formation of the insulating film.
- the pattern non-forming regions of the dummy patterns may be formed in stripe form or may be formed in character or graphical form.
- the pattern non-forming regions of the dummy patterns may preferably be shaped in character or graphical forms which are different for each dummy pattern.
- the dummy patterns may be shaped in square form. Also, the dummy patterns may be arranged and formed in lattice form.
- dummy patterns formed together with a wiring pattern are respectively provided with pattern non-forming regions each having a predetermined width.
- the predetermined width of the pattern non-forming region is defined as a width which is filled with an insulating film by plus sizing of the insulating film upon formation of the insulating film. Then, the insulating film is formed on the wiring pattern and the dummy patterns.
- the plus sizing of the insulating film is to deposit an insulating film material not only on a pattern upper surface but also on pattern sidewalls upon vapor phase growth of the insulating film and increase the size of each pattern at a predetermined rate.
- the width of each of the pattern non-forming regions of the dummy patterns is equivalent to the shortest distance between the pattern sidewalls at individual points lying in the pattern non-forming regions.
- the pattern non-forming regions are filled with the insulating film material which is deposited on the pattern sidewalls upon vapor phase growth of the insulating film, the coverage of the insulating film remains unchanged at dummy patterns (conventional dummy patterns) which are provided with no pattern non-forming regions and the dummy patterns which are provided with the pattern non-forming regions.
- an advantageous effect is achieved in that upon insertion of dummy patterns which are different from an actual wiring pattern, a pattern ratio can be prevented from increasing, and the wiring dummy patterns enable an improvement in the global step of CMP.
- FIG. 1 is a partly plan view (A) and a partly sectional view (B) showing a semiconductor device according to a first embodiment of the present invention
- FIG. 2 is a process view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention
- FIG. 3 is a partly plan view (A) and a partly sectional view (B) showing a semiconductor device according to a second embodiment of the present invention
- FIG. 4 is a partly plan view (A) and a partly sectional view (B) illustrating a semiconductor device according to a third embodiment of the present invention.
- FIG. 5 is a partly plan view depicting a semiconductor device according to a fourth embodiment of the present invention.
- FIG. 1 is a partially plan view (A) and a partially sectional view (B) showing a semiconductor device according to a first embodiment of the present invention.
- FIG. 2 is a process view showing a method of manufacturing the semiconductor device according to the first embodiment of the present invention.
- FIG. 1(A) a gate wiring pattern 12 (wiring pattern) is formed on a semiconductor substrate 10 , and a plurality of dummy patterns 14 are formed therearound.
- a BPSG (Boro Phospho Silicate Glass) oxide film 16 (insulating film) which is planarized by CMP is formed on the gate wiring pattern 12 and the dummy patterns 14 as an interlayer insulating film.
- FIG. 1(B) is a sectional view taken along line B-B in FIG. 1(A) .
- stripe-like slits 14 b are provided among a plurality of linear patterns 14 a.
- the width of each of the slits 14 b provided at the dummy patterns 14 is set so that a width of the slit 14 b is filled by plus sizing of each dummy pattern upon formation of the interlayer insulating film. Described specifically, the width which is filled by plus sizing is 72 ⁇ m or less, for example.
- a plurality of dummy patterns 14 are formed on a semiconductor substrate 10 together with a gate wiring pattern 12 by using a gate electrode forming mask (see FIG. 2(A) ).
- a BPSG oxide film 16 is formed on the gate wiring pattern 12 and the dummy patterns 14 by a chemical vapor deposition method. Since plus sizing of the dummy patterns occurs first at this time, a constituent material used for a BPSG oxide film 16 is deposited from the side surfaces of linear patterns 14 a so that slits 14 b of the dummy patterns 14 are filled (see FIG. 2(B) ). Thereafter, a BPSG oxide film 16 is formed (see FIG. 2(C) ).
- the surface of the BPSG oxide film 16 is smoothed by CMP (see FIG. 2(D) ).
- the semiconductor device is fabricated in this way.
- the dummy patterns 14 are provided with the slits 14 b each having a predetermined width, and the slits 14 b are filled by dummy pattern plus sizing upon vapor phase growth of the BPSG oxide film 16 . Therefore, the BPSG oxide film 16 is formed at the coverage which is no different from dummy patterns 14 (conventional dummy patterns) with no slits 14 b.
- the interval between lattices is varied to make it possible to easily optimize the pattern ratio. It is thus possible to suppress an increase in the global step more effectively.
- FIG. 3 is a partially plan view (A) and a partially sectional view (B) showing a semiconductor device according to a second embodiment of the present invention.
- the second embodiment takes a form in which arbitrary graphical (“square” in the second embodiment) openings 14 c (pattern non-forming regions) are respectively provided at the centers of square (square-shaped) dummy patterns 14 .
- FIG. 3(B) is a sectional view taken along line B-B in FIG. 3(A) . Since elements of structure other than the above are similar to those employed in the first embodiment, the description thereof will be omitted.
- the first embodiment has explained the form in which the plurality of linear patterns 14 a have built up the dummy patterns 14 (the dummy patterns 14 provided with the slits 14 b ) which are arranged at the predetermined intervals.
- the dummy patterns are constituted of the plurality of linear patterns 14 a in this case, the number of graphic forms increases and hence the dummy patterns 14 (linear patterns 14 a ) are inserted in large numbers.
- GDS2 data design data file
- the square dummy patterns 14 which are provided with the arbitrary graphical openings 14 c at their centers are formed to thereby suppress an increase in the number of graphical forms in the second embodiment.
- the width of the opening 14 c is similar to the width of the slit 14 b employed in the first embodiment.
- the form of the opening 14 c is not limited to the square but can be configured as any other arbitrary graphical form.
- the second embodiment is capable of obtaining a global step which is equivalent to one obtained where the conventional dummy patterns are provided, while reducing the pattern ratio by the provision of the opening 14 c at each dummy pattern 14 , in a manner similar to the first embodiment. Further, the second embodiment is capable of reducing the design data file capacity (GDS2 data) and improving its practical handling.
- GDS2 data design data file capacity
- FIG. 4 is a partially plan view (A) and a partially sectional view (B) showing a semiconductor device according to a third embodiment of the present invention.
- the present embodiment takes a form in which arbitrary character-shaped (“A” in the third embodiment) openings 14 c (pattern non-forming regions) are respectively provided at the centers of square dummy patterns 14 as shown in FIG. 4 .
- FIG. 4(B) is a sectional view taken along line B-B in FIG. 4(A) . Since elements of structure other than the above are similar to those employed in the second embodiment, the description thereof will be omitted.
- the gate wiring pattern 12 and the dummy patterns 14 can be easily identified since the shapes of the openings 14 c are represented in arbitrary character form.
- FIG. 5 is a partly plan view showing a semiconductor device according to a fourth embodiment of the present invention.
- the fourth embodiment takes a form in which square dummy patterns 14 are respectively provided with arbitrary character-shaped or graphical (“numerals” in the fourth embodiment) openings 14 c (pattern non-forming regions) which are different for each of the dummy patterns 14 as shown in FIG. 5 . Since the fourth embodiment is similar to the third embodiment except for the above, the description of the similar elements of structure will be omitted.
- the dummy patterns 14 can be used as addresses. It is thus possible to easily identify a specific pattern lying in the semiconductor device.
- the present invention is not limited thereto.
- the present invention can be applied even to a metal wiring pattern which is formed upon wiring multilayering, 3-dimensioning of a semiconductor device or the like.
- the BPSG oxide film has been described as the interlayer insulating film by way of illustration, the present invention is not limited thereto.
- one that causes a similar phenomenon such as a high density plasma CVD (High Density Plasma-Chemical Vapor Deposition: HDP-CVD) oxide film is also applicable.
- HDP-CVD High Density Plasma-Chemical Vapor Deposition
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
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- Semiconductor Integrated Circuits (AREA)
Abstract
A semiconductor device which is capable of avoiding an increase in pattern ratio and allowing wiring dummy patterns to improve global steps developed by CMP upon insertion of the dummy patterns which are different from an actual wiring pattern. The semiconductor device has a configuration wherein a gate wiring pattern is formed on a semiconductor substrate, a plurality of dummy patterns are provided therearound, and a BPSG oxide film which is flattened by CMP is formed on the gate wiring pattern and the dummy patterns as an interlayer insulating film. In the semiconductor device, the dummy patterns are formed so as to include pattern non-forming regions such as slits.
Description
- 1. Field of the Invention
- The present invention relates to a semiconductor device wherein dummy patterns are formed on a semiconductor substrate together with a wiring pattern, and to a method of manufacturing the semiconductor device.
- 2. Description of the Related Art
- In an interlayer film CMP (Chemical mechanical polishing) process, batch polishing has heretofore been performed to reach an intended or target remaining film thickness set value. When, at this time, a polishing pad which is brought into contact with the surface of a wafer is elastically deformed due to pressure from an underlying step at an initial polishing stage, the pressure that is applied from the polishing pad increases when a pattern density is low, whereas the pressure that is applied from the polishing pad is dispersed and becomes low when the pattern density is high, thus causing a difference in the polishing rate between loose and dense wiring pattern portions.
- Thus, the remaining film thickness differences (hereinafter might be called “global steps”) occur among the loose and dense wiring pattern portions after polishing. Each of the global steps consists of a difference in film thickness at the loosest portion and the densest portion of the underlying wiring pattern. The global steps are different from one another according to a wiring layout. Therefore, when the global step is large in the interlayer film CMP process, the underlying wiring pattern is exposed or disappears at the loose portion of the underlying wiring pattern, and the residual step occurs due to cutting insufficiency at the dense portion of the underlying wiring pattern.
- When such exposure, disappearance and residual steps of the underlying wiring pattern occur, no wiring is formed upon forming each wiring in a subsequent process, thus causing degradation in yield and reliability.
- Therefore, dummy patterns (pseudo dummy patterns) which are different from an actual wiring pattern are inserted into the entire surface of a chip to set the global steps as low as possible (refer to, for example, a patent document: Japanese Unexamined Patent Publication No. 2003-140319). The global steps vary depending on whether the dummy patterns exist. The insertion of the dummy patterns provides an improvement in the global step.
- However, a disadvantage occurs in that when the dummy patterns are inserted, a pattern ratio (pattern proportion) of a mask becomes too large to carry out an end point detector (EPD) upon etching at the formation of a wiring pattern. Therefore, there is a demand for suppressing the insertion of the dummy patterns as low as practicable to thereby reduce the global steps.
- While the dummy patterns may preferably be inserted to improve the global steps in this way, a disadvantage occurs in that when the pattern ratio become excessively large, EPD cannot be detected upon etching of the wiring pattern.
- In view of the foregoing problems, the present invention therefore provides a semiconductor device which is capable of avoiding an increase in pattern ratio and allowing wiring dummy patterns to improve global steps developed by CMP upon the insertion of the dummy patterns which are different from an actual wiring pattern, and a method of manufacturing the semiconductor device.
- The above-described problems are solved by the following aspects of the present invention:
- A semiconductor device of the present invention comprises a wiring pattern and a plurality of dummy patterns which are different from the wiring pattern, and an insulating film which is formed on the wiring pattern and the dummy patterns by a chemical vapor deposition method. The dummy patterns are provided with pattern non-forming regions each having a width which is filled by plus sizing of the insulating film upon formation of the insulating film.
- The pattern non-forming regions of the dummy patterns may be formed in stripe form or may be formed in character or graphical form.
- In the semiconductor device of the present invention, the pattern non-forming regions of the dummy patterns may preferably be shaped in character or graphical forms which are different for each dummy pattern.
- In the semiconductor device of the present invention, the dummy patterns may preferably be square. Also, the dummy patterns may preferably be arranged in lattice form.
- The present invention also provides a method of manufacturing a semiconductor device, which comprises the following steps of: forming a wiring pattern; forming a plurality of dummy patterns which are different from the wiring pattern together with the wiring pattern; and forming an insulating film on the wiring pattern and the dummy patterns by a chemical vapor deposition method.
- In the dummy pattern forming step, the dummy patterns are formed so as to be provided with pattern non-forming regions each having a width which is filled by plus sizing of the insulating film upon formation of the insulating film.
- In the dummy pattern forming step, the pattern non-forming regions of the dummy patterns may be formed in stripe form or may be formed in character or graphical form.
- In the dummy pattern forming step, the pattern non-forming regions of the dummy patterns may preferably be shaped in character or graphical forms which are different for each dummy pattern.
- In the dummy pattern forming step, the dummy patterns may be shaped in square form. Also, the dummy patterns may be arranged and formed in lattice form.
- In the present invention, dummy patterns formed together with a wiring pattern are respectively provided with pattern non-forming regions each having a predetermined width. The predetermined width of the pattern non-forming region is defined as a width which is filled with an insulating film by plus sizing of the insulating film upon formation of the insulating film. Then, the insulating film is formed on the wiring pattern and the dummy patterns.
- Here, the plus sizing of the insulating film is to deposit an insulating film material not only on a pattern upper surface but also on pattern sidewalls upon vapor phase growth of the insulating film and increase the size of each pattern at a predetermined rate. The width of each of the pattern non-forming regions of the dummy patterns is equivalent to the shortest distance between the pattern sidewalls at individual points lying in the pattern non-forming regions.
- Therefore, since the pattern non-forming regions are filled with the insulating film material which is deposited on the pattern sidewalls upon vapor phase growth of the insulating film, the coverage of the insulating film remains unchanged at dummy patterns (conventional dummy patterns) which are provided with no pattern non-forming regions and the dummy patterns which are provided with the pattern non-forming regions.
- When the formed insulating film is planarized, global steps equivalent to ones which are obtained when the dummy patterns provided with no pattern non-forming regions are provided, can be obtained while reducing a pattern ratio by the provision of the pattern non-forming regions at the dummy patterns.
- According to the semiconductor device of the present invention and its manufacturing method, an advantageous effect is achieved in that upon insertion of dummy patterns which are different from an actual wiring pattern, a pattern ratio can be prevented from increasing, and the wiring dummy patterns enable an improvement in the global step of CMP.
- While the specification concludes with claims particularly pointing out and distinctly claiming the subject matter which is regarded as the present invention, it is believed that the present invention, the objects and features of the present invention and further objects, features and advantages thereof will be better understood from the following description when taken in connection with the accompanying drawings in which:
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FIG. 1 is a partly plan view (A) and a partly sectional view (B) showing a semiconductor device according to a first embodiment of the present invention; -
FIG. 2 is a process view illustrating a method of manufacturing the semiconductor device according to the first embodiment of the present invention; -
FIG. 3 is a partly plan view (A) and a partly sectional view (B) showing a semiconductor device according to a second embodiment of the present invention; -
FIG. 4 is a partly plan view (A) and a partly sectional view (B) illustrating a semiconductor device according to a third embodiment of the present invention; and -
FIG. 5 is a partly plan view depicting a semiconductor device according to a fourth embodiment of the present invention. - The present invention will be described hereinbelow with reference to the accompanying drawings. Incidentally, structural components each substantially having the same function will be explained with the same reference numerals given thereto through all of the drawings.
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FIG. 1 is a partially plan view (A) and a partially sectional view (B) showing a semiconductor device according to a first embodiment of the present invention.FIG. 2 is a process view showing a method of manufacturing the semiconductor device according to the first embodiment of the present invention. - In the semiconductor device according to the first embodiment, as shown in
FIG. 1(A) , a gate wiring pattern 12 (wiring pattern) is formed on asemiconductor substrate 10, and a plurality ofdummy patterns 14 are formed therearound. As shown inFIG. 1(B) , a BPSG (Boro Phospho Silicate Glass) oxide film 16 (insulating film) which is planarized by CMP is formed on thegate wiring pattern 12 and thedummy patterns 14 as an interlayer insulating film. Here,FIG. 1(B) is a sectional view taken along line B-B inFIG. 1(A) . - In the
dummy patterns 14, stripe-like slits 14 b (pattern forming regions) are provided among a plurality oflinear patterns 14 a. - The width of each of the
slits 14 b provided at thedummy patterns 14 is set so that a width of theslit 14 b is filled by plus sizing of each dummy pattern upon formation of the interlayer insulating film. Described specifically, the width which is filled by plus sizing is 72 μm or less, for example. - A method of manufacturing the semiconductor device according to the present embodiment will now be described.
- First, a plurality of
dummy patterns 14 are formed on asemiconductor substrate 10 together with agate wiring pattern 12 by using a gate electrode forming mask (seeFIG. 2(A) ). - Next, a
BPSG oxide film 16 is formed on thegate wiring pattern 12 and thedummy patterns 14 by a chemical vapor deposition method. Since plus sizing of the dummy patterns occurs first at this time, a constituent material used for aBPSG oxide film 16 is deposited from the side surfaces oflinear patterns 14 a so that slits 14 b of thedummy patterns 14 are filled (seeFIG. 2(B) ). Thereafter, aBPSG oxide film 16 is formed (seeFIG. 2(C) ). - Then, the surface of the
BPSG oxide film 16 is smoothed by CMP (seeFIG. 2(D) ). The semiconductor device is fabricated in this way. - In the first embodiment as described above, the
dummy patterns 14 are provided with theslits 14 b each having a predetermined width, and theslits 14 b are filled by dummy pattern plus sizing upon vapor phase growth of theBPSG oxide film 16. Therefore, theBPSG oxide film 16 is formed at the coverage which is no different from dummy patterns 14 (conventional dummy patterns) with noslits 14 b. - Therefore, when the
BPSG oxide film 16 is planarized, global steps which are equivalent to ones obtained when the conventional dummy patterns are provided, can be obtained while reducing a pattern ratio by the provision of theslits 14 b at thedummy patterns 14. - Since the
dummy patterns 14 are arranged in lattice form in the first embodiment, the interval between lattices is varied to make it possible to easily optimize the pattern ratio. It is thus possible to suppress an increase in the global step more effectively. -
FIG. 3 is a partially plan view (A) and a partially sectional view (B) showing a semiconductor device according to a second embodiment of the present invention. - As shown in
FIG. 3 , the second embodiment takes a form in which arbitrary graphical (“square” in the second embodiment)openings 14 c (pattern non-forming regions) are respectively provided at the centers of square (square-shaped)dummy patterns 14. Here,FIG. 3(B) is a sectional view taken along line B-B inFIG. 3(A) . Since elements of structure other than the above are similar to those employed in the first embodiment, the description thereof will be omitted. - The first embodiment has explained the form in which the plurality of
linear patterns 14 a have built up the dummy patterns 14 (thedummy patterns 14 provided with theslits 14 b) which are arranged at the predetermined intervals. However, since the dummy patterns are constituted of the plurality oflinear patterns 14 a in this case, the number of graphic forms increases and hence the dummy patterns 14 (linear patterns 14 a) are inserted in large numbers. As a result, a problem arises in that since the number of graphic forms increases as compared with the capacity of a design data file (GDS2 data) at the insertion of mere square dummy patterns (dummy patterns 14 with noslits 14 b), data capacity is inevitable and its practical handling is inconvenient. - Thus, the
square dummy patterns 14 which are provided with the arbitrarygraphical openings 14 c at their centers are formed to thereby suppress an increase in the number of graphical forms in the second embodiment. The width of theopening 14 c is similar to the width of theslit 14 b employed in the first embodiment. Also, the form of theopening 14 c is not limited to the square but can be configured as any other arbitrary graphical form. - Therefore, the second embodiment is capable of obtaining a global step which is equivalent to one obtained where the conventional dummy patterns are provided, while reducing the pattern ratio by the provision of the
opening 14 c at eachdummy pattern 14, in a manner similar to the first embodiment. Further, the second embodiment is capable of reducing the design data file capacity (GDS2 data) and improving its practical handling. -
FIG. 4 is a partially plan view (A) and a partially sectional view (B) showing a semiconductor device according to a third embodiment of the present invention. - The present embodiment takes a form in which arbitrary character-shaped (“A” in the third embodiment)
openings 14 c (pattern non-forming regions) are respectively provided at the centers ofsquare dummy patterns 14 as shown inFIG. 4 . Here,FIG. 4(B) is a sectional view taken along line B-B inFIG. 4(A) . Since elements of structure other than the above are similar to those employed in the second embodiment, the description thereof will be omitted. - In the third embodiment, the
gate wiring pattern 12 and thedummy patterns 14 can be easily identified since the shapes of theopenings 14 c are represented in arbitrary character form. -
FIG. 5 is a partly plan view showing a semiconductor device according to a fourth embodiment of the present invention. - The fourth embodiment takes a form in which square
dummy patterns 14 are respectively provided with arbitrary character-shaped or graphical (“numerals” in the fourth embodiment)openings 14 c (pattern non-forming regions) which are different for each of thedummy patterns 14 as shown inFIG. 5 . Since the fourth embodiment is similar to the third embodiment except for the above, the description of the similar elements of structure will be omitted. - Since the shapes of the
openings 14 c are set to the character-like or graphical forms which are different for each of thedummy patterns 14 in the fourth embodiment, thedummy patterns 14 can be used as addresses. It is thus possible to easily identify a specific pattern lying in the semiconductor device. - Although any of the embodiments has explained the gate electrode pattern as the wiring pattern by way of illustration, the present invention is not limited thereto. The present invention can be applied even to a metal wiring pattern which is formed upon wiring multilayering, 3-dimensioning of a semiconductor device or the like. Although the BPSG oxide film has been described as the interlayer insulating film by way of illustration, the present invention is not limited thereto. For example, one that causes a similar phenomenon, such as a high density plasma CVD (High Density Plasma-Chemical Vapor Deposition: HDP-CVD) oxide film is also applicable.
- While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the present invention, will be apparent to those skilled in the art with reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments which fall within the true scope of the present invention.
Claims (9)
1. A method of manufacturing a semiconductor device including a semiconductor substrate having a pattern forming region and a pattern non-forming region, a wiring pattern formed on the pattern forming region, a plurality of dummy patterns formed on the pattern non-forming region, the plurality of dummy patterns being formed within a plurality of dummy areas, each of the plurality of dummy areas having a same shape, and including an insulating film formed on the wiring pattern and the plurality of dummy patterns, wherein each of the dummy patterns has a plurality of parallel line patterns, each of the line patterns of the plurality of line patterns being spaced apart from each other by an area filled by the deposition of the insulating film, and wherein a distance between each of the line patterns of the plurality of line patterns is less than 72 μm, the method comprising:
forming the wiring pattern and the dummy patterns above the semiconductor substrate;
forming the insulating film on the wiring pattern and the dummy patterns by chemical vapor deposition, an area between line patterns being filled by the insulating film; and
smoothing the insulating film by chemical mechanical polishing.
2. The method according to claim 1 , wherein the insulating film is Boro Phospho Silicate Glass (BPSG) oxide film.
3. The method according to claim 1 , wherein the insulating film is High Density Plasma-Chemical Vapor Deposition (HDP-CVD) oxide film.
4. A method of manufacturing a semiconductor device including a semiconductor substrate having a pattern area and a non-pattern area, a conductive pattern formed on the pattern area of the semiconductor substrate, a plurality of dummy patterns formed on the non-pattern area of the semiconductor substrate, each of the plurality of dummy patterns having a same continuous rectangular outline shape as each other and being arranged in a matrix with predetermined spacing, and an insulating film formed on the conductive pattern and the plurality of dummy patterns, wherein each of the dummy patterns has only one square-shaped opening so that a pattern ratio of the semiconductor device is reduced, and wherein a width of the opening of each of the dummy patterns is less than 72 μm, the method comprising:
forming the conductive pattern and the dummy patterns above the semiconductor substrate;
forming the insulating film on the conductive pattern and the dummy patterns by chemical vapor deposition, the opening of each dummy pattern being filled by the insulating film; and
smoothing the insulating film by chemical mechanical polishing.
5. The method according to claim 4 , wherein the insulating film is Boro Phospho Silicate Glass (BPSG) oxide film.
6. The method according to claim 4 , wherein the insulating film is High Density Plasma-Chemical Vapor Deposition (HDP-CVD) oxide film.
7. A method of manufacturing a semiconductor device including a semiconductor substrate having a pattern area and a non-pattern area, a conductor pattern formed on the pattern area of the semiconductor substrate, a plurality of dummy patterns formed on the non-pattern area of the semiconductor substrate, and an insulating film formed on the conductive pattern and the plurality of dummy patterns, wherein each of the plurality of dummy patterns are formed in a plurality of dummy areas, each of the plurality of dummy areas having a same shape, and each of the plurality of dummy patterns being arranged in a matrix with predetermined spacing, wherein each of the dummy patterns has a space portion within each of the dummy areas so that a pattern ratio of the semiconductor device is reduced, and wherein each of the dummy patterns includes an opening at the space portion, the opening having a shape of a letter or a number, each opening of the dummy patterns having a width less than 72 μm, the method comprising:
forming the conductor pattern and the dummy patterns above the semiconductor substrate;
forming the insulating film on the conductor pattern and the dummy patterns by chemical vapor deposition, the opening of each dummy pattern being filled by the insulating film; and
smoothing the insulating film by chemical mechanical polishing.
8. The method according to claim 7 , wherein the insulating film is Boro Phospho Silicate Glass (BPSG) oxide film.
9. The method according to claim 7 , wherein the insulating film is High Density Plasma-Chemical Vapor Deposition (HDP-CVD) oxide film.
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US12/320,346 US20090203209A1 (en) | 2003-10-30 | 2009-01-23 | Semiconductor device and method of manufacturing the same |
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JP370060/2003 | 2003-10-30 | ||
JP2003370060A JP2005136135A (en) | 2003-10-30 | 2003-10-30 | Semiconductor device and manufacturing method thereof |
US10/766,471 US7569936B2 (en) | 2003-10-30 | 2004-01-29 | Semiconductor device and method of manufacturing the same |
US12/320,346 US20090203209A1 (en) | 2003-10-30 | 2009-01-23 | Semiconductor device and method of manufacturing the same |
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US10/766,471 Continuation US7569936B2 (en) | 2003-10-30 | 2004-01-29 | Semiconductor device and method of manufacturing the same |
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US20090203209A1 true US20090203209A1 (en) | 2009-08-13 |
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US12/320,346 Abandoned US20090203209A1 (en) | 2003-10-30 | 2009-01-23 | Semiconductor device and method of manufacturing the same |
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Cited By (1)
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US20130174780A1 (en) * | 2012-01-09 | 2013-07-11 | Suk-Beom You | Deposition mask and deposition device using the same |
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KR100924337B1 (en) * | 2007-06-25 | 2009-11-02 | 주식회사 하이닉스반도체 | Method for forming wafer patterns of semiconductor devices |
JP5530804B2 (en) | 2010-05-17 | 2014-06-25 | パナソニック株式会社 | Semiconductor device, mask for manufacturing semiconductor device, and optical proximity correction method |
JP6044260B2 (en) | 2012-10-22 | 2016-12-14 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor wafer and semiconductor device |
US9107302B2 (en) * | 2013-02-12 | 2015-08-11 | Raytheon Company | Dummy structure for visual aid in printed wiring board etch inspection |
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US20050093165A1 (en) | 2005-05-05 |
US7569936B2 (en) | 2009-08-04 |
JP2005136135A (en) | 2005-05-26 |
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