US20060049449A1 - Non-volatile semiconductor memory and method for fabricating a non-volatile semiconductor memory - Google Patents

Non-volatile semiconductor memory and method for fabricating a non-volatile semiconductor memory Download PDF

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US20060049449A1
US20060049449A1 US11/103,612 US10361205A US2006049449A1 US 20060049449 A1 US20060049449 A1 US 20060049449A1 US 10361205 A US10361205 A US 10361205A US 2006049449 A1 US2006049449 A1 US 2006049449A1
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memory cell
volatile semiconductor
source
cell transistors
semiconductor memory
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Naohisa Iino
Yasuhiko Matsunaga
Fumitaka Arai
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Toshiba Corp
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Toshiba Corp
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ARAI, FUMITAKA, IINO, NAOHISA, MATSUNAGA, YASUHIKO
Publication of US20060049449A1 publication Critical patent/US20060049449A1/en
Priority to US11/832,459 priority Critical patent/US7750417B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series

Definitions

  • This present invention relates to a non-volatile semiconductor memory, more particularly, a non-volatile semiconductor memory and a method for fabricating the same using Silicon On Insulator (SOI) technique.
  • SOI Silicon On Insulator
  • EEPROM electrically erasable programmable read-only memory
  • a cell array is comprised in such a way that a memory cell transistor is arranged at an intersection where a word line in the row direction and a bit line in the column direction cross over each other.
  • EEPROMS the NAND flash EEPROM in which a plurality of memory cell transistors are connected in series, and which can erase all the written data simultaneously, has been in wide use.
  • a memory cell transistor of the NAND flash EEPROM includes n + -source and drain regions which are opposite to each other; and a p channel region between the source and drain regions.
  • a stacked gate structure is formed on the channel region in which a control gate electrode and a floating gate electrode are stacked.
  • Memory cell transistors adjacent to one another in the row direction are isolated from one another by an element isolation region.
  • the NAND flash EEPROM experiences of fluctuations in gate threshold voltage due to influence of parasitic capacitance in the element isolation region between memory cell transistors and parasitic capacitance between an interconnect and a substrate, and the like.
  • a NAND flash EEPROM which employs SOI technology in which a semiconductor layer (SOI layer), arranged on the an embedded insulating layer (SOI insulator), serves as an active layer.
  • SOI layer semiconductor layer
  • SOI insulator embedded insulating layer
  • the memory cell transistors adjacent to one another in the row direction are isolated from one another by the element isolation insulating film which is embedded as far as the SOI insulator, thereby enabling the parasitic capacitance in the element isolation region be reduced.
  • the SOI layer is formed on the SOI insulator, the parasitic capacitance between the interconnect and the substrate can be reduced, and hence the fluctuation in the gate threshold voltage can be reduced.
  • an interval between the source and the drain of the memory cell transistor has become so narrower that influence of the short channel effect has increased in the NAND flash EEPROM employing the SOI technology.
  • An aspect of the present invention inheres in a non-volatile semiconductor memory comprising memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor.
  • Another aspect of the present invention inheres in a non-volatile semiconductor memory having a plurality of memory cell transistors arranged in a matrix, wherein each of the memory cell transistors is a depletion mode MIS transistor including: source and drain regions having a first conductivity type disposed on an insulating layer; a channel region having the first conductivity type disposed between the source and drain regions, and having a lower impurity concentration than the source and drain regions; a floating gate electrode disposed above the channel region and insulated from the channel region; and a control gate electrode disposed above the floating gate electrode and insulated from the floating electrode.
  • MIS transistor including: source and drain regions having a first conductivity type disposed on an insulating layer; a channel region having the first conductivity type disposed between the source and drain regions, and having a lower impurity concentration than the source and drain regions; a floating gate electrode disposed above the channel region and insulated from the channel region; and a control gate electrode disposed above the floating gate electrode and insulated from the floating electrode
  • FIG. 1 is a cross-sectional view in the column direction (I-I direction of FIG. 2 ) showing an example of a cell array of a non-volatile semiconductor memory according to an embodiment of the present invention.
  • FIG. 2 is a plan view showing an example of the cell array of the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 3 is a cross-sectional view in the row direction (II-II direction of FIG. 2 ) showing an example of the cell array of the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 4 is an equivalent circuit diagram showing an example of the cell array of the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 5 is a graph showing an example of I-V characteristic of a memory cell transistor of the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 6 is a chart showing an example of operation voltage supplying to a wiring of the cell array of the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 7 is an equivalent circuit diagram for explaining writing operation of the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 8 is an equivalent circuit diagram for explaining erasing operation of the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 9 is an equivalent circuit diagram for explaining reading operation of the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 10 is a cross-sectional view for explaining a floating gate electrode, which does not store electron of the memory cell transistor of the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 11 is a cross-sectional view for explaining the floating gate electrode stores electron of the memory cell transistor of the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 12A is a cross-sectional view in the column direction (III-III direction of FIG. 2 ) showing an example of a method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 12B is a cross-sectional view in the column direction (II-II direction of FIG. 2 ) showing an example of the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 13A is a cross-sectional view in the column direction after the process of FIG. 12A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 13B is a cross-sectional view in the row direction after the process of FIG. 12B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 14A is a cross-sectional view in the column direction after the process of FIG. 13A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 14B is a cross-sectional view in the row direction after the process of FIG. 13B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 15A is a cross-sectional view in the column direction after the process of FIG. 14A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 15B is a cross-sectional view in the row direction after the process of FIG. 14B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 16A is a cross-sectional view in the column direction after the process of FIG. 15A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 16B is a cross-sectional view in the row direction after the process of FIG. 15B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 17A is a cross-sectional view in the column direction after the process of FIG. 16A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 17B is a cross-sectional view in the row direction after the process of FIG. 16B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 18A is a cross-sectional view in the column direction after the process of FIG. 17A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 18B is a cross-sectional view in the row direction after the process of FIG. 17B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 19A is a cross-sectional view in the column direction after the process of FIG. 18A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 19B is a cross-sectional view in the row direction after the process of FIG. 18B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 20A is a cross-sectional view in the column direction after the process of FIG. 19A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 20B is a cross-sectional view in the row direction after the process of FIG. 19B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 21A is a cross-sectional view in the column direction after the process of FIG. 20A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 21B is a cross-sectional view in the row direction after the process of FIG. 20B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 22A is a cross-sectional view in the column direction after the process of FIG. 21A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 22B is a cross-sectional view in the row direction after the process of FIG. 21B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 23A is a cross-sectional view in the column direction after the process of FIG. 22A showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 23B is a cross-sectional view in the row direction after the process of FIG. 22B showing the method for fabricating the non-volatile semiconductor memory according to the embodiment of the present invention.
  • FIG. 24 is a cross-sectional view showing an example of a memory cell transistor of a non-volatile semiconductor memory according to a first modification of the present invention.
  • FIG. 25 is a cross-sectional view for explaining operation of the memory cell transistor of the non-volatile semiconductor memory according to the first modification of the present invention.
  • FIG. 26 is a cross-sectional view in the column direction (III-III direction of FIG. 2 ) showing an example of a method for fabricating the non-volatile semiconductor memory according to a second modification of the present invention.
  • FIG. 27 is a cross-sectional view in the column direction after the process of FIG. 26 showing the method for fabricating the non-volatile semiconductor memory according to the second modification of the present invention.
  • FIG. 28 is a cross-sectional view in the column direction showing an example of a cell array of a non-volatile semiconductor memory according to a third modification of the present invention.
  • FIG. 29 is a cross-sectional view showing an example of a peripheral circuit in the non-volatile semiconductor memory according to the third modification of the present invention.
  • FIG. 30A is a cross-sectional view showing an example of method for fabricating a cell array of a non-volatile semiconductor memory according to the third modification of the present invention.
  • FIG. 30B is a cross-sectional view showing a method for fabricating a peripheral circuit of the non-volatile semiconductor memory according to the third modification of the present invention.
  • FIG. 31A is a cross-sectional view after the process of FIG. 30A showing the method for fabricating the cell array of the non-volatile semiconductor memory according to the third modification of the present invention.
  • FIG. 31B is a cross-sectional view after the process of FIG. 30B showing the method for fabricating the peripheral circuit of the non-volatile semiconductor memory according to the third modification of the present invention.
  • FIG. 32A is a cross-sectional view after view FIG. 31A showing the method for fabricating the cell array of the non-volatile semiconductor memory according to the third modification of the present invention.
  • FIG. 32B is a cross-sectional view after the process of FIG. 31B showing the method for fabricating the peripheral circuit of the non-volatile semiconductor memory according to the third modification of the present invention.
  • FIG. 33A is a cross-sectional view after view FIG. 32A showing the method for fabricating the cell array of the non-volatile semiconductor memory according to the third modification of the present invention.
  • FIG. 33B is a cross-sectional view after the process of FIG. 32B showing the method for fabricating the peripheral circuit of the non-volatile semiconductor memory according to the third modification of the present invention.
  • FIG. 34A is a cross-sectional view after view FIG. 33A showing the method for fabricating the cell array of the non-volatile semiconductor memory according to the third modification of the present invention.
  • FIG. 34B is a cross-sectional view after the process of FIG. 33B showing the method for fabricating the peripheral circuit of the non-volatile semiconductor memory according to the third modification of the present invention.
  • FIG. 35 is a cross-sectional view showing another example of a peripheral circuit in a non-volatile semiconductor memory according to the third modification of the present invention.
  • FIG. 36 is a circuit diagram showing an example of a two-transistor type cell array in a non-volatile semiconductor memory according to the fourth modification of the present invention.
  • FIG. 37 is a block diagram showing an example of a flash memory system using a non-volatile semiconductor memory according to the fifth modification of the present invention.
  • FIG. 38 is a cross-sectional view in the column direction showing an example of a non-volatile semiconductor memory according to the sixth modification of the present invention.
  • FIG. 39 is a cross-sectional view in the row direction showing an example of a non-volatile semiconductor memory according to the sixth modification of the present invention.
  • FIG. 40 is a cross-sectional view showing another example of a non-volatile semiconductor memory according to the sixth modification of the present invention.
  • FIG. 41 is a cross-sectional view in the row direction showing a cell array of a non-volatile semiconductor memory according to a comparative example.
  • FIG. 42 is a cross-sectional view in the row direction showing the call array of a non-volatile semiconductor memory according to the comparative example.
  • a non-volatile semiconductor memory is an insulating film (SOI insulator) and an NAND flash EEPROM in which a plurality of memory cell transistors are arranged in a matrix on the SOI insulator.
  • FIG. 1 is a cross-sectional view of the non-volatile semiconductor memory taken along the I-I line in the column direction as shown in FIG. 2 .
  • the memory cell transistors MT 11 to MT 1n are depletion mode MIS transistors including source and drain regions 421 to 42 (n+1) having a first conductivity (n + ) type.
  • the memory cell transistors MT 11 to MT 1n are arranged on the SOI insulator 1 , and are opposite to each other.
  • Channel regions 411 to 41 n having a first conductivity (n ⁇ ) type are interposed between each adjacent pair of the source and drain regions 421 to 42 (n+1).
  • the impurity concentrations of the channel regions 411 to 41 n are lower than that of the source and drain regions 421 to 42 ( n+ 1).
  • Floating gate electrodes 13 are insulated, and each is arranged above each of the channel regions 411 to 41 n.
  • Control gate electrodes 15 are insulated, and each is arranged above each of the floating gate electrodes 13 .
  • the memory cell transistors MT 11 to MT 1n include the channel regions 411 to 41 n having a conductivity which is the same as that of the source and drain regions 421 to 42 ( n+ 1), thereby constituting the depletion mode MIS transistors.
  • the “MIS transistor” is an insulated gate transistor, such as a field effect transistor (FET) and a static induction transistor (SIT), which controls channel current by gate voltage through an insulating film (gate insulating film) interposed between a gate electrode and a channel region.
  • FET field effect transistor
  • SIT static induction transistor
  • a MISFET in which a silicon oxide film (SiO 2 film) is used as a gate insulating film is referred to as a metal oxide semiconductor field effect transistor (MOSFET).
  • SiO 2 silicon nitride (Si 3 N 4 ) tantalum oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ), alumina (Al 2 O 3 ), zirconium oxide (ZrO 2 ) and the like can be used as a material for the gate insulating film of the MIS transistor.
  • n (n is an integer) memory cell transistors MT 11 to MT 1n are arranged in the column direction so that they are adjacent to one another.
  • Each of the memory cell transistors MT 11 to MT 1n is a depletion mode MIS transistor including: the source and drain regions 421 to 42 ( n+ 1), each of which is common to each adjacent pair of the memory cell transistors MT 11 to MT 1n ; floating gate electrodes 13 , each of which is arranged above one of the channel regions 411 to 41 n interposed between each adjacent pair of the source and drain regions 421 to 42 ( n+ 1) with a gate insulating film (tunnel oxide film) 12 interposed between the floating gate electrode and the channel region; and control gate electrodes 15 , each of which is arranged above each of the floating gate electrodes 13 with an inter-electrode insulating film 14 interposed between the control gate electrode and the floating gate electrode.
  • Each of the memory cell transistors Mt 11 to MT 11 is a depletion mode MIS transistor implemented by a stacked gate structure in which the floating gate electrodes 13 and the control gate electrodes 15 are stacked.
  • SiO 2 , sapphire (Al 2 O 3 ) and the like can be used as materials of the SOI insulator 1 with which an SOI structure is provided.
  • Single crystal silicon, silicon germanium (SiGe) and the like can be used as a material for an semiconductor layer (SOI layer) 2 provided on the top of the SOI insulating film 1 .
  • SOI layer semiconductor layer
  • the n ⁇ channel regions 411 to 41 n and the n + -source and drain regions 421 to 42 ( n+ 1) are arranged in the SOI insulating layer 2 .
  • Each of the source regions 421 to 42 n, each of the channel regions 411 to 41 n and each of the drain regions 422 to 42 ( n+ 1) are arranged alternately in one column direction so that, out of the plurality of memory cell transistors MT 11 to MT 1n arranged in the column direction in the matrix, the drain region 422 of one memory cell transistor MT 11 serves as the source region 422 of another memory cell transistor MT 12 , adjacent to the memory cell transistor MT 11 .
  • the memory cell transistors MT 11 to MT mn are arranged in a plurality of parallel columns so that the source regions 421 to 42 n, the channel regions 411 to 41 n and the drain regions 422 to 42 ( n+ 1) are isolated from the corresponding source regions, channel regions and drain regions in other columns.
  • the select gate transistor STS 1 is an enhancement MIS transistor including: an n + drain region 421 which is common a source region 421 of the memory cell transistor MT 11 positioned in one end of the arrangement in the column direction; a channel region 42 having a second conductivity (p) type arranged so as to be adjacent to the drain region 421 ; an n + source region 43 arranged so as to be adjacent to the channel region 42 ; select gate electrodes 13 a and 15 a arranged above the channel region 42 with the gate insulating film 12 interposed between the channel region 42 and the set of select gate electrodes 13 a and 15 a.
  • the drain region 421 , the channel region 42 and the source region 43 are arranged in the SOI layer 2 .
  • a source line contact 18 is arranged on the source region 43 so that the source line contact 18 is adjacent to the select gate transistor STS 1
  • the select gate transistor STD 1 is an enhancement MIS transistor including: an n + source region 42 ( n+ 1) which is common a drain region 42 ( n+ 1) of the memory cell transistor MT in positioned in another end of the arrangement in the column direction; a channel region 44 having a second conductivity type (p) arranged so as to be adjacent to the source region 42 ( n+ 1); an n + drain region 45 arranged so as to be adjacent to the channel region 44 ; select gate electrodes 13 b and 15 b arranged above the channel region 44 with the gate insulating film 12 interposed between the channel region 44 and the set of select gate electrodes 13 b and 15 b.
  • the source region 42 ( n + ), the channel region 44 and the drain region 45 are arranged in the SOI layer 2 .
  • a bit line contact 17 is arranged on the drain region 45 so that the bit line contact 17 is adjacent to the select gate transistor STDl.
  • a source line SL connected to the source line contact 18 ; a select gate line SGS to which the select gate electrodes 13 a and 15 a of a select gate transistor STS 1 are connected; word lines WL 1 to WLn to which the control gate electrodes 15 of the respective memory cell transistors MT 11 to MT 1n are connected; and a select gate line SGD to which the select gate electrodes 13 b and 15 b of the select gate transistor STD 1 are connected.
  • Bit lines BL 1 and BL 2 connected to the bit line contact 17 are arranged in the row direction.
  • FIG. 3 is a cross-sectional view of the non-volatile semiconductor memory taken along the II-II line in the row direction shown in FIG. 2 .
  • an element isolation insulating film 6 is embedded between the floating gate electrode 13 and the channel region 411 of each of the memory cell transistors MT 11 and MT 21 which are adjacent to one another in the row direction. Elements of the respective memory cell transistors MT 11 and MT 21 , which are adjacent to one another in the row direction, are completely isolated from one another.
  • a peripheral circuit of a cell array arranged on a semiconductor substrate is further provided in the outside of the cell array comprised of a plurality of memory cell transistors.
  • FIG. 4 An equivalent circuit of the non-volatile semiconductor memory according to the embodiment shown in FIGS. 1 to 3 is shown in FIG. 4 .
  • a cell array 100 comprises m ⁇ n (m and n are integers) memory cell transistors MT 11 to MT 1n , MT 21 to MT 2n , . . . , MT mn to MT mn which are depletion mode MIS transistors.
  • a plurality of memory cell transistors MT 11 to MT 11 are arranged as a group in a column; a plurality of memory cell transistors MT 21 to MT 2n are arranged as a group in another column; . . .
  • a plurality of memory cell transistors MT m1 to MT mn are arranged as a group in the other column.
  • the group of memory cell transistors MT 11 to MT 1n , the group of memory cell transistors MT 21 to MT 2n , and the group of memory cell transistors MT m1 to MT mn are arranged in the row direction. In this way, the plurality of memory cell transistors MT 11 to MT 1n , MT 21 to MT 2n , . . . , MT m1 to MT mn are arranged in a matrix.
  • the memory cell transistors MT 11 to MT 1 n, the select gate transistors STS 1 and STD 1 are connected in series, thereby comprising a cell unit.
  • the drain region of the enhancement mode select gate transistor STS 1 which selects one out of the memory cell transistors MT 11 to MT 1n is connected to the source region of the memory cell transistor MT 11 positioned at one end of the arrangement in which the group of memory cell transistors MT 11 to MT 1n are connected in series.
  • the source region of the enhancement selective gate transistor STD 1 which selects one out of the memory cell transistors MT 11 to MT 1n is connected to the drain region of the memory cell transistor MT 1n positioned at the other end of the arrangement in which the group of memory cell transistors MT 11 to MT 1n are connected in series.
  • the source regions of the respective select gate transistors STS 1 to STSm are connected with a source line SL common the source regions.
  • a source line driver 103 which supplies voltage to the source line SL is connected to the source line SL.
  • the following are connected to a row decoder 101 : a select gate line SGS common the select gate transistors STS 1 to STSm; a select gate line SGD common the select gate transistors STD 1 to STDm; a word line WL 1 common the memory cell transistors MT 11 , MT 21 , . . . , MT m1 ; a word line WL 2 common the memory cell transistors MT 12 , MT 22 , . . . , MT m2 ; . .
  • the row decoder 101 obtains a row address decoded signal by decoding a row address signal, and supplies operation voltage to the word lines WL 1 to WLm and the select gate lines SGS and SGD in a selective manner.
  • Each of bit lines BL 1 to BLm is connected to the drain region of each of the select gate transistors STD 1 to STDm.
  • a sense amplifier 102 and a column decoder 104 are connected to the bit lines BL 1 to BLm.
  • the column decoder 104 obtains a column address decoded signal by decoding a column address signal, and selects one out of the bit lines BL 1 to BLm based on the column address decoded signal.
  • the sense amplifier 102 amplifies data which has been read from a memory cell transistor selected by the row decoder 101 and the column decoder 104 .
  • a threshold voltage of the memory cell transistor MT 11 is a negative threshold voltage Ve as shown in FIG. 5 , since the memory cell transistor MT 11 is a depletion mode memory cell transistor.
  • a description will be provided for an example of a writing operation with reference to FIGS. 6 and 7 .
  • it is assumed that the memory cell transistor MT 11 is selected during its writing and reading operations.
  • the memory cell transistor MT 11 which has been selected is referred to as a “selected memory cell transistor,” and the memory cell transistors MT 12 to MT 1n , MT 21 to MT 2n , . . . , and MT m1 to MT mn which have not been selected are referred to as “non-selected memory cell transistors.”
  • the bit line BL 1 and the word line WL 1 connected to the selected memory cell transistor MT 11 are referred to as a “selected bit line” and a “selected word line” respectively.
  • the bit lines BL 2 to BLm and the word lines WL 2 to WLn connected only to the non-selected memory cell transistors MT 21 to MT 2 n, . . . , MTm 1 and MTmn are referred to as “non-selected bit lines” and “non-selected word lines.”
  • a voltage of 0 V and a power supply voltage Vcc are applied to the selected bit line BL 1 and the source line SL respectively.
  • a voltage of 0 V is applied to the select gate line SGS, thus causing the select gate transistor STS 1 to be in the “off” state, thus causing the source line SL to be in the “cut-off” state.
  • the power supply voltage Vcc (for example, 3 V) is applied to the select gate line SGD, and the select gate transistor STD 1 is caused to be in the “on” state, accordingly causing 0 V in the selected bit line BL 1 to be transmitted to the selected memory cell transistor MT 1n .
  • a write voltage V pgm (for example, 20 V) is applied to the selected word line WL 1 .
  • An intermediate potential V pass1 (for example, 10 V) is applied to each of the non-selected word lines WL 2 to WLm.
  • the selected memory cell transistor MT 11 and the non-selected memory cell transistors MT 12 to MT 11 are all caused to be in the “on” state, thus causing 0 V in the selected bit line BL 1 to be transmitted.
  • the write voltage V pgm (for example, 20 V) is applied to the control gate electrode 15 shown in FIG. 1 , and a high electric field is applied between the channel region 411 underneath the floating gate electrode 13 to which 0 V is transmitted from the selected bit line BL 1 and the floating gate electrode 13 , thus injecting electrons into the floating gate electrode 13 through the gate insulating film 12 .
  • a threshold voltage of the selected memory cell transistor MT 11 increases by ⁇ V from the negative threshold voltage Ve to a positive threshold voltage Vp, and accordingly the selected memory cell transistor MT 11 is in the “write” state (data is 0).
  • the power supply voltage Vcc (for instance, 3 V) is applied to each of the non-selected bit lines BL 2 to BLm.
  • a voltage of 0 V is applied to the select gate line SGS, and thus each of the select gate transistors STS 2 to STSm is in the “off” state, accordingly causing the source line SL to be in the “cut-off” state.
  • the power supply voltage Vcc (for example, 3 V) is applied to the select gate line SGD, thus causing each of the selected gate transistors STD 2 to STDm to be in the “on” state.
  • the select gate transistors SGD 2 to SGDm and the select gate transistors SGS 2 to SGSm are cut off, the channel regions underneath the respective non-selected memory cell transistors MT 21 to MT 2n , . . . , MT m1 to MT mn are in the “on” state, and the channel regions from the source line SL and the bit lines BL 2 to BLm are in the “floating” state. Potentials of channel regions which have been in the “floating” state are increased (larger than, or equal to, Vcc and smaller than, equal to, Vpass, for example 7 to 8 V) by the coupling of the potentials Vpgm and Vpass.
  • An erase voltage Vera (for example, 20 V) is applied to all the bit lines BL 1 to BLm and the source line SL, respectively.
  • An initial voltage Vsgd (for example, 4 V) is applied to the select gate line SGD, so that the select gate transistor STD 1 is in the “on” state. Accordingly, the erase voltage Vera (for example, 20 V) in the bit line BL 1 to BLm is transmitted to the memory cell transistors MT 1n , MT 2n , . . . , MT mn .
  • An initial voltage Vsgs (for example, 4 V) is applied to the select gate line SGS, so that the select gate transistor STS 1 is in an “on” state. Accordingly, the erase voltage Vera (for example, 20 V) in the source line SL is transmitted to the memory cell transistors MT 11 , MT 21 , . . . , MT m1 .
  • a voltage of 0 V is applied to all the word lines WL 1 to WLn. Since the memory cell transistors MT 11 to MT 1n , MT 21 to MT 2n , . . . , MT m1 to MT mn are depletion mode memory cell transistors, the memory cell transistors MT 11 to MT 1n , MT 21 to MT 2n , . . . , MT m1 to MT mn are in the “on” state if 0 V is applied to the control gate electrodes 15 .
  • the erase voltage Vera for example, 20 V
  • the threshold voltage of the selected memory cell transistor MT 11 is decreased by ⁇ V from a positive threshold voltage Vp to a negative threshold voltage Ve as shown in FIG. 5 .
  • the selected memory cell transistor MT 11 will in the “erase” state (date is 1). Consequently, data are erased simultaneously from the memory cell transistors MT 11 to MT 1n , MT 21 to MT 2n , . . . , MT m1 to MT mn .
  • a pre-charged voltage V b1 (for example, 1 V) is applied to each of the bit lines BL 1 to BLm, and 0 V is applied to the source line SL.
  • the power supply voltage Vcc (for example, 3 V) is applied to the select gate line SGS, so that the select gate transistor STS 1 is in the “on” state Accordingly, 0 V in the source line SL is transmitted to the memory cell transistors MT 1n , MT 21 , . . . , MT m1 .
  • the power supply voltage Vcc (for example, 3 V) is applied to the select gate line SGD, so that the select gate transistor STD 1 is in the “on” state. Accordingly, the pre-charged voltage V b1 (for example, 1 V) in the bit lines BL 1 to BLm is transmitted to the memory cell transistors MT 1n , MT 2n , . . . , MT mn .
  • a voltage V read (for example, 4.5 V), which is higher than the power supply voltage Vcc, is applied to the non-selected word lines WL 2 to WLm, so that the non-selected memory cell transistors MT 12 to MT 1n , MT 21 to MT 2n , and MT m1 to MT mn are in the “on” state. Accordingly, the non-selected memory cell transistors MT 12 to MT 1n , MT 21 to MT 2n , and MT m1 to MT mn serve as transfer transistors.
  • a voltage of 0 V is applied to the selected word line WL 1 . In the memory cell transistor MT 11 , 0 V is applied to the control gate electrode 15 as shown in FIGS.
  • the threshold voltage Ve of the selected memory cell transistor MT 11 is less than 0 V as shown in FIG. 5 . For this reason, even if the voltage applied to the control gate electrode 15 is 0 V, the selected memory cell transistor MT 11 is in the “on” state, and accordingly channel current flows. On the other hand, when electrons have accumulated in the floating gate electrode 13 as shown in FIG. 11 , the threshold voltage Vp of the selected memory cell transistor MT 11 is higher than 0 V as shown in FIG. 5 . A depletion layer A of the channel region 411 underneath the floating gate electrode 13 spreads as shown in FIG. 11 .
  • the memory cell transistor MT 11 is in the “off” state.
  • the channel current does not flow. If the channel current flows into the selected memory cell transistor MT 11 , it is judged on determined that the selected memory cell transistor MT 11 is in the “erase” state (data is “1”). If the channel current does not flow into the selected memory cell transistor MT 11 , it is judged on determined that the selected memory cell transistor MT 11 is in the “write” state (data is “0”).
  • FIG. 41 shows a comparative example of enhancement memory cell transistors MT 111 to MT 11n .
  • Each of the memory cell transistors MT 111 to MT 11 n includes an n + -source and drain region 104 which are provided on a p-semiconductor substrate 111 , and a floating gate electrode 113 and a control gate electrode 115 which are provided above a channel region between the source and drain regions 104 .
  • the width W of the channel region between the source and drain regions 104 has become so narrow that the influence of the short channel effect has increased.
  • the channel region is depleted in a state whrere electrons have been accumulated in the floating gate electrode 13 , thereby enabling the short channel effect to be reduced.
  • the memory cell transistors MT 11 to MT 1n are depletion mode transistors having the source and drain regions 421 to 42 ( n+ 1) and the channel regions 411 to 41 n.
  • the SOI layer 2 may have a thickness of approximately 30 nm to 40 nm, and it is more preferable that the SOI layer 2 may have a thickness of approximately 30 nm to 35 nm.
  • influence of a capacitance C ch-sub between the channel region 104 and the semiconductor substrate 111 is large as shown in FIG. 42 .
  • the capacitance of the SOI layer 2 can be reduced because of the SOI structure in which the SOI layer 2 is formed on the SOI insulator 1 as shown in FIG. 1 .
  • the memory cell transistors MT 111 and MT 121 of the comparative case are isolated from one another in the row direction by element isolation regions (STI) 106 , respectively, as shown in FIG. 42 , and a parasitic capacitance C sti is generated between the element isolation regions (STI) 106 .
  • the memory cell transistors MT 11 and MT 21 in the row direction are completely isolated from each other by the element isolation insulating film 6 as shown in FIG. 3 . Consequently, parasitic capacitance C sti influence between the element isolation regions (STI) 106 shown in FIG. 42 can be reduced. Accordingly, punch-through immunity, field inversion breakdown voltage and the like do not have to be considered. For this reason, the widths Ws of the respective element isolation insulating films 6 in the row direction shown in FIG. 3 can be set at a minimum width for allowing lithographic and etching techniques.
  • the peripheral circuit (MOS transistor), which is not illustrated, for driving the memory cell transistors MT 11 to MT 1n , MT 21 to MT 2n , . . . , MTm 1 to MTmn can also be formed on the SOI layer 2 provided in the SOI insulator 1 .
  • MOS transistor MOS transistor
  • a p-type impurity diffusion layer and an n-type impurity diffusion layer may be used, in common with the select gate transistor.
  • an n-type impurity diffusion layer and a p-type impurity diffusion layer may be used.
  • FIGS. 12A, 13A , and 23 A show a fabrication cross-sectional process flow of the cell array 100 shown in FIG. 2 in the column direction taken along the III-III line.
  • FIGS. 12B, 13B , . . . , and 23 B show a fabrication cross-sectional process flow of the cell array 100 in the row direction taken along the II-II line.
  • the SOI layer 2 having a first conductivity type provided on the SOI insulator 1 is prepared.
  • the SIMOX technique oxygen ions (O + ) are implanted into a silicon (Si) substrate, which is not illustrated, and then the silicon substrate is thermally treated.
  • the SOI insulator 1 is formed in the Si substrate, and the SOI layer 2 is formed on the SOI insulator 1 .
  • the wafer bonding technique the SOI insulator 1 is formed on one of the two wafers. Then, the two wafers are bonded, and are thermally treated. Subsequently, one of the two wafers is made into a thin film through planarization, thereby forming the SOI layer 2 .
  • a resist film is coated on the SOI layer 2 , and the resist film is patterned by the lithographic technique.
  • ions having p-type impurity such as boron ( 11 B + ) are implanted with the patterned resist film 21 used as a mask. Residual resist film 21 is removed by use of resist remover or the like.
  • a resist film is coated on the SOI layer 2 , and then the resist film is patterned with the lithographic technique. Subsequently, as shown in FIGS.
  • ions having n-type impurity such as phosphorus ( 31 P + ) and arsenic ( 75 As + ), are implanted with the patterned resist film 22 used as a mask.
  • a resist film is also coated on the region surrounding the cell array 100 , where the peripheral circuit is to be formed, and the coated resist film is patterned. Then, if necessary, ions are implanted.
  • a gate insulating film (tunnel oxidation film) 12 such as a SiO 2 film is formed by use of the thermal oxidation method so that the thickness of the gate insulating film is approximately 1 nm to 15 nm.
  • a p-doped first polysilicon layer (floating gate electrode) 13 x which is going to be a floating gate electrode, is deposited on the gate insulating film 12 by reduced pressurized CVD so that the thickness of the first polysilicon layer may be 10 nm to 200 nm.
  • a mask material 5 such as a Si 3 N 4 film is deposited on the first polysilicon layer 13 x by CVD so that the thickness of the mask material may be approximately 50 nm to 200 nm.
  • a resist film is spin-coated on the mask material 5 , and an etching mask of the resist film is formed by the lithographic technique. Parts of the mask material 5 are removed in a selective manner by the reactive ion etching (RIE) in which an etching mask is used. After etching, the resist film is removed. With the mask material 5 used as a mask, parts of the first polysilicon layer 13 x, the gate insulating film 12 and the SOI layer 2 are removed in the column direction in a selective manner until the SOI insulating layer 1 underneath the parts is exposed. As a result, groove portions 7 are formed which penetrate through the first polysilicon layer 13 x, the gate insulating film 12 and the SOI layer 2 , as shown in FIGS. 16A and 16B . Although FIG. 16B shows that parts of the SOI insulating layer 1 are removed, the SOI insulating layer 1 may remain planar.
  • RIE reactive ion etching
  • an element isolation insulating film 6 is embedded in the groove portions 7 shown in FIG. 16B by CVD or the like so that the thickness of the element isolation insulating film 6 is approximately 200 nm to 1,500 nm.
  • the element isolation insulating film 6 is etched back by use of chemical-mechanical polishing (CMP) so that the element isolation insulating film 6 may be planarized.
  • CMP chemical-mechanical polishing
  • the upper surfaces of the element isolation insulating films 6 are situated in positions higher than the upper surfaces of the gate insulating films 12 . As a result, the elements of the memory cell transistors MT 11 to MT 21 in the row direction are completely isolated from one another.
  • an inter-electrode insulating film 14 is deposited on the tops of the first polysilicn layers 13 x and the tops of the element isolation insulating films 6 by CVD or the like.
  • a resist film 23 is coated on the inter-electrode insulating film 14 , and the resist film 23 is patterned by the lithographic technique.
  • opening portions 8 are formed in a part of the inter-electrode insulating film 14 with the patterned resist film 23 used as a mask by RIE or the like. As shown in FIGS.
  • a p-doped second polysilicon layer (control gate electrode) 15 x which will be a control gate electrode, is deposited on the inter-electrode insulating film 14 by CVD so that the thickness of the second polysilicon layer 15 x is approximately 10 nm to 200 nm.
  • a resist film 24 is coated on the second polysilicon layer 15 x, and the resist film 24 is patterned by the lithographic technique. As shown in FIGS. 22A and 22B , parts of the second polysilicon layer 15 x, the inter-electrode insulating layer 14 , and the first polysilicon layer 13 x are removed in the row direction with the patterned resist film 24 used as a mask by RIE in a selective manner until the gate insulating film 12 underneath the parts is exposed. As a result, grooves are formed which penetrate through the second polysislicon layer 15 x, the inter-electrode insulating film 14 and the first polysilicon layer 13 x. The resist film 24 is removed by a resist remover and the like.
  • Ions of 31 P + or 75 As + are implanted through the gate insulating films 12 in a self-aligned manner with the second polysilicon layer 15 x used as a mask. Subsequently, n-type impurity ions of the first polysilicon layers 13 x and the second polysilison layers 15 x are activated by thermal treatment. Thereby, the floating gate electrodes 13 and the control gate electrodes 15 are formed. As shown in FIGS. 23A and 23B , p-type impurity ions and n-type impurity ions in the SOI layer 2 are activated.
  • n + -type impurity diffusion layers (source and drain regions) 421 and 422 are formed in the SOI layer 2 positioned at the bottom of grooves as shown in FIG. 1 , and an n ⁇ -type impurity diffusion layer (channel region) 411 is formed in the SOI layer 2 underneath the first polysilicon layer 13 x. Consequently, the depletion mode memory cell transistor MT 11 is formed.
  • n + -type impurity diffusion layers (source and drain regions) 423 to 42 ( n+ 1) are formed in the SOI layer 2 positioned at the bottom of the grooves as shown in FIG.
  • n ⁇ -type impurity diffusion layers (channel regions) 412 to 41 n are formed in the SOI layer 2 underneath the first polysilicon layer 13 x. Consequently, the memory cell transistors, illustration omitted, are crossed in the column direction and in the row direction and the memory cell transistors are formed in a matrix.
  • the select gate electrodes 13 a and 15 a are formed as shown in FIGS. 23A and 23B .
  • a p-type impurity diffusion layer (channel region) 42 is formed in the SOI layer 2 , and an n + -type impurity diffusion layer (source region) 43 is formed.
  • an enhancement mode select gate transistor STS 1 is formed.
  • the select gate electrodes 13 b and 15 b shown in FIG. 1 are formed, and the p-impurity diffusion layer (channel region) 44 and the n + -type impurity diffusion layer (drain region) 45 are formed.
  • the enhancement mode select gate transistor STD 1 is also formed.
  • predetermined interconnects and insulating films are formed or deposited, thereby completing the non-volatile semiconductor memory shown in FIG. 1 .
  • the non-volatile semiconductor memory shown in FIG. 1 can be provided. Since the element isolation region (STI) 6 as shown in FIG. 1 does not have to be embedded, a minaturized process can be performed with ease. Note that the method for fabricating the non-volatile semiconductor memory shown in FIG. 12A to FIG. 23B is an example. It is possible to provide the non-volatile semiconductor memory by other various methods.
  • STI element isolation region
  • n + -source and drain regions 421 and 422 may be extended to parts of an SOI layer 2 underneath a floating gate electrode 13 as shown in FIG. 24 .
  • the SOI layer 2 underneath the floating gate electrode 13 is comprised of only an n channel region 411 as shown in FIG. 1 , if the voltage in a control gate electrode 15 is 0 V for an erasing operation in a state whrere electrons have accumulated in the floating gate electrode 13 , the erasing operation is retarded due to formation of a depletion layer in the n ⁇ channel region 411 .
  • the n + -source and drain regions 421 and 422 are provided in the SOI layer 2 underneath the floating gate electrode 13 as shown in FIG. 24 , thereby the n + -source and drain regions 421 and 422 are not easily depleted. Accordingly, electrons are easily extracted between the floating gate electrode 13 and each of the n + -source and drain regions 421 and 422 . For this reason, it is possible to speed up the erasing operation.
  • An n channel region 411 is provided in the middle of the SOI layer 2 underneath the floating gate electrode 13 . Because of this, during the reading operation, the n ⁇ channel region 411 underneath the floating gate electrode 13 is depleted as shown in FIG. 25 , accordingly forming a depletion layer A′. Thus, channel current can be fully off.
  • the source and drain regions 421 and 422 may be formed by forming the n channel region 411 in the middle of the SOI layer 2 underneath the floating gate electrode 13 and by diffusing an n-type impurity as far as parts of the SOI layer 2 underneath the floating gate electrode 13 .
  • a method for fabricating a non-volatile semiconductor memory according to a second modification only p-type impurity ions are implanted in the entire surface of an SOI layer 2 , instead of implanting p-type impurity ions and n-type impurity ions into the SOI layer 2 in a selective manner as shown in FIGS. 13A to 14 B. Subsequently, a series of steps shown in FIGS. 15A to 22 B are performed in substantially the same manner.
  • n-type impurity ions are implanted in a self-aligned manner with a second polysilicon layer 15 x used as a mask, and a thermal treatment is performed.
  • n-type impurity ions in the SOI layer 2 are activated, and hence n + -source and drain regions 421 and 422 as well as a source region 43 are formed as shown in FIG. 27 .
  • the n-type impurity ions diffuse, and an n channel region 411 is formed in the SOI layer 2 underneath a floating gate electrode 13 .
  • n + -source and drain regions 423 to 42 ( n+ 1) as well as n-channel regions 412 to 41 n shown in FIG. 1 are formed.
  • the n-type impurity ions diffuse, and hence each of the source and drain region 421 and the source region 43 is expanded by a length Ln into the SOI layer 2 underneath select gate electrodes 13 a and 15 a.
  • a length Lw 1 of a control gate electrode 15 in a memory cell transistor MT 11 may be shorter than a length 2Ln aggregating the length Ln of the expansion of the source and drain region 421 and the length Ln of the expanded the source region 43 .
  • a length Lsg of each of the select gate electrodes 13 a and 15 a may be set longer than the length 2Ln aggregating the length Ln of the expanded the source and drain region 421 and the length Ln of the expanded the source region 43 .
  • a non-volatile semiconductor memory according to a third modification is different from the non-volatile semiconductor memory shown in FIG. 1 in that a semiconductor substrate 30 is arranged under an SOI insulator 1 x as shown in FIG. 28 .
  • a convex cell array portion 30 x is provided in the semiconductor substrate 30 , and is connected with a source region 43 through a first opening portion 32 provided in the SOI insulator 1 x.
  • a source line contact 18 is arranged over the convex cell array portion 30 x with the source region 43 interposed between the source line contact 18 and the convex cell array portion 30 x.
  • a peripheral circuit (MIS transistor) Tp is arranged in the outer periphery of the cell array.
  • the peripheral circuit Tp is formed by using as an active layer a peripheral convex portion 30 y of the semiconductor substrate 30 in contact with the peripheral circuit, through a second opening portion 33 provided in the SOI insulator 1 x.
  • Impurity diffusion layers 31 a and 31 b are provided in the peripheral convex portion 30 y of the semiconductor substrate 30 .
  • Gate electrodes 13 c and 15 c are arranged over a channel region between the impurity diffusion layers 31 a and 31 b with a gate insulating film 12 interposed between the gate electrode 13 c and the channel region.
  • the peripheral circuit Tp is isolated from an adjacent element, illustration is omitted, by the SOI insulator 1 x. According to the third modification, the peripheral circuit Tp can be arranged, as it is, on the present semiconductor substrate 30 , instead of being formed on the SOI insulator 1 employing the SOI technology.
  • the semiconductor substrate 30 is prepared.
  • a resist film is coated on the semiconductor substrate 30 , and the resist film is patterned by the lithographic technique. With the patterned resist film used as a mask, parts of the semiconductor substrate 30 are removed in a selective manner by RIE or the like. As a result, the convex cell array portion 30 x and the peripheral convex portion 30 y, which are at substantially the same horizontal level, are formed as shown in FIG. 28 .
  • the SOI insulator 1 x is deposited on the semiconductor substrate 30 , as shown in FIG. 32A and FIG. 32B . As shown in 33 A and 33 B, the SOI insulator 1 x is etched back and planarized by CMP and the like, until the convex cell array portion 30 x and the peripheral convex portion 30 y are exposed.
  • the SOI layer 2 is deposited on the SOI insulator 1 x by CVD and the like.
  • the source line contact 18 is formed over the convex cell array portion 30 x of the semiconductor substrate 30 with the SOI layer 2 interposed between the source line contact 18 and the convex cell array portion 30 x.
  • the peripheral circuit Tp is formed in the peripheral convex portion 30 y of the semiconductor substrate 30 .
  • the other steps are substantially the same as the series of steps shown in FIGS. 13A to FIG. 23B . For this reason, a description will be omitted for the common steps.
  • the peripheral circuit Tpx may be arranged in the SOI layer 2 on the semiconductor substrate 30 , as shown in FIG. 35 .
  • An element of the peripheral circuit Tpx is isolated by an element isolation region (STI) 31 from an element, illustration omitted, and which is adjacent the element of the peripheral circuit Tpx.
  • the peripheral circuit Tpx can be provided by selectively removing parts of the SOI layer 2 and by embedding the element isolation region (STI) 31 .
  • a non-volatile semiconductor memory according to a fourth modification of the present invention may have a two-transistor cell structure which is an expansion of a planar pattern structure of a one-transistor cell structure shown in FIG. 2 .
  • the non-volatile semiconductor memory shown in FIG. 36 comprises a cell array 100 x, a column decoder 104 , a sense amplifier 102 , a first row decoder 101 x, a second row decoder 101 y and a source line driver 103 .
  • the cell array 100 x comprises a plurality ((m+1) ⁇ (n+1); m and n are integers) of memory cells MC 00 to MC mn .
  • Each of the memory cells MC includes a memory cell transistor MT and a select transistor ST. In each of the cell transistor and the select transistor a current pathway is connected in series.
  • the memory cell transistor MT comprises a stacked gate structure including: a floating gate electrode formed above a semiconductor substrate with a gate insulating film interposed between the floating gate electrode and the semiconductor substrate; and a control gate electrode formed above the floating gate electrode with an inter-electrode insulating film interposed between the control gate electrode and the floating gate electrode.
  • a source region of the memory cell transistor MT is connected to a drain region of the select transistor ST.
  • Each of two memory cells MC adjacent to each other in the column direction share the source region of the select transistor ST or the drain region of the memory cell transistor MT.
  • the control gate electrodes of the respective memory cell transistors MT of the respective memory cells MC in the same row are commonly connected to one of word lines WL 0 to WLm.
  • the gates of the respective select transistors ST of the respective memory cells in the same row are connected to any one of select gate lines SG 0 to SGm.
  • the drain regions of the respective memory cell transistors MT of the respective memory cells MC in the same row are commonly connected to one of bit lines BL 0 to BLn.
  • the sources of the respective select transistors ST of the respective memory cells MC are commonly connected to a source line SL, and the source line SL is connected to a source line driver 103 .
  • the column decoder 104 decodes a column address signal, thereby obtaining a column address decoded signal.
  • One of the bit lines BL 0 to BLn is selected on a basis of the column address decoded signal.
  • the first and second row decoders 101 x and 101 y decode a row address signal, thereby obtaining a row address decoded signal.
  • the first row decoder 101 x selects one of the word lines WL 0 to WLn when writing is initiated.
  • the second row decoder 101 y selects one of the select gate lines SG 0 to SGm when reading is initiated.
  • the sense amplifier 102 amplifies data which have been read out from a memory cell selected by the second row decoder 101 y and the column decoder 104 .
  • the source line driver 103 supplies voltage to the source line SL during reading.
  • the non-volatile semiconductor memory is designed to comprise the two-transistor cell structure, so that the memory cell MC is positively cut off, and thus enabling a readers operation to be performed.
  • a three-transistor cell structure in which a select transistor ST is connected to both a source region and a drain region for each of the memory cell transistors MT can be easily expanded from the planar pattern shown in FIG. 2 .
  • the flash memory system 142 comprises a host platform 144 and a universal serial bus (USB) flash device 146 .
  • the host platform 144 is connected to the USB flash device 146 through a USB cable 148 .
  • the host platform 144 is connected to the USB cable 148 through a USB host connector 150
  • the USB flash device 146 is connected to the USB cable 148 through a USB flash device connector 152 .
  • the host platform 144 comprises a USB host controller 154 for controlling packet transfer on the USB.
  • the USB flash device 146 includes: a USB flash device controller 156 for controlling other elements in the USB flash device 146 , and for controlling an interface to the USB bus of the USB flash device 146 ; a USB flash device connector 152 ; and at least one flash memory module 158 including a non-volatile semiconductor memory according to an embodiment of the present invention.
  • USB flash device 146 Once the USB flash device 146 is connected to the host platform 144 , a standard USB listing process is started. At this point, the hot platform 114 recognizes the USB flash device 146 , and selects a mode of communications with the USB flash device 146 . Then, the host platform 114 transmits data to, and receives data from, the USB flash device 146 through an FIFO buffer, termed as an endpoint, for storing transmitted data. The host platform 144 recognizes changes in physical, electrical conditions such as disconnection and connection of the USB flash device 146 and the like through the endpoint. In addition, if there is a packet to be received, the host platform 144 receives it.
  • the host platform 144 requests a service from the USB flash device 146 by transmitting a request packet to the USB host controller 154 .
  • the USB host controller 154 transmits a packet on the USB cable 148 . If the USB flash device 146 has an endpoint which receives this request packet, the requests are received by the USB flash device controller 156 .
  • the USB flash device controller 156 performs various operations such as reading data from the flash memory module 158 , writing data to the flash memory module 158 , erasing data and the like. In addition, the USB flash device controller 156 supports basic USB functions such as the acquisition of a USB address and the like.
  • the USB flash device controller 156 controls the flash memory module 158 through a control line 160 for controlling output from the flash memory module 158 , or, for example, through a read/write signal and various other signals such as a chip enable signal and the like.
  • the flash memory module 158 is also connected to the USB flash device controller 156 through an address data bus 162 .
  • the address data bus 12 transfers a read command, a write command and an erase command as well as an address and data in the flash memory module 158 .
  • the USB flash device 146 transmits a state packet by use of a state endpoint (endpoint 0 ). At this point, the host platform 144 checks whether or not there is a state packet, and the SB flash device 146 returns an empty packet or the state packet if there is no new packet of a state message.
  • USB flash device 146 various functions of the USB flash device 146 can be achieved.
  • the connectors may be connected directly.
  • a non-volatile semiconductor memory according to a sixth modification of the present invention is -three-dimensionally integrated by stacking SOI structures.
  • the inter-layer dielectric 3 is disposed on elements such as the memory cell transistors MT 11 to MT 1n , the select gate transistors STD 1 and STS 1 , and the like.
  • the inter-layer dielectric 3 is used for insulation material of an upper layer of the SOI structure.
  • Memory cell transistors MT 111 to MT 11n are depletion mode MIS transistors including: n + source and drain regions 521 to 52 (n+1) which are arranged on the inter-layer dielectric (SOI insulator) 3 , and which are opposite to each other; n channel regions 511 to 51 n, each of which is interposed between each adjacent pair of the source and drain regions 521 to 52 ( n+ 1), and whose impurity concentrations are lower than those of the source and drain regions 521 to 52 ( n+ 1) ; floating gate electrodes 63 which are insulated, and each of which is arranged above each of the channel regions 511 to 51 n; and control gate electrodes 65 which are insulated, each of which is arranged above each of the floating gate electrodes 63 .
  • Each of two select gate transistors STS 11 and STD 11 is arranged in, and adjacent to, each end of the column direction of the memory cell transistors MT 111 to MT 11n .
  • the select gate transistor STS 11 is an enhancement MIS transistor including: an n + drain region 521 which is a region common a source region 521 of the memory cell transistor MT 111 positioned at one end of the arrangement in the column direction; p channel region 52 arranged so as to be adjacent to the drain region 521 ; an n source region 53 arranged so as to be adjacent to the channel region 52 ; select gate electrodes 63 a and 65 a arranged above the channel region 52 with the gate insulating film 62 interposed between the channel region 52 and the set of select gate electrodes 63 a and 65 a.
  • the select gate transistor STD 11 is an enhancement MIS transistor including: an n + source region 52 ( n+ 1) which is common a drain region 52 ( n+ 1) of the memory cell transistor MT 11n positioned at another end of the arrangement in the column direction; a p channel region 54 arranged so as to be adjacent to the source region 52 ( n+ 1) ; an n + drain region 55 arranged so as to be adjacent to the channel region 54 ; select gate electrodes 63 b and 65 b arranged above the channel region 54 with the gate insulating film 62 interposed between the channel region 54 and the set of select gate electrodes 63 b and 65 b.
  • a bit line contact 171 is arranged on the drain region 55 so that the bit line contact 171 is adjacent to the select gate transistor STD 11 .
  • a source line contact 181 is arranged on the source region 53 so that the source line contact 181 is adjacent to the select gate transistor STS 11 .
  • the bit line contact 171 and the source line contact 181 are insulated at the periphery by the inter-layer dielectric 3 , the insulating film 7 on the inter-layer dielectric 3 , and the inter-layer dielectric 4 on the insulating film 7 .
  • the word line contacts 91 and 92 which are different from each other, are disposed in upper and lower layers, respectively.
  • the element isolation region 8 isolates the memory cell transistors MT 111 and MT 121 .
  • An element insulation region 4 is disposed on elements such as the memory cell transistors MT 111 to MT 11n and the select gate transistors STS 11 and STD 11 , and the like.
  • the bit line contact 17 and the source line contact 18 may be commonly disposed from the lower layer to the upper layer.
  • the word line contacts 91 and 92 are disposed in the upper layer and lower layer, respectively.
  • the memory cell transistors MT 111 to MT 11n are described as depletion transistors, however the memory cell transistors MT 111 to MT 11n may be enhancement transistors.
  • the structure is described in which two layers of SOI structures are stacked, SOI structure having a plurality of layers, which may be more than three layers, may be provided.
  • the inter-layer dielectric 3 is formed by CVD or the like in order to cover the memory cell transistors MT 11 to MT 1n and the select gate transistors STD 1 and STS 1 . Thereafter, the same procedure as other modifications may be used for forming the memory cell transistors MT 11 to MT 1n and the select gate transistors STD 1 and STS 1 , the memory cell transistors MT 111 to MT 11n and the select gate transistors STD 11 and STS 11 on the inter-layer dielectric 3 .
  • m ⁇ n memory cell transistors MT 11 to MT 1n , MT 21 to MT 2n , . . . , MT m1 to MT mn are explained.
  • a cell array may be comprised by more plurality of memory cell transistors, memory cells and blocks.
  • a biary NAND EEPROM is described.
  • a multi-level storage for example, three-level or more storage in the NAND EEPROM.
  • Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.

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