US11824014B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US11824014B2
US11824014B2 US17/155,016 US202117155016A US11824014B2 US 11824014 B2 US11824014 B2 US 11824014B2 US 202117155016 A US202117155016 A US 202117155016A US 11824014 B2 US11824014 B2 US 11824014B2
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layer
buffer layer
semiconductor device
semiconductor
plan
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US20210305174A1 (en
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Akito Nishii
Tatsuo Harada
Katsumi Uryu
Noritsugu NOMURA
Sho Tanaka
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Assigned to MITSUBISHI ELECTRIC CORPORATION reassignment MITSUBISHI ELECTRIC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HARADA, TATSUO, NISHII, AKITO, NOMURA, NORITSUGU, TANAKA, SHO, URYU, Katsumi
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    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/38—Effects and problems related to the device integration
    • H01L2924/386—Wire effects

Definitions

  • the present disclosure relates to semiconductor devices.
  • a semiconductor layer can be damaged when external wiring used for connection to an external circuit is joined to an electrode.
  • Damage of the semiconductor layer causes a problem of a diode, for example, as described below.
  • the performance required for the diode is that in reducing a loss at recovery.
  • various methods for reducing the loss at recovery including a method of reducing impurity concentration of an anode layer, a method of reducing the thickness of the semiconductor layer, and a method of reducing a life time of carriers in the semiconductor layer. From among these methods, the method of reducing the impurity concentration of the anode layer is a method of reducing the density of the carriers in the semiconductor layer in an on state to reduce a recovery current at switching to thereby reduce the loss.
  • a breakdown voltage is held by a depletion layer spreading in the semiconductor layer from a PN junction in a breakdown voltage held state or in a reverse bias application state as in recovery operation.
  • the depletion layer spreads mainly toward a drift layer, but is also likely to spread toward the anode layer when the anode layer has a lower impurity concentration to reduce the loss at recovery. The breakdown voltage is thus reduced when the anode layer is thin.
  • An effective thickness of the anode layer can locally be reduced by damage, such as a scratch, a dent, and further a crack, of the anode layer.
  • the concentration and the thickness of the anode layer are usually designed not to cause punch-through due to the spread of the depletion layer to an anode electrode.
  • the depletion layer reaches the anode electrode to cause a problem of reduction in breakdown voltage or breakdown of the device due to the difficulty in holding the breakdown voltage.
  • Japanese Patent Application Laid-Open No. 2014-029975 discloses, as a structure to prevent damage of a semiconductor layer when external wiring is joined to an electrode, a structure in which an insulating layer is disposed immediately below a region where the external wiring is joined to the electrode to separate the region where the external wiring and the electrode are joined to each other and a region where the electrode and the semiconductor layer are in contact with each other in plan view.
  • One cause of the damage of the semiconductor layer is foreign matter on or inside the anode electrode.
  • the foreign matter is present immediately below the region where the external wiring is joined, the foreign matter is pushed into the anode electrode at joining of the external wiring. If the pushed foreign matter reaches the semiconductor layer, the semiconductor layer is damaged.
  • a semiconductor device includes: a first semiconductor layer; a second semiconductor layer disposed on a front surface of the first semiconductor layer, and having a different conductivity type from the first semiconductor layer; a buffer layer disposed on a front surface of the second semiconductor layer, and having at least one opening in plan view; and an electrode disposed over the second semiconductor layer and the buffer layer, and being in contact with the second semiconductor layer through the at least one opening.
  • the buffer layer has a higher Vickers hardness than the electrode.
  • the buffer layer disposed on the front surface of the second semiconductor layer, and having the at least one opening in plan view is included, resistance between the external wiring and the semiconductor layer can be suppressed. Furthermore, since the width w of each of the at least one opening satisfies w ⁇ W th , frequency of the damage of the semiconductor layer caused by the foreign matter at connection of the external wiring can be suppressed.
  • a semiconductor device includes: a first semiconductor layer; a second semiconductor layer disposed on a front surface of the first semiconductor layer, and having a different conductivity type from the first semiconductor layer; a conductive buffer layer disposed at least selectively on a front surface of the second semiconductor layer; and an electrode disposed on a front surface of the buffer layer.
  • the buffer layer has a higher Vickers hardness than the electrode.
  • the buffer layer is conductive, resistance between the external wiring and the semiconductor layer can be suppressed. Furthermore, since the buffer layer has a higher Vickers hardness than the electrode, frequency of the damage of the semiconductor layer caused by the foreign matter at connection of the external wiring can be suppressed.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1;
  • FIG. 2 is a plan view illustrating the shape of a buffer layer of the semiconductor device according to Embodiment 1;
  • FIG. 3 is a cross-sectional view of the semiconductor device according to Embodiment 1;
  • FIG. 4 is a plan view illustrating the shape of a buffer layer of a modification of the semiconductor device according to Embodiment 1;
  • FIG. 5 is a plan view illustrating the shape of a buffer layer of a modification of the semiconductor device according to Embodiment 1;
  • FIG. 6 is a plan view illustrating the shape of a buffer layer of a modification of the semiconductor device according to Embodiment 1;
  • FIG. 7 is a cross-sectional view of a semiconductor device according to Embodiment 2.
  • FIG. 8 is a plan view illustrating the shape of a buffer layer of the semiconductor device according to Embodiment 2.
  • an N-type and a P-type as conductivity types are interchangeable.
  • names dependent on the conductivity types in the embodiments should be read differently, for example, an anode electrode should be read as a cathode electrode, and an anode layer should be read as a cathode layer.
  • FIG. 1 is a cross-sectional view of a semiconductor device 100 according to Embodiment 1.
  • the semiconductor device 100 includes a drift layer 1 as a first semiconductor layer, an anode layer 2 as a second semiconductor layer, an anode electrode 3 as an electrode, and a buffer layer 5 .
  • External wiring 4 illustrated in FIG. 1 is wiring to make electrical connection between the semiconductor device 100 and an outside.
  • the drift layer 1 is an N-type semiconductor layer.
  • the anode layer 2 is a semiconductor layer having a different conductivity type from the drift layer 1 , that is, a P-type.
  • the semiconductor device 100 is, for example, a diode, and is particularly used as a freewheeling diode (FWD) that is one of devices constituting a power module.
  • the semiconductor device 100 is the diode
  • the semiconductor device 100 further includes an N-type cathode layer and a cathode electrode, which are not illustrated in FIG. 1 .
  • the cathode layer is disposed on a back surface of the drift layer 1 opposite a surface on which the anode layer 2 is disposed, and the cathode electrode is disposed on a back surface of the cathode layer.
  • the semiconductor device 100 may not be the diode, and may be a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT), for example.
  • MOSFET metal-oxide-semiconductor field-effect transistor
  • IGBT insulated gate bipolar transistor
  • the semiconductor device 100 may also be a module or a device including the diode, the MOSFET, or the IGBT as a part thereof.
  • the drift layer 1 and the anode layer 2 are silicon semiconductors, for example.
  • the anode layer 2 is disposed on the front surface of the drift layer 1 .
  • the buffer layer 5 is disposed selectively on the front surface of the anode layer 2 , and has a mesh shape in plan view. That is to say, the buffer layer 5 has openings in plan view.
  • a region composed of the openings of the buffer layer 5 and the buffer layer 5 in plan view occupies the entirety of the front surface of the drift layer 1 in plan view as illustrated in FIG. 2 .
  • the influence of variations in location when the external wiring 4 is joined can thereby be suppressed.
  • the anode electrode 3 is disposed on front sides of the anode layer 2 and the buffer layer 5 , and is in contact with the anode layer 2 through the openings of the buffer layer 5 .
  • the buffer layer 5 has a higher Vickers hardness than the anode electrode 3 .
  • As a material for the anode electrode 3 aluminum having a Vickers hardness of 0.44 GPa or copper having a Vickers hardness of 0.80 GPa is used, for example.
  • the buffer layer 5 is an insulator including silicon oxide or silicon nitride, for example, having a higher Vickers hardness than aluminum or copper.
  • the buffer layer 5 has a higher Vickers hardness than the anode electrode 3 , frequency or a degree of a push of foreign matter located inside the anode electrode 3 and adhering to an upper surface of the anode electrode 3 into the semiconductor device 100 beyond the buffer layer 5 , that is, into the anode layer 2 beyond the buffer layer 5 can be suppressed compared with a case without the buffer layer 5 . Frequency of damage of the anode layer 2 can thereby be suppressed.
  • the buffer layer 5 has the mesh shape in plan view, and has the openings in plan view, resistance between the external wiring 4 and the anode layer 2 can be suppressed to reduce the loss at energization even in a case where the buffer layer 5 is the insulator, such as silicon oxide and silicon nitride.
  • s is the thickness of the buffer layer 5
  • t is the thickness of the anode electrode 3 as illustrated in FIG. 3 .
  • the thickness of the anode electrode 3 refers to the distance from an interface between the anode electrode 3 and the anode layer 2 to the front surface of the anode electrode 3 .
  • the condition that w ⁇ W th is obtained from a condition that, in a case where spherical foreign matter 7 having a diameter of t or more is pushed from the anode electrode 3 toward the anode layer 2 when the external wiring 4 is joined, the foreign matter 7 does not reach the anode layer 2 by being stopped by the buffer layer 5 .
  • the buffer layer 5 and the anode layer 2 are assumed not to be deformed. Spherical foreign matter having a diameter of less than t does not reach the anode layer 2 even if it is pushed from the anode electrode 3 toward the anode layer 2 when the external wiring 4 is joined because the thickness of the anode electrode 3 is t.
  • each of the openings of the mesh of the buffer layer 5 satisfies w ⁇ W th as described above, so that frequency or the degree of the push of the foreign matter located inside the anode electrode 3 and adhering to the upper surface of the anode electrode 3 into the semiconductor device 100 beyond the buffer layer 5 , that is, into the anode layer 2 beyond the buffer layer 5 can be suppressed compared with the case without the buffer layer 5 . Frequency of the damage of the anode layer 2 can thereby be suppressed.
  • the anode electrode 3 has a thickness t of 4 ⁇ m and the buffer layer 5 has a thickness s of 1 ⁇ m
  • foreign matter having a diameter of more than 4 ⁇ m can damage the anode layer 2 by being pushed by the external wiring 4 when the foreign matter is assumed to be spherical.
  • the damage of the anode layer 2 caused by such foreign matter can be prevented when the width w of each of the openings of the mesh of the buffer layer 5 satisfies w ⁇ W th ⁇ 3.5 ⁇ m.
  • the semiconductor device 100 includes the buffer layer 5 , and the width w of each of the openings of the buffer layer 5 satisfies w ⁇ W th , so that resistance between the external wiring 4 and the anode layer 2 can be suppressed, and frequency of the damage of the anode layer 2 caused by the foreign matter when the wiring is joined can be suppressed.
  • frequency of the damage of the anode layer 2 frequency of reduction in breakdown voltage and the occurrence of breakdown of the semiconductor device 100 caused by variations in effective depth of the anode layer 2 can be suppressed.
  • resistance between the external wiring 4 and the anode layer 2 can be suppressed, and frequency of the damage of the anode layer 2 caused by the foreign matter can be suppressed not only when the external wiring 4 is joined to the anode electrode 3 but also when the external wiring 4 and the anode electrode 3 are only in contact with each other as in a case where a test terminal is brought into contact.
  • the buffer layer 5 has a higher Vickers hardness than the anode electrode 3 , the buffer layer 5 has at least one opening in plan view, and the width w of each of the at least one opening satisfies w ⁇ W th .
  • resistance between the external wiring 4 and the anode layer 2 can be suppressed, and frequency of the damage of the anode layer 2 caused by the foreign matter can be suppressed.
  • the region composed of the openings of the buffer layer 5 and the buffer layer 5 in plan view occupies the entirety of the front surface of the drift layer 1 in plan view. The influence of variations in location when the external wiring 4 is joined can thereby be suppressed.
  • the buffer layer 5 includes silicon oxide or silicon nitride. A configuration in which the buffer layer 5 has a higher Vickers hardness than the anode electrode 3 can thereby easily be achieved.
  • the shape of the buffer layer 5 in plan view is not limited to the mesh shape described in ⁇ A-1. Configuration>.
  • the buffer layer 5 may have any shape as long as it has at least one opening in plan view, and the width w of each of the at least one opening satisfies w ⁇ W th .
  • the anode electrode 3 is in contact with the anode layer 2 through the at least one opening of the buffer layer 5 . Resistance between the external wiring 4 and the anode layer 2 can be reduced when the buffer layer 5 has the at least one opening, and frequency of the damage caused by the foreign matter can be suppressed when the width w of each of the at least one opening satisfies w ⁇ W th .
  • FIGS. 4 to 6 illustrate modifications of the semiconductor device 100 each including the buffer layer 5 having a different shape in plan view.
  • FIG. 4 illustrates an example in which the buffer layer 5 has the mesh shape, but the region composed of the openings of the buffer layer 5 and the buffer layer 5 occupies only a partial region of the front surface of the anode layer 2 .
  • the buffer layer 5 is disposed so that the region composed of the openings of the buffer layer 5 and the buffer layer 5 occupies only the partial region of the front surface of the anode layer 2 .
  • the buffer layer 5 is disposed so that the region composed of the openings of the buffer layer 5 and the buffer layer 5 includes an external wiring connection region 8 where the external wiring 4 is connected.
  • the region composed of the openings of the buffer layer 5 and the buffer layer 5 occupies only the partial region of the front surface of the anode layer 2 , a region where the buffer layer 5 is not disposed in plan view can be increased to further suppress resistance between the external wiring 4 and the anode layer 2 .
  • Each of the openings of the mesh of the buffer layer 5 may not have a rectangular shape as illustrated in FIGS. 2 and 4 , and may have any shape contained within a rectangle that is W th in length on each side in plan view. Each of the openings has such a shape, so that resistance between the external wiring 4 and the anode layer 2 can be suppressed, and frequency of the damage of the anode layer 2 caused by the foreign matter can be suppressed.
  • the buffer layer 5 may not have the mesh shape, and may be shaped so that each of the openings of the buffer layer 5 has a linear shape having a width w of less than W th .
  • FIGS. 5 and 6 illustrate examples in each of which each of the openings of the buffer layer 5 has the linear shape having the width w of less than W th .
  • FIG. 5 illustrates an example in which the buffer layer 5 has a striped shape in plan view.
  • FIG. 6 illustrates an example in which the buffer layer 5 has a concentric annular shape in plan view.
  • the buffer layer 5 may have a shape other than the shapes illustrated in FIGS. 5 and 6 , such as a spiral shape, in plan view.
  • each of the at least one opening of the buffer layer 5 has the linear shape having the width of less than W th , resistance between the external wiring 4 and the anode layer 2 can be suppressed, and frequency of the damage of the anode layer 2 caused by the foreign matter can be suppressed.
  • a semiconductor device 101 according to the present embodiment includes a buffer layer 6 in place of the buffer layer 5 of the semiconductor device 100 according to Embodiment 1.
  • the buffer layer 6 is made of a different material from the buffer layer 5 .
  • the buffer layer 6 may have a different shape from the buffer layer 5 , and, with the difference, the semiconductor device 101 may differ from the semiconductor device 100 in how the anode electrode 3 and the anode layer 2 are in contact with each other or whether the anode electrode 3 and the anode layer 2 are in contact with each other.
  • the semiconductor device 101 is otherwise the same as the semiconductor device 100 .
  • the buffer layer 6 has a higher Vickers hardness than the anode electrode 3 and the external wiring 4 .
  • frequency at which the foreign matter located inside the anode electrode 3 and adhering to the upper surface of the anode electrode 3 reaches the anode layer 2 when the external wiring 4 is joined can be suppressed, and frequency of the damage of the anode layer 2 caused by the foreign matter can be suppressed.
  • the buffer layer 6 is a conductor. Since the buffer layer 6 is the conductor, resistance between the external wiring 4 and the anode layer 2 can be suppressed even when the buffer layer 6 is provided.
  • the buffer layer 6 includes any of titanium, tungsten, molybdenum, and hafnium, for example. Titanium, tungsten, molybdenum, and hafnium have a higher Vickers hardness than aluminum and copper used for the anode electrode 3 and the external wiring 4 . Titanium, tungsten, molybdenum, and hafnium are conductive materials commonly used in a semiconductor manufacturing process, and process control of them is easy.
  • the buffer layer 6 is disposed at least selectively on the front surface of the anode layer 2 .
  • the buffer layer 6 may have the same shape as any of the buffer layer 5 according to Embodiment 1 and the buffer layer 5 according to the modifications of Embodiment 1, for example.
  • the buffer layer 6 may have a shape not having any openings in plan view.
  • the buffer layer 6 having the shape not having any openings in plan view may be disposed selectively on the anode layer 2 as illustrated in FIGS. 7 and 8 , for example, or may be disposed on the entirety of the anode layer 2 .
  • the buffer layer 6 is disposed selectively on the anode layer 2 , the buffer layer 6 is disposed in a region including the external wiring connection region 8 where the external wiring 4 is joined to the anode electrode 3 in plan view as illustrated in FIG. 8 .
  • the semiconductor device 101 includes the conductive buffer layer 6 disposed at least selectively on the front surface of the anode layer 2 and having a higher Vickers hardness than the anode electrode 3 .
  • resistance between the external wiring 4 and the anode layer 2 can be suppressed, and frequency of the damage of the anode layer 2 caused by the foreign matter can be suppressed.
  • the buffer layer 6 includes any of titanium, tungsten, molybdenum, and hafnium. Titanium, tungsten, molybdenum, and hafnium are the conductive materials commonly used in the semiconductor manufacturing process, and process control of them is easy.
  • the embodiments can freely be combined with each other, and can be modified or omitted as appropriate.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
US17/155,016 2020-03-30 2021-01-21 Semiconductor device Active 2041-02-25 US11824014B2 (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61131856U (ja) 1985-02-01 1986-08-18
JPH10335679A (ja) 1997-06-02 1998-12-18 Fuji Electric Co Ltd ダイオードとその製造方法
JP2002319685A (ja) 2001-04-20 2002-10-31 Fuji Electric Co Ltd 半導体装置およびその製造方法
JP2003188391A (ja) 2001-12-21 2003-07-04 Sanken Electric Co Ltd 半導体素子及びその製造方法
US20040009638A1 (en) * 2002-06-19 2004-01-15 Kabushiki Kaisha Toshiba Semiconductor device
JP2007103656A (ja) 2005-10-04 2007-04-19 Denso Corp 半導体装置およびその製造方法
JP2014029975A (ja) 2011-10-17 2014-02-13 Rohm Co Ltd チップダイオードおよびダイオードパッケージ
US20150333270A1 (en) * 2009-09-07 2015-11-19 Semiconductor Energy Laboratory Co., Ltd. Light-Emitting Element, Light-Emitting Device, Lighting Device, and Electronic Device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63199459A (ja) * 1987-02-16 1988-08-17 Hitachi Ltd 半導体装置
JP2000332265A (ja) 1999-05-21 2000-11-30 Sansha Electric Mfg Co Ltd ダイオードとその製造方法
JP2008251925A (ja) 2007-03-30 2008-10-16 Sanyo Electric Co Ltd ダイオード
JP2009212374A (ja) 2008-03-05 2009-09-17 Kansai Electric Power Co Inc:The 半導体装置の製造方法および半導体装置
JP2010129585A (ja) 2008-11-25 2010-06-10 Toyota Motor Corp 半導体装置の製造方法
JP5472862B2 (ja) 2009-03-17 2014-04-16 三菱電機株式会社 電力用半導体装置の製造方法
JP2011071281A (ja) 2009-09-25 2011-04-07 Toyota Central R&D Labs Inc 半導体装置とその製造方法
JP5671867B2 (ja) 2010-08-04 2015-02-18 富士電機株式会社 半導体装置およびその製造方法
JP6111572B2 (ja) 2012-09-12 2017-04-12 富士電機株式会社 半導体装置および半導体装置の製造方法
JP2014187192A (ja) 2013-03-22 2014-10-02 Toshiba Corp 半導体装置
WO2017187477A1 (ja) * 2016-04-25 2017-11-02 三菱電機株式会社 半導体装置
DE112017002530B4 (de) * 2016-05-18 2022-08-18 Mitsubishi Electric Corporation Halbleitereinheit und verfahren zur herstellung derselben

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61131856U (ja) 1985-02-01 1986-08-18
US20050179105A1 (en) 1997-06-02 2005-08-18 Fuji Electric Holdings Co., Ltd. Diode and method for manufacturing the same
US20050151219A1 (en) 1997-06-02 2005-07-14 Fuji Electric Holdings Co., Ltd. Diode and method for manufacturing the same
US20010035560A1 (en) 1997-06-02 2001-11-01 Fuji Electric Co., Ltd. Diode and method for manufacturing the same
US20060244006A1 (en) 1997-06-02 2006-11-02 Fuji Electric Holdings Co., Ltd. Diode and method for manufacturing the same
US20030030120A1 (en) 1997-06-02 2003-02-13 Fuji Electric Co., Ltd. Diode and method for manufacturing the same
JPH10335679A (ja) 1997-06-02 1998-12-18 Fuji Electric Co Ltd ダイオードとその製造方法
US20010017393A1 (en) 1997-06-02 2001-08-30 Fuji Electric Co., Ltd Diode and method for manufacturing the same
JP2002319685A (ja) 2001-04-20 2002-10-31 Fuji Electric Co Ltd 半導体装置およびその製造方法
JP2003188391A (ja) 2001-12-21 2003-07-04 Sanken Electric Co Ltd 半導体素子及びその製造方法
US20040009638A1 (en) * 2002-06-19 2004-01-15 Kabushiki Kaisha Toshiba Semiconductor device
JP2007103656A (ja) 2005-10-04 2007-04-19 Denso Corp 半導体装置およびその製造方法
US20150333270A1 (en) * 2009-09-07 2015-11-19 Semiconductor Energy Laboratory Co., Ltd. Light-Emitting Element, Light-Emitting Device, Lighting Device, and Electronic Device
JP2014029975A (ja) 2011-10-17 2014-02-13 Rohm Co Ltd チップダイオードおよびダイオードパッケージ
US20140284754A1 (en) 2011-10-17 2014-09-25 Rohm Co., Ltd. Chip diode and diode package

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
An Office Action; "Notice of Reasons for Refusal," mailed by the Japanese Patent Office dated Jul. 4, 2023, which corresponds to Japanese Patent Application No. 2020-059505 and is related to U.S. Appl. No. 17/155,016; with English language translation.

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