US11393847B2 - Semiconductor storage apparatus, product-sum calculation apparatus, and electronic equipment - Google Patents

Semiconductor storage apparatus, product-sum calculation apparatus, and electronic equipment Download PDF

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US11393847B2
US11393847B2 US17/040,685 US201917040685A US11393847B2 US 11393847 B2 US11393847 B2 US 11393847B2 US 201917040685 A US201917040685 A US 201917040685A US 11393847 B2 US11393847 B2 US 11393847B2
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transistor
gate electrode
storage apparatus
semiconductor storage
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Masanori Tsukamoto
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Sony Semiconductor Solutions Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/223—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using MOS with ferroelectric gate insulating film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
    • H01L27/1159—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H01L27/11587—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/10—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B51/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors
    • H10B51/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods

Definitions

  • the present disclosure relates to a semiconductor storage apparatus, a product-sum calculation apparatus, and electronic equipment.
  • CMOS complementary MOS
  • nMOSFET n-type metal-oxide-semiconductor field-effect transistor
  • pMOSFET p-type MOSFET
  • CMOS circuit is used in many large scale integration (LSI) devices.
  • LSI large scale integration
  • SoC system on a chip
  • a static random access memory or the like is used as a memory mounted on an LSI.
  • a dynamic RAM DRAM
  • MRAM magnetic RAM
  • FeRAM ferroelectric RAM
  • the FeRAM is a semiconductor storage apparatus that stores information using the direction of remanent polarization of a ferroelectric.
  • a structure of the FeRAM for example, there has been proposed a 1 transistor (1T) type structure using a field effect transistor using a ferroelectric material for a gate insulating film as a memory cell.
  • Patent Document 1 discloses a ferroelectric memory that enables a voltage to be applied only to a memory cell in which information is written by connecting a selection transistor to the gate of a ferroelectric transistor.
  • the present disclosure proposes a new and improved semiconductor storage apparatus, product-sum calculation apparatus, and electronic equipment capable of reducing the plane area of a memory cell.
  • a semiconductor storage apparatus including: a first transistor including a first gate electrode via a ferroelectric film on an activation region including source or drain regions; and a second transistor including source or drain regions in an activation layer provided on the first gate electrode and a second gate electrode on the activation layer via an insulating film.
  • a product-sum calculation apparatus including: a first transistor including a first gate electrode via a ferroelectric film on an activation region including source or drain regions; and a second transistor including source or drain regions in an activation layer provided on the first gate electrode and a second gate electrode on the activation layer via an insulating film.
  • electronic equipment including: a semiconductor storage apparatus including: a first transistor including a first gate electrode via a ferroelectric film on an activation region including source or drain regions; and a second transistor including source or drain regions in an activation layer provided on the first gate electrode and a second gate electrode on the activation layer via an insulating film.
  • a semiconductor storage apparatus As described above, according to the present disclosure, there are provided a semiconductor storage apparatus, a product-sum calculation apparatus, and electronic equipment in which memory cells are highly integrated and highly densified.
  • FIG. 1 is a circuit diagram showing an equivalent circuit of a semiconductor storage apparatus according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic view showing a plane structure and a cross-sectional structure of the semiconductor storage apparatus according to the embodiment.
  • FIG. 3 is a plan view and a cross-sectional view explaining a process of a method for manufacturing the semiconductor storage apparatus according to the embodiment.
  • FIG. 4 is a plan view and a cross-sectional view explaining a process of a method for manufacturing the semiconductor storage apparatus according to the embodiment.
  • FIG. 5 is a plan view and a cross-sectional view explaining a process of a method for manufacturing the semiconductor storage apparatus according to the embodiment.
  • FIG. 6 is a plan view and a cross-sectional view explaining a process of a method for manufacturing the semiconductor storage apparatus according to the embodiment.
  • FIG. 7 is a plan view and a cross-sectional view explaining a process of a method for manufacturing the semiconductor storage apparatus according to the embodiment.
  • FIG. 8 is a plan view and a cross-sectional view explaining a process of a method for manufacturing the semiconductor storage apparatus according to the embodiment.
  • FIG. 9 is a plan view and a cross-sectional view explaining a process of a method for manufacturing the semiconductor storage apparatus according to the embodiment.
  • FIG. 10 is a plan view and a cross-sectional view explaining a process of a method for manufacturing the semiconductor storage apparatus according to the embodiment.
  • FIG. 11 is a plan view and a cross-sectional view explaining a process of a method for manufacturing the semiconductor storage apparatus according to the embodiment.
  • FIG. 12 is a plan view and a cross-sectional view explaining a process of a method for manufacturing the semiconductor storage apparatus according to the embodiment.
  • FIG. 13 is a plan view and a cross-sectional view explaining a process of a method for manufacturing the semiconductor storage apparatus according to the embodiment.
  • FIG. 14 is a plan view and a cross-sectional view explaining a process of a method for manufacturing a semiconductor storage apparatus according to a variation.
  • FIG. 15 is a plan view and a cross-sectional view explaining a process of a method for manufacturing a semiconductor storage apparatus according to a variation.
  • FIG. 16 is a plan view and a cross-sectional view explaining a process of a method for manufacturing a semiconductor storage apparatus according to a variation.
  • FIG. 17 is a plan view and a cross-sectional view explaining a process of a method for manufacturing a semiconductor storage apparatus according to a variation.
  • FIG. 18 is a schematic diagram showing a plane structure and a cross-sectional structure of a semiconductor storage apparatus according to a variation.
  • FIG. 19 is a schematic circuit diagram showing an equivalent circuit of a product-sum calculation apparatus.
  • FIG. 20 is a schematic diagram explaining application of the semiconductor storage apparatus according to an embodiment of the present disclosure to a product-sum calculation apparatus.
  • FIG. 21A is an external view showing an example of electronic equipment in which the semiconductor storage apparatus according to the embodiment is mounted.
  • FIG. 21B is an external view showing an example of electronic equipment in which the semiconductor storage apparatus according to the embodiment is mounted.
  • FIG. 21C is an external view showing an example of electronic equipment in which the semiconductor storage apparatus according to the embodiment is mounted.
  • FIG. 1 is a circuit diagram showing an equivalent circuit of a semiconductor storage apparatus according to the present embodiment.
  • gate represents a gate electrode of a field effect transistor
  • drain represents a drain electrode or a drain region of the field effect transistor
  • source represents a source electrode or a source region of the field effect transistor
  • a semiconductor storage apparatus 10 includes a first transistor 11 and a second transistor 12 connected to the gate of the first transistor 11 .
  • the first transistor 11 is a field effect transistor having a gate insulating film including a ferroelectric material.
  • the first transistor 11 stores information in the direction of remanent polarization of the gate insulating film.
  • the first transistor 11 is connected to a second bit line BL ⁇ at one of the source and the drain, and is connected to a source line Vs at the other of the source and the drain.
  • the source line Vs may be electrically connected to a power supply VDD or a ground GND.
  • the second transistor 12 is a field effect transistor having a gate insulating film including, for example, a paraelectric material.
  • the second transistor 12 functions as a switching element that controls voltage application to the gate of the first transistor 11 .
  • the second transistor 12 is connected to the gate of the first transistor 11 at one of the source and the drain, and is connected to a first bit line BL at the other of the source and the drain.
  • the gate of the second transistor 12 is connected to a word line WL, and ON/OFF of the second transistor 12 is controlled by voltage application from the word line WL.
  • the second transistor 12 may be a field effect transistor having a gate insulating film including a ferroelectric material.
  • the semiconductor storage apparatus 10 first turns on the second transistor 12 by applying a voltage to the word line WL. Next, the semiconductor storage apparatus 10 applies a predetermined potential difference to the first bit line BL and the second bit line BL ⁇ , thereby generating an electric field in the gate insulating film (that is, a ferroelectric film) of the first transistor 11 . Therefore, the semiconductor storage apparatus 10 can control the direction of the remanent polarization of the gate insulating film of the first transistor 11 by an external electric field and write information in the first transistor 11 .
  • the semiconductor storage apparatus 10 first turns on the second transistor 12 by applying a voltage to the word line WL. Next, the semiconductor storage apparatus 10 applies a voltage to the first bit line BL to turn on the first transistor 11 , and then causes a current to flow between the second bit line BL ⁇ and the source line Vs. Since a threshold voltage Vt of the first transistor 11 changes according to the direction of remanent polarization of the gate insulating film, the channel resistance of the first transistor 11 changes according to the direction of remanent polarization of the gate insulating film. Therefore, the semiconductor storage apparatus 10 can read the information stored in the first transistor 11 by measuring the magnitude of the current flowing between the second bit line BL ⁇ and the source line Vs.
  • the semiconductor storage apparatus 10 can operate as a ferroelectric random access memory (FeRAM) that stores 1-bit information of 0 or 1 in the first transistor 11 .
  • FeRAM ferroelectric random access memory
  • the semiconductor storage apparatus 10 since the source or the drain of the second transistor 12 is connected to the gate of the first transistor 11 , whether or not an electric field is applied to the gate insulating film of the first transistor 11 can be controlled by controlling the second transistor 12 .
  • the semiconductor storage apparatus 10 can selectively apply a voltage to the gate insulating film of the first transistor 11 when writing or reading information, and it is possible to prevent the information stored in the unselected first transistor 11 from being overwritten. Furthermore, the semiconductor storage apparatus 10 can selectively apply an electric field to the gate insulating film of the first transistor 11 when writing or reading information, and it is possible to suppress deterioration of the ferroelectric material constituting the gate insulating film.
  • the second transistor 12 can be provided on the first transistor by forming the second transistor 12 as a so-called thin film transistor (TFT). According to this, the semiconductor storage apparatus 10 can reduce the plane area of the semiconductor storage apparatus 10 as compared with the case where the first transistor 11 and the second transistor 12 are arranged in a plane.
  • TFT thin film transistor
  • FIG. 2 is a schematic view showing a plane structure and a cross-sectional structure of the semiconductor storage apparatus 10 according to the present embodiment.
  • FIG. 2 shows a cross-section obtained by cutting the plan view along each of line A-A, line B-B, or line C-C.
  • first conductivity type represents one of “p type” and “n type”
  • second conductivity type represents the other of “p type” and “n type” different from the “first conductivity type”.
  • a storage apparatus 1 is provided on a semiconductor substrate 100 .
  • the storage apparatus 1 is formed by arranging a large number of semiconductor storage apparatuses 10 that stores 1-bit information in a matrix on the semiconductor substrate 100 , and stores a large amount of information.
  • a region surrounded by a broken line corresponds to one semiconductor storage apparatus 10 .
  • the first transistor 11 includes a ferroelectric film 140 provided on the semiconductor substrate 100 , a first gate electrode 130 provided on the ferroelectric film 140 , and source or drain regions 151 provided on the semiconductor substrate 100 .
  • One of the source or drain regions 151 of the first transistor 11 is electrically connected to a second wiring layer 410 (source line Vs) extending in a second direction (upward and downward direction when directly facing FIG. 2 ) via a contact 271 .
  • the other of the source or drain regions 151 is electrically connected to a third wiring layer 512 (second bit line BL ⁇ ) extending in a first direction (right and left direction when directly facing FIG. 2 ) orthogonal to the second direction via a contact 272 and the second wiring layer 420 .
  • the second transistor 12 includes an activation layer 250 extending in the second direction passing over the first gate electrode 130 , a gate insulating film 240 provided on the activation layer 250 , and a second gate electrode 230 extending in the first direction passing over the activation layer 250 via the gate insulating film 240 .
  • the activation layer 250 and the second gate electrode 230 are provided so as to be orthogonal to each other.
  • a source or drain region is provided in the activation layer 250 on both sides of the intersection of the activation layer 250 and the second gate electrode 230 .
  • the second gate electrode 230 functions as the word line WL by being provided so as to extend in the first direction.
  • One of the source or drain regions provided in the activation layer 250 is electrically connected to the first gate electrode 130 .
  • the other of the source or drain regions provided in the activation layer 250 is electrically connected to a first wiring layer 310 (first bit line BL) extending in the second direction via a contact 261 .
  • the semiconductor substrate 100 is a substrate including a semiconductor material and on which the first transistor 11 is formed.
  • the semiconductor substrate 100 may be a silicon substrate or a silicon on insulator (SOI) substrate in which an insulating film, e.g., of SiO 2 , is sandwiched in the silicon substrate.
  • the semiconductor substrate 100 may be a substrate including another elemental semiconductor such as germanium, or a substrate including a compound semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), or silicon carbide (SiC).
  • An element isolation layer 105 includes an insulating material, and electrically insulates each of the semiconductor storage apparatuses 10 provided on the semiconductor substrate 100 from each other.
  • the element isolation layer 105 is provided, for example, so as to extend in the first direction of the semiconductor substrate 100 (right and left direction when directly facing FIG. 2 ), and separates the surface of the semiconductor substrate 100 into parallel strip-shaped regions that are separated from each other.
  • the parallel strip-shaped regions separated from each other by the element isolation layer 105 become an activation region 150 in which the first transistor 11 is formed.
  • the semiconductor substrate 100 of the activation region 150 may be doped with, for example, a first conductivity type impurity (for example, a p-type impurity such as boron (B) or aluminum (Al)).
  • the element isolation layer 105 may include an insulating oxynitride such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON).
  • the element isolation layer 105 may be formed such that a part of the semiconductor substrate 100 in a predetermined region is removed by etching or the like using a shallow trench isolation (STI) method and then an opening formed by the etching or the like is filled with silicon oxide (SiO x ).
  • STI shallow trench isolation
  • the element isolation layer 105 may be formed by thermally oxidizing the semiconductor substrate 100 in a predetermined region using a local oxidation of silicon (LOCOS) method.
  • LOCS local oxidation of silicon
  • the ferroelectric film 140 includes a ferroelectric material and is provided on the semiconductor substrate 100 . Specifically, the ferroelectric film 140 is provided on the semiconductor substrate 100 for each memory cell so as to cross the activation region 150 in the second direction.
  • the ferroelectric film 140 includes a ferroelectric material which is spontaneously polarized and whose remanent polarization direction can be controlled by an external electric field.
  • the ferroelectric film 140 may include a perovskite structure ferroelectric material such as lead zirconate titanate (Pb(Zr,Ti)O 3 : PZT) or strontium bismuth tantalate (SrBi 2 Ta 2 O 9 : SBT).
  • the ferroelectric film 140 may be a ferroelectric film obtained by modifying a film including a high dielectric material such as HfO x , ZrO x , or HfZrO x by heat treatment or the like, or may be a ferroelectric film modified by introducing atoms such as lanthanum (La), silicon (Si), or gadolinium (Gd) into a film including the aforementioned high dielectric material.
  • the ferroelectric film 140 may include a single layer or may include a plurality of layers.
  • the ferroelectric film 140 may be a single layer film including a ferroelectric material such as HfO x .
  • the ferroelectric film 140 can be formed by using atomic layer deposition (ALD), chemical vapor deposition (CVD), or the like.
  • the first gate electrode 130 includes a conductive material and is provided on the ferroelectric film 140 . Specifically, the first gate electrode 130 is provided for each memory cell on the ferroelectric film 140 so as to cross the activation region 150 in the second direction.
  • the first gate electrode 130 may include polysilicon or the like, and may include a metal, an alloy, a metal compound, or an alloy of a refractory metal (such as Ni) and polysilicon (so-called silicide). Furthermore, the first gate electrode 130 may include ruthenium (Ru), ruthenium oxide (RuO 2 ), or the like. Specifically, the first gate electrode 130 may be formed in a stack structure of a metal layer and a polysilicon layer. For example, the first gate electrode 130 may be formed in a stack structure of a metal layer including TiN or TaN provided on the ferroelectric film 140 and a polysilicon layer. With such a stack structure, the first gate electrode 130 can reduce the wiring resistance as compared with the case where it includes only the polysilicon layer.
  • the source or drain regions 151 are a second conductivity type region formed in the semiconductor substrate 100 .
  • the source or drain regions 151 are provided in the activation region 150 on both sides of the first gate electrode 130 .
  • One of the source or drain regions 151 is electrically connected to the second wiring layer 410 (source line Vs) extending in the second direction via the contact 271 .
  • the other of the source or drain regions 151 is electrically connected to the third wiring layer 512 (second bit line BL ⁇ ) extending in the first direction via the contact 272 and the second wiring layer 420 .
  • the source or drain regions 151 may be formed by introducing a second conductivity type impurity (for example, an n-type impurity such as phosphorus (P) or arsenic (As)) into a predetermined region of the activation region 150 . Furthermore, between the source or drain region 151 and the first gate electrode 130 , a lightly-doped drain (LDD) region having the same conductivity type as the source or drain region 151 and having a lower concentration than the source or drain region 151 may be formed.
  • a second conductivity type impurity for example, an n-type impurity such as phosphorus (P) or arsenic (As)
  • LDD lightly-doped drain
  • any of the source or drain regions 151 provided on both sides of the first gate electrode 130 may function as a source region or any of them may function as a drain region. These can be arbitrarily changed depending on the polarity of the conductivity type impurity or the wiring to be connected.
  • a sidewall insulating film 132 includes an insulating material, and is provided as a sidewall on the side surface of the first gate electrode 130 and the activation layer 250 , which will be described later.
  • the sidewall insulating film 132 can be formed by stacking the first gate electrode 130 and the activation layer 250 , forming an insulating film uniformly, and performing vertical anisotropic etching on the insulating film.
  • the sidewall insulating film 132 may include an insulating oxynitride such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON) in a single layer or a plurality of layers.
  • the sidewall insulating film 132 shields the conductive impurities introduced into the activation region 150 , so that the positional relationship between the first gate electrode 130 and the source or drain region 151 into which the conductivity type impurity is introduced is caused to be self-aligned.
  • the impurity can be introduced into the activation region 150 step by step, so that the LDD region can be self-alignedly formed between the source or drain region 151 and the first gate electrode 130 .
  • the activation layer 250 is provided on the first gate electrode 130 and is provided over the plurality of activation regions 150 by being extended in the second direction. Specifically, the activation layer 250 alternately passes over the first gate electrode 130 and the semiconductor substrate 100 along the outer shape of the first gate electrode 130 and the semiconductor substrate 100 so as to extend up and down and is provided by being extended in the second direction.
  • the activation layer 250 is a layer in which the channel of the second transistor and the source or drain region are formed, and includes a semiconductor material.
  • the activation layer 250 may include polycrystalline, single-crystal, or amorphous silicon (Si), may include a compound semiconductor such as germanium (Ge), gallium arsenide (GaAs), or indium gallium arsenide (InGaAs), may include an oxide semiconductor such as zinc oxide (ZnO) or gallium indium tin oxide (InGaZnO), or may include a two-dimensional semiconductor such as molybdenum sulfide (MoS 2 ).
  • the source or drain region of the second transistor 12 is formed.
  • the channel of the second transistor 12 may be formed in the activation layer 250 in the A-A cross-section of FIG. 2 .
  • the source or drain region of the second transistor 12 may be formed by introducing the second conductivity type impurity into the activation layer 250 in the B-B cross-section of FIG. 2 .
  • One of the source or drain regions formed in the activation layer 250 is formed on the first gate electrode 130 and is electrically connected to the first gate electrode 130 . Furthermore, the other of the source or drain regions provided in the activation layer 250 is electrically connected to a first wiring layer 310 (first bit line BL) extending in the second direction via the contact 261 .
  • the gate insulating film 240 includes an insulating material and is provided on the semiconductor substrate 100 and the activation layer 250 . Specifically, the gate insulating film 240 is uniformly provided on the first transistor 11 and the activation layer 250 .
  • the gate insulating film 240 may include an insulating material known as a gate insulating film of a field effect transistor.
  • the gate insulating film 240 may include an insulating oxynitride such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON).
  • the second gate electrode 230 includes a conductive material and is provided on the gate insulating film 240 by extending in the first direction. Specifically, the second gate electrode 230 is provided on the element isolation layer 105 of the semiconductor substrate 100 so as to extend in the first direction via the gate insulating film 240 . Furthermore, the second gate electrode 230 is provided on the activation layer 250 via the gate insulating film 240 across the orthogonal activation layer 250 . The second gate electrode 230 functions as the word line WL by being provided so as to extend in the first direction.
  • the second gate electrode 230 may include polysilicon or the like, and may include a metal, an alloy, a metal compound, or an alloy of a refractory metal (such as Ni) and polysilicon (so-called silicide). Furthermore, the second gate electrode 230 may include ruthenium (Ru), ruthenium oxide (RuO 2 ), or the like. Specifically, the second gate electrode 230 may be formed in a stack structure of a metal layer and a polysilicon layer. For example, the second gate electrode 230 may be formed in a stack structure of a metal layer including TiN or TaN provided on the gate insulating film 240 and a polysilicon layer. With such a stack structure, the second gate electrode 230 can reduce the wiring resistance as compared with the case where it includes only the polysilicon layer.
  • the second gate electrode 230 is provided so as to be orthogonal to the activation layer 250 via the gate insulating film 240 and forms the channel of the second transistor 12 in the activation layer 250 overlapping with the second gate electrode 230 in a plan view.
  • the channel formed in the activation layer 250 reduces the resistance between the source region and the drain region formed in the activation layer 250 , thereby bringing conduction between the first gate electrode 130 and the contact 261 and the first wiring layer 310 .
  • a planarized film 200 includes an insulating material, accommodates the first transistor 11 and the second transistor 12 , and is provided over the entire surface of the semiconductor storage apparatus 10 .
  • the planarized film 200 may include an insulating oxynitride such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON).
  • the contact 261 includes a conductive material and is provided to extend through the planarized film 200 and the gate insulating film 240 . Specifically, the contact 261 is provided to extend through the planarized film 200 and the gate insulating film 240 on the source or drain region of the second transistor 12 provided in the activation layer 250 on the side facing the first gate electrode 130 across the second gate electrode 230 extending in the first direction. Therefore, the contact 261 electrically connects the other of the source and the drain of the second transistor to the first wiring layer 310 (first bit line BL).
  • the contact 261 may include a low resistance metal such as titanium (Ti) or tungsten (W), or a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN).
  • the contact 261 may include a single layer or may include a stack body of a plurality of layers.
  • the contact 261 may include a stack body including Ti or TiN and W.
  • a lower first interlayer film 301 accommodates the first wiring layer 310 and is provided on the planarized film 200 over the entire surface of the semiconductor storage apparatus 10 .
  • the lower first interlayer film 301 may include an insulating oxynitride such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON).
  • the first wiring layer 310 includes a conductive material and is provided on the planarized film 200 . Specifically, the first wiring layer 310 is provided on the contact 261 as wiring extending in the second direction. The first wiring layer 310 functions as the first bit line BL by being electrically connected to the other of the source and the drain of the second transistor 12 via the contact 261 .
  • the first wiring layer 310 may include a metal material such as copper (Cu) or aluminum (Al), or may include a Cu damascene structure or a dual damascene structure, for example.
  • An upper first interlayer film 302 is provided on the lower first interlayer film 301 over the entire surface of the semiconductor storage apparatus 10 .
  • the upper first interlayer film 302 is provided to electrically insulate the first wiring layer 310 from the second wiring layers 410 and 420 .
  • the upper first interlayer film 302 may include an insulating oxynitride such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON).
  • the contacts 271 and 272 include a conductive material and are provided so as to extend through the planarized film 200 , the lower first interlayer film 301 , and the upper first interlayer film 302 .
  • the contact 271 is provided on one of the source or drain regions 151 and electrically connects one of the source and the drain of the first transistor 11 to the second wiring layer 410 (source line Vs).
  • the contact 272 is provided on the other of the source or drain regions 151 , and electrically connects the other of the source and the drain of the first transistor 11 to the third wiring layer 512 (second bit line BL ⁇ ) via the second wiring layer 420 and a via 511 .
  • the contacts 271 and 272 may include a low resistance metal such as titanium (Ti) or tungsten (W), or a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN).
  • the contacts 271 and 272 may include a single layer or may include a stack body of a plurality of layers.
  • the contacts 271 and 272 may include a stack body including Ti or TiN and W.
  • a second interlayer film 400 accommodates the second wiring layers 410 and 420 and is provided on the upper first interlayer film 302 over the entire surface of the semiconductor storage apparatus 10 .
  • the second interlayer film 400 may include an insulating oxynitride such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON).
  • the second wiring layers 410 and 420 include a conductive material and are provided on the upper first interlayer film 302 .
  • the second wiring layer 410 is provided on the contact 271 as wiring extending in the second direction.
  • the second wiring layer 410 functions as the source line Vs by being electrically connected to one of the source and the drain of the first transistor 11 via the contact 271 .
  • the second wiring layer 420 is provided on the contact 272 as a wiring layer that electrically connects the contact 272 in a lower layer and the via 511 in an upper layer.
  • the second wiring layers 410 and 420 may include a metal material such as copper (Cu) or aluminum (Al), or may include a Cu damascene structure or a dual damascene structure.
  • the via 511 includes a conductive material and is provided to extend through a lower third interlayer film 501 . Specifically, the via 511 is provided on the second wiring layer 420 as a via that electrically connects the second wiring layer 420 in a lower layer and the third wiring layer 512 in an upper layer.
  • the via 511 may include a low resistance metal such as titanium (Ti) or tungsten (W), or a metal compound such as titanium nitride (TiN) or tantalum nitride (TaN).
  • the via 511 may include a single layer or may include a stack body of a plurality of layers, and may include a stack body including Ti or TiN and W, for example.
  • the lower third interlayer film 501 accommodates the via 511 and is provided on the second interlayer film 400 over the entire surface of the semiconductor storage apparatus 10 .
  • the lower third interlayer film 501 may include an insulating oxynitride such as silicon oxide (SiO x ), silicon nitride (SiN x ), or silicon oxynitride (SiON).
  • the third wiring layer 512 includes a conductive material and is provided on the via 511 as wiring extending in the first direction.
  • the third wiring layer 512 functions as the second bit line BL ⁇ by being electrically connected to the other of the source and the drain of the first transistor 11 via the via 511 , the second wiring layer 420 , and the contact 272 .
  • the third wiring layer 512 may include a metal material such as copper (Cu) or aluminum (Al), or may include a Cu damascene structure or a dual damascene structure.
  • the second transistor 12 can be formed as a thin film transistor (TFT) on the first transistor 11 .
  • TFT thin film transistor
  • the semiconductor storage apparatus 10 enables control of the presence or absence of the generation of an electric field in the ferroelectric film 140 of the first transistor 11 by the second transistor 12 and enables formation with a reduced plane area. With this structure, since the semiconductor storage apparatus 10 can improve the degree of integration of the memory cells of the storage apparatus 1 , it is possible to improve the storage density of the storage apparatus 1 .
  • FIGS. 3 to 13 are plan views and cross-sectional views explaining a process of a method for manufacturing the semiconductor storage apparatus 10 .
  • each of the cross-sectional views shows a cross-section obtained by cutting the plan view along the line AA, the line BB, and the line CC.
  • the element isolation layer 105 is formed on the semiconductor substrate 100 , and the activation region 150 in which the first transistor 11 is formed is formed.
  • a SiO 2 film is formed on the semiconductor substrate 100 including Si by dry oxidation or the like, and a Si 3 N 4 film is further formed by low pressure chemical vapor deposition (CVD) or the like.
  • CVD low pressure chemical vapor deposition
  • a resist layer patterned so as to protect the activation region 150 is formed on the Si 3 N 4 film, and the SiO 2 film, the Si 3 N 4 film, and the semiconductor substrate 100 are etched to a depth of 350 nm to 400 nm.
  • the element isolation layer 105 is formed by forming SiO 2 with a film thickness of 650 nm to 700 nm and filling the opening by etching.
  • high density plasma CVD which has favorable step coverage and is capable of forming a dense SiO 2 film may be used.
  • the surface of the semiconductor substrate 100 is planarized by removing the excessively formed SiO 2 film using chemical mechanical polish (CMP) or the like. It is sufficient if the removal of the SiO 2 film by CMP may be performed, for example, until the Si 3 N 4 film is exposed.
  • CMP chemical mechanical polish
  • the Si 3 N 4 film is removed using hot phosphoric acid or the like.
  • the semiconductor substrate 100 can also be annealed under N 2 , O 2 , or H 2 /O 2 environment before the removal of the Si 3 N 4 film.
  • the surface of the semiconductor substrate 100 of the activation region 150 is oxidized by about 10 nm to form an oxide film 101 , and then a first conductivity type impurity (for example, boron (B) or the like) is ion-implanted to turn the activation region 150 to a first conductivity type well region.
  • a first conductivity type impurity for example, boron (B) or the like
  • the first gate electrode 130 is formed on the ferroelectric film 140 .
  • the oxide film 101 covering the surface of the semiconductor substrate 100 is peeled off using a hydrofluoric acid solution or the like.
  • the oxide film 101 may be a thermal oxide film (SiO 2 ), a thermal oxynitride film (SiON), or a plasma-nitrided oxynitride film (SiON).
  • hafnium oxide (HfO x ) is formed to a film thickness of 3 nm to 10 nm on the semiconductor substrate 100 .
  • hafnium oxide (HfO x ) which is a high dielectric material, is converted into the ferroelectric film 140 by being subjected to annealing treatment in the subsequent stage.
  • hafnium oxide instead of hafnium oxide, a high dielectric material such as zirconium oxide (ZrO x ) or hafnium zirconium oxide (HfZrO x ) can be used. Furthermore, it is also possible to dope these high dielectric materials with lanthanum (La), silicon (Si), gadolinium (Gd), or the like to convert them into ferroelectric materials. Furthermore, as the ferroelectric film 140 , it is possible to use a perovskite-based ferroelectric material such as lead zirconate titanate (PZT) or strontium bismuth tantalate (SBT).
  • PZT lead zirconate titanate
  • SBT strontium bismuth tantalate
  • hafnium oxide (HfO x ) is formed to a film thickness of 5 nm to 20 nm as an electrode material on hafnium oxide (HfO x ).
  • TaN, Ru, RuO 2 , or the like may be used as the electrode material.
  • anisotropic etching is performed to pattern the formed hafnium oxide (HfO x ) and TiN, so that hafnium oxide (HfO x ) and TiN are deposited on the region covering the activation region 150 .
  • the activation layer 250 and the first gate electrode 130 are simultaneously patterned.
  • a polysilicon film is formed to a film thickness of 50 nm to 150 nm by using low pressure CVD with SiH 4 gas as a source gas at a film forming temperature of 580° C. to 620° C. Thereafter, by using a patterned resist as a mask, anisotropic etching is performed on the formed polysilicon to form the activation layer 250 .
  • anisotropic etching for example, HBr or Cl-based gas can be used.
  • the first gate electrode 130 is formed by simultaneously performing anisotropic etching on TiN, which is an under layer of the polysilicon.
  • the sidewall insulating film 132 is formed on both side surfaces of the first gate electrode 130 and the activation layer 250 , and the source or drain region 151 is formed in the semiconductor substrate 100 .
  • arsenic (As) that is the second conductivity type impurity is ion-implanted on both sides of the first gate electrode 130 and the activation layer 250 at a concentration of 5 to 20 ⁇ 10 13 /cm 2 at 5 keV to 20 keV to form the LDD region. Since the LDD region suppresses a short channel effect, it is possible to suppress the characteristic variation of the first transistor 11 .
  • phosphorus (P) can be used as the second conductivity type impurity.
  • Si 3 N 4 is formed with a film thickness of 30 nm to 50 nm by plasma CVD to form an insulating film for sidewalls. Thereafter, anisotropic etching is performed on the insulating film for sidewalls to form the sidewall insulating film 132 on both side surfaces of the first gate electrode 130 and the activation layer 250 .
  • arsenic (As) which is a second conductivity type impurity is ion-implanted into the activation layer 250 at 20 keV to 50 ke at a concentration of 1 to 2 ⁇ 10 15 /cm 2 . Therefore, the second conductivity type impurity is introduced into the semiconductor substrate 100 on both sides of the first gate electrode 130 to form the source or drain region 151 . Moreover, rapid thermal annealing (RTA) is performed at 1000° C. for 5 seconds to activate the ion-implanted second conductivity type impurity. Therefore, the first transistor 11 is formed.
  • RTA rapid thermal annealing
  • the annealing for activating the second conductivity type impurity described above may also serve as an annealing treatment for converting hafnium oxide (HfO x ), which is a high dielectric material, into a ferroelectric material. In such a case, the annealing conditions may be adjusted appropriately.
  • a silicide compound such as CoSi 2 or NiSi may be formed on the surface of the source or drain region 151 in order to reduce the contact resistance.
  • the source or drain region is formed by introducing the second conductivity type impurity into the activation layer 250 , and the gate insulating film 240 is formed on the activation layer 250 .
  • arsenic (As) which is a second conductivity type impurity is ion-implanted into the activation layer 250 of a predetermined region at 10 keV to 50 keV at a concentration of 1 to 2 ⁇ 10 15 /cm 2 to introduce the second conductivity type impurity to the activation layer 250 of the predetermined region. Therefore, the source or drain region can be formed in the activation layer 250 .
  • the predetermined region of the activation layer 250 into which the second conductivity type impurity is introduced is, for example, a region on both sides of a region where the second gate electrode 230 is formed in the subsequent stage.
  • the gate insulating film 240 is formed on the activation layer 250 by forming SiO 2 or SiN to a film thickness of 5 nm to 10 nm over the entire surface of the semiconductor storage apparatus 10 by CVD.
  • the second gate electrode 230 extending in the first direction is formed on the gate insulating film 240 so as to be orthogonal to the activation layer 250 extending in the second direction.
  • a polysilicon film is formed to a film thickness of 20 nm to 150 nm on the gate insulating film 240 by using low pressure CVD with SiH 4 gas as a source gas at a film forming temperature of 580° C. to 620° C. Thereafter, by using a patterned resist as a mask, anisotropic etching is performed on the formed polysilicon to form the second gate electrode 230 .
  • anisotropic etching for example, HBr or Cl-based gas can be used.
  • W, WSi x , or the like may be further stacked on the second gate electrode 230 in order to reduce the resistance, and the second gate electrode 230 may be salicided. Therefore, the second transistor 12 is formed.
  • the contact 261 is formed.
  • SiO 2 is formed over the entire surface of the semiconductor storage apparatus 10 by CVD or the like to a film thickness of 50 nm to 200 nm so as to accommodate the first transistor 11 and the second transistor 12 . Thereafter, the formed SiO 2 layer is planarized by the CMP method to form the planarized film 200 .
  • etching is performed to form an opening in the planarized film 200 .
  • the opening for exposing the activation layer 250 on the side facing the first gate electrode 130 across the second gate electrode 230 is formed in the planarized film 200 by etching.
  • Ti and TiN are formed with respect to the opening of the planarized film 200 by CVD or the like, W is further formed, and then planarized by the CMP method, so that the contact 261 is formed on the activation layer 250 .
  • Ti and TiN may be formed by a sputtering method using ion metal plasma (IMP), for example.
  • planarization may be performed using entire surface etching back instead of the CMP method.
  • the first wiring layer 310 is formed.
  • the first wiring layer 310 may include Al or the like.
  • the first wiring layer 310 functions as the first bit line BL by being provided on the contact 261 so as to extend in the second direction.
  • SiO 2 is formed over the entire surface of the semiconductor storage apparatus 10 on the lower first interlayer film 301 to a film thickness of 100 nm to 500 nm, and then planarized by the CMP method, so that the upper first interlayer film 302 is formed.
  • an opening for exposing the source or drain region 151 is formed in the upper first interlayer film 302 , the lower first interlayer film 301 , and the planarized film 200 by etching.
  • Ti and TiN are formed with respect to the formed opening by CVD or the like, W is further formed, and then planarized by the CMP method, so that the contacts 271 and 272 are formed on the source or drain region 151 .
  • Ti and TiN may be formed by a sputtering method using ion metal plasma (IMP), for example.
  • planarization may be performed using entire surface etching back instead of the CMP method.
  • the second wiring layers 410 and 420 are formed.
  • SiO 2 is formed over the entire surface of the semiconductor storage apparatus 10 on the upper first interlayer film 302 to a film thickness of 10 nm to 500 nm, and then planarized by the CMP method, so that the second interlayer film 400 is formed. Then, after forming an opening for forming an electrical connection with the contacts 271 and 272 in the second interlayer film 400 by etching, Cu or the like is used as a wiring material to form the second wiring layers 410 and 420 by using a damascene structure or a dual damascene structure. Note that the second wiring layers 410 and 420 may include Al or the like.
  • the second wiring layer 410 functions as the source line Vs by being provided on the contact 271 so as to extend in the second direction. Furthermore, the second wiring layer 420 electrically connects the via 511 formed in an upper layer and the contact 272 .
  • the via 511 is formed.
  • the third wiring layer 512 is formed.
  • SiO 2 is formed over the entire surface of the semiconductor storage apparatus 10 on the second interlayer film 400 to a film thickness of 100 nm to 500 nm, and then planarized by the CMP method, so that the lower third interlayer film 501 is formed. Then, an opening for forming an electrical connection with the second wiring layer 420 is formed in the lower third interlayer film 501 by etching. Next, TiN is formed with respect to the formed opening by CVD or the like, W is further formed, and then planarized by the CMP, so that the via 511 is formed. Note that TiN may be formed by a sputtering method using IMP, or the like. Furthermore, planarization may be performed using entire surface etching back instead of CMP.
  • the third wiring layer 512 is used as a wiring material to form the third wiring layer 512 by using a damascene structure or a dual damascene structure.
  • the third wiring layer 512 may include Al or the like.
  • the third wiring layer 512 functions as the second bit line BL ⁇ by being provided on the via 511 so as to extend in the first direction.
  • the semiconductor storage apparatus 10 can be formed.
  • FIGS. 14 to 17 are plan views and cross-sectional views explaining a process of a method for manufacturing the semiconductor storage apparatus 20 .
  • FIG. 18 is a schematic view showing a plane structure and a cross-sectional structure of the semiconductor storage apparatus 20 .
  • each of the cross-sectional views and each of the cross-sectional views show a cross-section obtained by cutting the plan view along the line AA or the line BB.
  • the semiconductor storage apparatus 20 instead of the semiconductor substrate 100 , a semiconductor layer 100 A formed on a substrate is used.
  • the memory cell can be multi-layered by repeatedly forming a stack structure from the semiconductor layer 100 A to the upper first interlayer film 302 . With this structure, in the storage apparatus 2 in which a large number of semiconductor storage apparatuses 20 is arranged in a matrix, it is possible to integrate memory cells at a higher density.
  • the respective configurations that are distinguished by being designated with “A” or “B” added to the reference numerals are substantially similar to the respective configurations of the semiconductor storage apparatus 10 that are not designated with “A” and “B” for the reference numerals, and therefore detailed description thereof will be omitted.
  • a semiconductor layer 100 A is formed on a substrate, then an element isolation layer 105 A is formed on the semiconductor layer 100 A, and an activation region 150 A in which the first transistor 11 is formed is formed.
  • an amorphous silicon or a polysilicon film is formed on the substrate to a film thickness of 20 nm to 100 nm by using low pressure CVD with SiH 4 gas as a source gas at a film forming temperature of 580° C. to 620° C.
  • the material of the substrate is not particularly limited, and other patterns, wirings, elements, or circuits may be formed on the substrate.
  • a circuit for driving the semiconductor storage apparatus 20 may be formed on the substrate.
  • a SiO 2 film is formed on the semiconductor layer 100 A by dry oxidation or the like, and a Si 3 N 4 film is further formed by low pressure CVD or the like.
  • a resist layer patterned so as to protect the activation region 150 A is formed on the Si 3 N 4 film, and the SiO 2 film, the Si 3 N 4 film, and the semiconductor layer 100 A are etched to the depth of the film thickness of the semiconductor layer 100 A.
  • the element isolation layer 105 A is formed by forming SiO 2 and filling the opening by etching.
  • high density plasma CVD which has favorable step coverage and is capable of forming a dense SiO 2 film may be used.
  • the surface of the semiconductor layer 100 A is planarized by removing the excessively formed SiO 2 film using chemical mechanical polish (CMP) or the like. It is sufficient if the removal of the SiO 2 film by CMP may be performed, for example, until the Si 3 N 4 film is exposed.
  • CMP chemical mechanical polish
  • the Si 3 N 4 film is removed using hot phosphoric acid or the like.
  • the semiconductor layer 100 A can also be annealed under N 2 , O 2 , or H 2 /O 2 environment before the removal of the Si 3 N 4 film.
  • the surface of the semiconductor layer 100 A of the activation region 150 A is oxidized about 10 nm to form an oxide film 101 A.
  • FIG. 15 the process described with reference to FIGS. 3 to 11 is performed to form the first transistor 11 and the second transistor 12 on the semiconductor layer 100 A. Thereafter, a semiconductor layer 100 B is formed.
  • the surfaces of the contacts 271 A and 272 A are retreated (recessed) by etching or the like, and Ti is deposited about 5 nm to 20 nm by CVD or the like. Thereafter, the deposited Ti is planarized by CMP or the like. Note that cobalt (Co) or the like having high heat resistance may be used instead of titanium (Ti).
  • an amorphous silicon or a polysilicon film is formed on the second interlayer film 400 A to a film thickness of 20 nm to 100 nm by using low pressure CVD with SiH 4 gas as a source gas at a film forming temperature of 580° C. to 620° C.
  • the formed amorphous silicon or polysilicon becomes the semiconductor layer 100 B, which is a second layer.
  • FIG. 16 the process described with reference to FIGS. 2 to 11 is performed to form a first transistor 11 B and a second transistor 12 B on the semiconductor layer 100 B.
  • the second wiring layers 410 and 420 are formed.
  • SiO 2 is formed over the entire surface of the semiconductor storage apparatus 20 on the upper first interlayer film 302 B to a film thickness of 10 nm to 500 nm, and then planarized by the CMP method, so that a second interlayer film 400 B is formed. Then, after forming an opening for forming an electrical connection with the contacts 271 B and 272 B in the second interlayer film 400 B by etching, Cu or the like is used as a wiring material to form the second wiring layers 410 and 420 by using a damascene structure or a dual damascene structure. Note that the second wiring layers 410 and 420 may include Al or the like.
  • the second wiring layer 410 functions as the source line Vs by being provided on the contact 271 B so as to extend in the second direction. Furthermore, the second wiring layer 420 electrically connects the via 511 formed in an upper layer and the contact 272 B.
  • the via 511 is formed.
  • the third wiring layer 512 is formed.
  • SiO 2 is formed over the entire surface of the semiconductor storage apparatus 20 on the second interlayer film 400 B to a film thickness of 100 nm to 500 nm, and then planarized by the CMP method, so that the lower third interlayer film 501 is formed. Then, an opening for forming an electrical connection with the second wiring layer 420 is formed in the lower third interlayer film 501 by etching. Next, TiN is formed with respect to the formed opening by CVD or the like, W is further formed, and then planarized by the CMP, so that the via 511 is formed. Note that TiN may be formed by a sputtering method using IMP, or the like. Furthermore, planarization may be performed using entire surface etching back instead of CMP.
  • the third wiring layer 512 is used as a wiring material to form the third wiring layer 512 by using a damascene structure or a dual damascene structure.
  • the third wiring layer 512 may include Al or the like.
  • the third wiring layer 512 functions as the second bit line BL ⁇ by being provided on the via 511 so as to extend in the first direction.
  • the semiconductor storage apparatus 20 according to the variation can be formed.
  • the semiconductor storage apparatus 20 according to the variation can achieve higher integration by further repeating the stack structure of the first transistor 11 and the second transistor 12 .
  • Table 1 is a table showing an example of voltages (unit: V) applied to each wiring in the write operation and the read operation of the semiconductor storage apparatus 10 .
  • the word line, the first bit line, and the second bit line of a selected memory cell are described as SWL, SBL, and SBL ⁇ , respectively. Furthermore, the word line, the first bit line, and the second bit line of an unselected memory cell are described as UWL, UBL, and UBL ⁇ , respectively. Moreover, the source line is described as Vs.
  • the potential of the first bit line BL is transmitted to the first gate electrode 130 of the first transistor 11 via the second transistor 12 , which is in the ON state. Furthermore, the potential of the second bit line BL ⁇ is transmitted to the source or drain region 151 of the first transistor 11 . Therefore, an external electric field having a high potential on the first gate electrode 130 side is generated in the ferroelectric film 140 of the first transistor 11 , and the polarization state of the ferroelectric film 140 is controlled. Therefore, the semiconductor storage apparatus 10 can write, for example, information “1” in the selected memory cell.
  • the potential of the first bit line BL is transmitted to the first gate electrode 130 of the first transistor 11 via the second transistor 12 , which is in the ON state. Furthermore, the potential of the second bit line BL ⁇ is transmitted to the source or drain region 151 of the first transistor 11 . Therefore, an external electric field having a low potential on the first gate electrode 130 side is generated in the ferroelectric film 140 of the first transistor 11 , and the polarization state of the ferroelectric film 140 is controlled. Therefore, the semiconductor storage apparatus 10 can write, for example, information “0” in the selected memory cell.
  • 1.5 V is applied to the word line WL connected to the selected memory cell, 1.0 V is applied to the first bit line BL, and 1.0 V is applied to the second bit line BL ⁇ . Note that, for example, 1.0 V is applied to the source line Vs.
  • the potential of the first bit line BL is transmitted to the first gate electrode 130 of the first transistor 11 via the second transistor 12 , and the first transistor 11 becomes the ON state. Furthermore, in the first transistor 11 , the threshold voltage Vt changes depending on the direction of the remanent polarization of the ferroelectric film 140 , and, for example, in a case where information “1” is stored above, Vt becomes low, and in a case where information of “0” is stored above, Vt becomes high.
  • the amount of current flowing between the second bit line BL ⁇ and the source line Vs changes depending on the direction of the remanent polarization of the ferroelectric film 140 . Therefore, it can be determined whether the information stored in the ferroelectric film 140 of the first transistor 11 is “1” or “0” according to the amount of current flowing between the second bit line BL ⁇ and the source line Vs.
  • the semiconductor storage apparatus 10 since the source or drain of the second transistor 12 is connected to the gate of the first transistor 11 that stores information, the generation of an electric field in the ferroelectric film 140 of the first transistor 11 can be controlled. Therefore, in the semiconductor storage apparatus 10 , it is possible to prevent the information stored in the unselected memory cells from being disrupted (or disturbed) when information is written in or read from the selected memory cells.
  • the leak current of the first transistor 11 along the second bit line BL ⁇ is larger than the current flowing between the second bit line BL ⁇ and the source line Vs at the time of reading information, it can be difficult to determine the information.
  • the word line WL of each memory cell can be formed independently, it is possible to control the leak current of the first transistor 11 by the word line WL.
  • the negative word line technique of applying a negative voltage to the word line WL of the unselected memory cell is applied, the leak current of the first transistor 11 can be further reduced.
  • FIGS. 19, 20, 21A, 21B, and 21C an application example of the semiconductor storage apparatus 10 according to the present embodiment will be described with reference to FIGS. 19, 20, 21A, 21B, and 21C .
  • the semiconductor storage apparatus 10 according to the present embodiment can be used, for example, as a product-sum calculation apparatus.
  • the application of the semiconductor storage apparatus 10 according to the present embodiment to a product-sum calculation apparatus will be described with reference to FIGS. 19 and 20 .
  • FIG. 19 is a schematic circuit diagram showing an equivalent circuit of a product-sum calculation apparatus.
  • FIG. 20 is a schematic diagram explaining application of the semiconductor storage apparatus 10 according to the present embodiment to a product-sum calculation apparatus.
  • a product-sum calculation apparatus 3 includes a plurality of input lines extending in a first direction (for example, a row direction), a plurality of output lines extending in a second direction (for example, a column direction) orthogonal to the first direction, and resistors 30 provided at the intersections of the input lines and the output lines.
  • the product-sum calculation apparatus 3 can perform product-sum calculation by weighting each cell with a resistance value of the resistor 30 .
  • Such a product-sum calculation apparatus 3 can implement, for example, a neural network (also called an artificial neural network) that imitates a neural network of a living body as an analog circuit.
  • a neural network also called an artificial neural network
  • the circuit element that realizes the neural network is also called a neuromorphic element.
  • the resistor 30 provided at the intersection of the input line and the output line can be configured by a resistance change memory in which the resistance value can be overwritten to reflect the learning result. Since the semiconductor storage apparatus 10 according to the present embodiment is a nonvolatile resistance change memory capable of changing the channel resistance of the first transistor 11 , it can be applied as the resistor 30 constituting each cell of the product-sum calculation apparatus 3 .
  • the source or drain of the first transistor 11 corresponds to the input line or the output line.
  • the gate of the second transistor 12 corresponds to a first selection line SL 1 for selecting a cell, and the other of the source and the drain of the second transistor 12 corresponds to a second selection line SL 2 for selecting a cell.
  • Table 2 is a table showing an example of voltages (unit: V) applied to each wiring in the write operation and the calculation operation in a case where the semiconductor storage apparatus 10 is applied to the product-sum calculation apparatus 3 .
  • the first selection line, the second selection line, and the input line of the selected cell are described as SSL1, SSL2, and SIN, respectively. Furthermore, the first selection line, the second selection line, and the input line of the unselected cell are described as USL1, USL2, and UIN, respectively. Moreover, the output line is described as OUT.
  • the potential of the second selection line SL 2 is transmitted to the first gate electrode 130 of the first transistor 11 via the second transistor 12 , which is in the ON state. Furthermore, the potential of the input line IN is transmitted to the source or drain region 151 of the first transistor 11 . Therefore, an external electric field having a high potential on the first gate electrode 130 side is generated in the ferroelectric film 140 of the first transistor 11 , and the polarization state of the ferroelectric film 140 is controlled. With this arrangement, for example, information “1” can be written in the cell configured by the semiconductor storage apparatus 10 .
  • the potential of the second selection line SL 2 is transmitted to the first gate electrode 130 of the first transistor 11 via the second transistor 12 , which is in the ON state. Furthermore, the potential of the input line IN is transmitted to the source or drain region 151 of the first transistor 11 . Therefore, an external electric field having a low potential on the first gate electrode 130 side is generated in the ferroelectric film 140 of the first transistor 11 , and the polarization state of the ferroelectric film 140 is controlled. With this arrangement, for example, information “0” can be written in the cell configured by the semiconductor storage apparatus 10 .
  • the semiconductor storage apparatus 10 can prevent the occurrence of Disturb (Write Disturb) in the unselected cells.
  • 1.5 V is applied to the first selection line SL 1 connected to the selected cell and 1.0 V is applied to the second selection line SL 2 . Furthermore, 1.0 V is applied to the input line IN.
  • the potential of the second selection line SL 2 is transmitted to the first gate electrode 130 of the first transistor 11 via the second transistor 12 , which is in the ON state, and the first transistor 11 becomes the ON state.
  • the threshold voltage Vt changes depending on the direction of the remanent polarization of the ferroelectric film 140 , and, for example, in a case where information “1” is stored above, Vt becomes low, and in a case where information of “0” is stored above, Vt becomes high. Therefore, the product-sum calculation apparatus can obtain the calculation result according to the data stored in the semiconductor storage apparatus 10 by the amount of current (or resistance value) flowing between the input line IN and the output line OUT.
  • the semiconductor storage apparatus 10 can prevent the occurrence of Disturb (Read Disturb) in the unselected cells.
  • the semiconductor storage apparatus 10 can be mounted in a circuit included in various pieces of electronic equipment.
  • FIGS. 21A, 21B, and 21C an example of the electronic equipment in which such a semiconductor storage apparatus 10 is mounted will be described.
  • FIGS. 21A, 21B, and 21C are external views showing an example of electronic equipment in which the semiconductor storage apparatus 10 is mounted.
  • the electronic equipment in which the semiconductor storage apparatus 10 is mounted may be electronic equipment such as a smartphone.
  • a smartphone 900 includes a display unit 901 that displays various types of information, and an operation unit 903 that includes buttons and the like for receiving an operation input by the user.
  • the semiconductor storage apparatus 10 described above may be provided in the circuit mounted on the smartphone 900 .
  • the electronic equipment in which the semiconductor storage apparatus 10 is mounted may be electronic equipment such as a digital camera.
  • a digital camera 910 includes a main body (camera body) 911 , a replaceable lens unit 913 , a grip portion 915 held by the user at the time of capturing, and a monitor unit 917 for displaying various types of information, and an electronic view finder (EVF) 919 for displaying a through image observed by the user at the time of capturing.
  • FIG. 21B is an external view of the digital camera 910 viewed from the front (that is, the subject side)
  • FIG. 21C is an external view of the digital camera 910 viewed from the rear (that is, the capturer side).
  • the semiconductor storage apparatus 10 described above may be provided in the circuit mounted on the digital camera 910 .
  • the electronic equipment in which the semiconductor storage apparatus 10 is mounted is not limited to the above example.
  • the electronic equipment in which the semiconductor storage apparatus 10 is mounted may be electronic equipment of any field. Examples of such electronic equipment include, for example, eyeglass-type wearable devices, head mounted displays (HMDs), television apparatuses, electronic books, personal digital assistants (PDAs), notebook personal computers, video cameras, game devices, and the like.
  • HMDs head mounted displays
  • PDAs personal digital assistants
  • notebook personal computers notebook personal computers, video cameras, game devices, and the like.
  • a semiconductor storage apparatus including:
  • a first transistor including a first gate electrode via a ferroelectric film on an activation region including source or drain regions;
  • a second transistor including source or drain regions in an activation layer provided on the first gate electrode and a second gate electrode on the activation layer via an insulating film.
  • the semiconductor storage apparatus in which the activation region is provided on a semiconductor substrate so as to extend in a first direction.
  • the semiconductor storage apparatus in which the activation layer includes a semiconductor material.
  • the semiconductor storage apparatus in which the first gate electrode is provided so as to extend in a second direction orthogonal to the first direction.
  • the semiconductor storage apparatus in which the second gate electrode is provided so as to extend in the first direction.
  • one of the source or drain regions of the first transistor is electrically connected to a source line extending in the second direction
  • Another of the source or drain regions of the first transistor is electrically connected to a second bit line extending in the first direction.
  • one of the source or drain regions of the second transistor is electrically connected to the first gate electrode
  • Another of the source or drain regions of the second transistor is electrically connected to a first bit line extending in the second direction.
  • the source or drain regions of the first transistor are provided in the activation region on both sides of the first gate electrode, and
  • the source or drain regions of the second transistor are provided in the activation layer on both sides of the second gate electrode.
  • the semiconductor storage apparatus according to any one of (2) to (8), in which the activation layer is provided on the first gate electrode and the semiconductor substrate along an outer shape of the first gate electrode and the semiconductor substrate.
  • the semiconductor storage apparatus according to any one of (2) to (9), in which the second gate electrode is provided on the activation layer and the semiconductor substrate along an outer shape of the activation layer and the semiconductor substrate via the insulating film.
  • each of the source or drain regions of the first transistor and the second transistor is provided as a same conductivity type region.
  • the semiconductor storage apparatus according to any one of (1) to (11), in which the second transistor is provided as a thin film transistor.
  • the semiconductor storage apparatus according to any one of (1) to (12), in which a plurality of sets of the first transistor and the second transistor is provided by a repetition of stacking.
  • a product-sum calculation apparatus including:
  • a first transistor including a first gate electrode via a ferroelectric film on an activation region including source or drain regions;
  • a second transistor including source or drain regions in an activation layer provided on the first gate electrode and a second gate electrode on the activation layer via an insulating film.
  • Electronic equipment including:
  • a semiconductor storage apparatus including:
  • a first transistor including a first gate electrode via a ferroelectric film on an activation region including source or drain regions;
  • a second transistor including source or drain regions in an activation layer provided on the first gate electrode and a second gate electrode on the activation layer via an insulating film.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Thin Film Transistor (AREA)
  • Dram (AREA)
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JP2018069390A JP2019179885A (ja) 2018-03-30 2018-03-30 半導体記憶装置、積和演算装置及び電子機器
PCT/JP2019/007412 WO2019187908A1 (ja) 2018-03-30 2019-02-27 半導体記憶装置、積和演算装置及び電子機器

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WO2019187908A1 (ja) 2019-10-03
TWI802663B (zh) 2023-05-21

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