TWI810422B - 用於製造供用於前側影像感測器之基材的方法 - Google Patents
用於製造供用於前側影像感測器之基材的方法 Download PDFInfo
- Publication number
- TWI810422B TWI810422B TW108147236A TW108147236A TWI810422B TW I810422 B TWI810422 B TW I810422B TW 108147236 A TW108147236 A TW 108147236A TW 108147236 A TW108147236 A TW 108147236A TW I810422 B TWI810422 B TW I810422B
- Authority
- TW
- Taiwan
- Prior art keywords
- layer
- substrate
- semiconductor layer
- carrier substrate
- transferred
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 124
- 238000000034 method Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 claims abstract description 43
- 150000002500 ions Chemical class 0.000 claims abstract description 18
- 238000002513 implantation Methods 0.000 claims abstract description 11
- 239000002184 metal Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 238000010438 heat treatment Methods 0.000 claims description 17
- 239000007789 gas Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 239000001307 helium Substances 0.000 claims description 5
- 229910052734 helium Inorganic materials 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 239000007769 metal material Substances 0.000 claims description 3
- -1 helium ion Chemical class 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 23
- 229910052802 copper Inorganic materials 0.000 description 13
- 239000010949 copper Substances 0.000 description 13
- 239000000463 material Substances 0.000 description 8
- 238000005259 measurement Methods 0.000 description 8
- 238000000407 epitaxy Methods 0.000 description 7
- 238000004627 transmission electron microscopy Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 239000002244 precipitate Substances 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004381 surface treatment Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000010023 transfer printing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3223—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering using cavities formed by hydrogen or noble gas ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/1892—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof methods involving the use of temporary, removable substrates
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Electromagnetism (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Facsimile Heads (AREA)
- Recrystallisation Techniques (AREA)
Abstract
本發明係關於一種用於製造供用於前側影像感測器之基材的方法,其包含:
提供一供體基材,其包含待轉印之一半導體層;
提供一半導體載體基材;
將該供體基材接合至該載體基材,一電氣絕緣層係位於接合界面處;
將該半導體層轉印至該載體基材;
使氣體離子穿過經轉印半導體層及該電氣絕緣層植入至該載體基材中;
在該植入之後,在該經轉印半導體層之頂部上磊晶生長一額外半導體層。
Description
發明領域
本發明係關於一種用於製造供用於前側影像感測器之基材的方法。
發明背景
絕緣體上半導體結構,且特定而言絕緣體上矽(SOI)基材,為用於製造前側影像感測器之有利基材。
SOI基材自其背面至其正面具有以下各者:由矽製成之載體基材,其在一定程度上經摻雜;氧化矽層,其被稱作「內埋氧化物層」(常常由首字母縮寫「BOX」指代);以及被稱作作用矽層之層,其具有可能不同於載體基材之摻雜的摻雜。光電二極體之矩陣陣列配置於作用層中,各光電二極體界定影像感測器之一像素。
在一些應用中,將內埋氧化物層選擇為相對較薄(亦即,厚度小於100 nm,且特定而言,介於20 nm與50 nm之間),以便藉由允許經由背面對像素加偏壓來起到電容器之介電質的作用。載體基材之位於內埋氧化物層下方的部分經偏壓至不同於作用層之電壓的電壓,此允許介電層與作用層之間的界面鈍化。待施加至載體基材之位於內埋氧化物層下方之部分的電壓取決於此層之厚度。待施加之電位差與內埋氧化物層之厚度成比例:內埋氧化物層愈薄,待施加之電位差愈小。
此內埋氧化物層之另一功能為防止由於在行進通過各像素期間未被吸收之光子在載體基材中重組而產生寄生信號(串擾防止),其中應理解,取決於所選擇厚度,內埋氧化物層相對於入射光子為僅部分反射及/或吸收的。
用於製造影像感測器之方法的一個缺點為其對金屬污染之敏感度。具體而言,SOI基材本身及像素二者可在其製造方法期間曝露於金屬。此曝露尤其導致在作用層內存在金屬原子。然而,甚至在低濃度下,金屬原子,特定而言銅原子,可導致不可接受的影像感測器效能損失。具體而言,金屬原子能夠與由俘獲於像素中之光子產生的電荷相互作用,且不利地影響其收集效能。
為了克服此缺點,已知實務上形成用於捕獲SOI基材內之金屬原子的層。
文件US 6,083,324因此描述藉由離子植入氣體物種及接著進行適合於由所植入離子形成微泡或沈澱物之熱處理來在SOI基材之作用層中形成捕獲層。此等微泡或沈澱物形成金屬原子之捕獲位點。然而,此捕獲層由於其形成於像素中之空腔及界面而可能干擾光子穿過像素之軌跡,且不利地影響影像感測器之電氣效能。
文件US 2010/0090303描述在載體基材中形成捕獲層。更具體而言,當使用智慧Cut™層轉印技術形成SOI基材時,用於製造SOI基材之方法包含以下步驟:
- 提供矽供體基材,其由意欲形成BOX之氧化矽層覆蓋且包含限定薄矽層之弱化區;
- 提供載體基材,其中已藉由離子植入形成捕獲層;
- 經由氧化物層接合供體基材與載體基材;
- 沿著弱化區拆離供體基材,以便將薄矽及氧化物層轉印至載體基材;
- 在經轉印薄層之頂部上磊晶生長額外矽層,直至已獲得影像感測器之作用層的所要厚度。
然而,若內埋氧化物層極薄,則出於形成捕獲層之目的而已經歷離子植入的載體基材之表面狀態的品質不足以提供良好接合,其為此方法之顯著缺點,尤其在接合薄氧化物之情況下,諸如針對近紅外線前側影像感測器之彼等氧化物。
發明概要
因此,仍需要在用於形成前側影像感測器之絕緣體上半導體結構之載體基材中形成捕獲區(亦即,吸氣區),同時保證作用層與載體基材之間的良好黏著。
為此目的,本發明提出一種用於製造供用於前側影像感測器之基材的方法,其包含:
提供供體基材,其包含待轉印之半導體層;
提供半導體載體基材;
將供體基材接合至載體基材,電氣絕緣層係位於接合界面處;
將半導體層轉印至載體基材;
經由經轉印半導體層及電氣絕緣層將氣體離子植入至載體基材中;
在該植入之後,在經轉印半導體層之頂部上磊晶生長額外半導體層。
有利地,該方法包含在適合於使得自所植入氣體離子產生空腔之溫度下進行熱處理,該等空腔形成用於捕獲載體基材中之金屬原子的層。
根據一個實施例,該熱處理係在額外半導體層之磊晶生長期間進行。
較佳地,捕獲層(亦即,吸氣層)中之空腔密度高於或等於1015
個空腔/立方公分。
根據一個實施例,各半導體層為矽層。
根據一個實施例,該電氣絕緣層為氧化矽層。
替代地,該電氣絕緣層由介電及/或金屬材料之堆疊組成。
較佳地,電氣絕緣層之厚度介於5 nm與400 nm之間,且較佳介於30 nm與150 nm之間。
較佳地,該等氣體離子包含氦離子。
根據一個實施例,半導體層之轉印包含:
- 在供體基材中形成弱化區以便界定待轉印之該半導體層;
- 在接合之後,沿著弱化區拆離供體基材。
本發明亦係關於一種用於製造前側影像感測器之方法,其包含:使用如上文所描述之方法製造基材,將經轉印半導體層及額外半導體層一起形成該影像感測器之作用層;以及在該作用層中形成多個電氣隔離溝槽以便界定多個像素。
較佳實施例之詳細說明
圖1A說明根據本發明之一個實施例的用於影像感測器之SOI基材。
該基材自其背面至其正面依次包含載體基材1、電氣絕緣層2及被稱作作用層之半導體層3,該半導體層意欲用於形成影像感測器之像素。
用於捕獲金屬原子之層4 (亦即,吸氣層)配置於載體基材1中之某一深度處,其不一定與電氣絕緣層2接觸。如下文將詳細地描述,該層4包含在熱處理之作用下自植入至載體基材中之氣體離子產生的空腔。該捕獲層4中之空腔的密度有利地高於或等於1015
個空腔/立方公分。該等空腔使得能夠俘獲存在於SOI基材中電氣絕緣層2附近之金屬原子,該等金屬原子可不利地影響感測器之正確操作。此等原子最初可存在於載體基材1及/或作用層3中,且在熱處理之作用下遍及SOI基材擴散直至到達捕獲層4,在該捕獲層處其被俘獲。
載體基材有利地為矽基材,特定而言為單晶矽基材。
電氣絕緣層2可為氧化矽層,其在絕緣體上矽基材之領域中為習知絕緣體。
替代地,電氣絕緣層可由各種介電及/或金屬材料之堆疊組成,諸如所謂的「ONO」,亦即,氧化物-氮化物-氧化物堆疊。有利地選擇該堆疊之構成材料以便相較於具有相同總厚度之氧化矽層,增加電氣絕緣層在紅外線中之反射率。較佳地,金屬層囊封於二個介電層之間,因此防止作用層之任何金屬污染。此使得有可能避免在作用層與電氣絕緣層之間的界面處之電氣缺陷的產生及在作用層之半導體材料與影像感測器之金屬組份之間的重組,該等金屬組份可摻雜作用層。
根據圖1B中所說明之一個特定實施例,電氣絕緣層2在二個氧化矽層21、23之間包含氮化矽層22。配置於載體基材1側上之層21的厚度介於50 nm與500 nm之間,配置於作用層3側上之層23的厚度介於5 nm與50 nm之間,且層22之厚度介於10 nm與100 nm之間。此電氣絕緣層具有如下優點:相比圖1A之基材的相同厚度之氧化矽層,更好地反射透射穿過作用層3之光子。
特別有利地,無論由一種抑或數種材料組成,電氣絕緣層2皆為薄的,亦即,其厚度介於5 nm與400 nm之間且較佳介於30 nm與150 nm之間。此層不形成對金屬(特定而言,銅)原子之擴散的阻障。因此,不必如在文件US 2010/0090303中局部破壞電氣絕緣層以便允許原子穿過。
作用層有利地為單晶的。如圖1中示意性地展示,作用層3係藉由堆疊第一層3a及額外層3b而形成,層3b係藉由在層3a之頂部上的磊晶而製造,該層3b接著用作晶種層。層3a及3b之材料有利地展現類似的晶格參數及熱膨脹係數,此使得有可能在層3b磊晶生長時其內最少地形成晶體缺陷。根據一個較佳實施例,層3a及3b由通常為矽或矽鍺之相同材料組成。層3a及/或3b可潛在地經摻雜。
層3之厚度通常大於或等於1 µm。
現將參看圖2至圖5描述用於基於智慧Cut™方法製造圖1A之基材的方法。
參看圖2,提供由電氣絕緣層2覆蓋之供體基材30。該電氣絕緣層可藉由熱氧化供體基材之材料及/或藉由沈積一或多個介電及/或金屬層而形成。藉由將原子物種(由箭頭表示)植入至供體基材30中而形成限定待轉印之半導體層3a的弱化區。出於此目的而植入之原子物種有利地包含氫及/或氦。
參看圖3,將供體基材30接合至載體基材1,電氣絕緣層2位於接合界面處。
參看圖4,沿著弱化區31拆離供體基材30,以便將半導體層3a轉印至載體基材1。
參看圖5,氣體(例如,氦)離子穿過半導體層3a及電氣絕緣層2植入至載體基材1中。熟習此項技術者能夠定義植入參數,特定而言為劑量及植入能量,以便將該等氣體離子40定位於載體基材1之厚度上的層中。作為指示,介於1E16個原子/平方公分與5E17個原子/平方公分之間的劑量適合於獲得至少10E15個空腔/立方公分之空腔密度。植入能量通常介於幾keV與120 keV之間。熟習此項技術者將根據離子必須穿過之層的厚度來選擇合適能量,以使該等離子定位於電氣絕緣層下方之載體基材中。
接下來進行熱處理以自所植入氣體離子產生空腔,以便形成用於捕獲金屬原子之層。一般而言,此處理涉及將基材加熱至介於850℃與1200℃之間的溫度持續介於30分鐘與180分鐘之間的時間。此熱處理可作為方法中之特定步驟來進行。然而,有利地在方法中使用另一步驟之熱預算,例如,表面處理SOI基材(諸如,用於平滑或用於修復缺陷之退火)之步驟或為了在經轉印層3a之頂部上生長額外半導體層3b而進行的磊晶步驟。
作為上文所描述之智慧Cut™方法的替代例,可在將供體基材接合至載體基材之後藉由將供體基材自其與接合界面相對之面薄化(例如,藉由蝕刻)直至獲得經轉印半導體層之所要厚度來轉印半導體層。在此狀況下,不必形成弱化區。
在將供體基材接合至載體基材之後而非之前(如描述於文件US 2010/0090303中)形成捕獲層使得有可能確保待接合之表面具有最佳品質,且因此二個基材之間的黏著良好,即使電氣絕緣層為薄的亦如此。另外,在額外半導體層之磊晶之前植入氣體離子使得有可能最小化植入能量且避免破壞作用層。
參看圖6,藉由經轉印層3a之頂部上的磊晶來生長額外半導體層3b,直至獲得作用層3之所要厚度。如上文所提及,此磊晶之熱預算可用以產生形成捕獲層4之空腔。接下來,形成穿過作用層3向下至電氣絕緣層2中之溝槽,且用介電材料填充該等溝槽5以便電氣隔離影像感測器之像素。
實驗結果
已產生諸如圖5中所說明之SOI基材,且已藉由自所植入氣體離子產生空腔而形成捕獲層,空腔係藉由將該等SOI基材中之一些加熱至950℃之溫度持續40分鐘而產生(參見圖7)。
該等基材接著經歷熱處理,包括用於捕獲金屬原子之層的SOI基材可經歷該等熱處理,以便檢查甚至在已經歷具有高熱預算之熱處理之後,捕獲層亦穩定且仍操作(參見圖8)。假定在1100℃下持續二個小時之處理的熱預算為允許保留空腔層之捕獲性質的最大熱預算。此熱預算與表面處理步驟及(任擇地)磊晶相容。
圖7展示在已進行用於產生空腔之熱處理之後由透射電子顯微法產生的圖5之基材的截面之影像(右側影像為左側影像之放大)。在載體基材1內,可見配置於層4中之空腔,該層形成用於捕獲金屬原子之層。在所說明之實例中,層4之厚度為179 nm且其內埋於載體基材1與電氣絕緣層2之間的界面下方205 nm之深度處。
圖8為相對於圖7之影像,在額外熱處理已應用於基材之後由透射電子顯微法產生的圖5之基材的截面之影像,該熱處理係在高達1100℃之溫度下進行持續少於或等於二小時之時間。在載體基材1之厚度上,在氣體離子之植入深度處,可見配置於層4中之空腔,該層形成用於捕獲金屬原子之層。
圖9展示藉由次級離子質譜分析(SIMS)獲取之圖5之基材中的銅濃度之量測,其疊加於由透射電子顯微法產生之該基材的截面之影像上。為進行此量測,將銅層沈積於半導體層3a之頂部上且進行熱處理(800℃持續二小時)以使銅原子擴散至基材中。出於證實之目的,選擇此熱處理以在考慮銅在矽及氧化矽中之物理擴散性質的情況下確保此元素完全分散至材料中。此量測因此反映銅原子穿過電氣絕緣層2且被捕獲層4捕獲之能力。因此,當銅原子之濃度在層3a中為約1.1E11個原子/立方公分且在電氣絕緣層中為約1.8E9個原子/立方公分時,曲線展示在層4處具有銅原子濃度之峰值,為約2.3E13個原子/立方公分。在層4下方之銅原子的濃度極低。
圖10及圖11分別展示在不具有及具有捕獲層4之情況下類似於圖5之基材的基材內之銅濃度的SIMS量測。為進行此量測,將銅層沈積於載體基材1之背面上且進行熱處理(800℃持續二小時)以使銅原子擴散至基材中。在圖10 (無捕獲層)之狀況下,在載體基材1中電氣絕緣層下方觀察到銅原子之高濃度(峰值P1)且在經轉印層中該層之自由表面附近觀察到銅原子之高濃度(峰值P2)。在圖11 (存在根據本發明之捕獲層)之狀況下,觀察到銅原子濃度峰值P3位於捕獲層中。
REFERENCES
US 6,083,324
US 2010/0090303
1:半導體載體基材
2:電氣絕緣層
3:半導體層/作用層
3a:第一層/半導體層/經轉印層
3b:額外半導體層
4:捕獲層
5:電氣隔離溝槽
21,23:氧化矽層
22:氮化矽層
30:供體基材
31:弱化區
40:氣體離子
P1,P2:峰值
P3:銅原子濃度峰值
本發明之其他特徵及優點將參看附圖自以下實施方式顯現,在附圖中:
- 圖1A為根據本發明之一個實施例的用於影像感測器之SOI基材的截面圖;
- 圖1B為根據圖1A之一個變體的基材之截面圖;
- 圖2示意性地說明將原子物種植入至供體基材中以便在供體基材處形成弱化區,從而限定待轉印之半導體層;
- 圖3示意性地說明將圖2之弱化供體基材接合至載體基材;
- 圖4示意性地說明將半導體層轉印至載體基材以便形成SOI結構;
- 圖5示意性地說明將氦植入至圖4之SOI結構中;
- 圖6說明在圖1之基材中形成電氣隔離溝槽以便單體化影像感測器之各像素之後獲得的基材,該基材預先已經歷再磊晶步驟;
- 圖7展示由透射電子顯微法產生之圖5的基材之截面的影像(右側影像為左側影像之放大);
- 圖8為相對於圖7之影像的由透射電子顯微法產生之在額外熱處理已應用於基材之後的圖5之基材的截面之影像;
- 圖9展示藉由次級離子質譜分析(SIMS)進行之銅濃度的量測,其說明銅在圖5之基材內的擴散,該量測疊加於由透射電子顯微法產生之該基材之截面的影像上;
- 圖10展示銅濃度之SIMS量測,其說明銅在基材內之擴散,該基材類似於圖5之基材但不具有捕獲層;
- 圖11展示銅濃度之SIMS量測,其說明銅在圖5之基材內的擴散。
為了使圖式更清晰,各種層未按比例繪製。自一個圖至下一圖相同之參考符號已用以參考相同或執行相同功能之元件。
1:半導體載體基材
2:電氣絕緣層
3:半導體層/作用層
3a:第一層/半導體層/經轉印層
3b:額外半導體層
4:捕獲層
Claims (11)
- 一種用於製造供用於前側影像感測器之基材的方法,其包含:提供一供體基材,其包含待轉印之一半導體層;提供一半導體載體基材;將該供體基材接合至該載體基材,一電氣絕緣層係位於接合界面處;將該半導體層轉印至該載體基材;使氣體離子穿過經轉印半導體層及該電氣絕緣層植入至該載體基材中;在該植入之後,在該經轉印半導體層之頂部上磊晶生長一額外半導體層。
- 如請求項1之方法,其包含在適合於使得自所植入氣體離子產生空腔之一溫度下進行的一熱處理,該等空腔形成用於捕獲該載體基材中之金屬原子的一層。
- 如請求項2之方法,其中該熱處理係在該額外半導體層之磊晶生長期間進行。
- 如請求項2及3中任一項之方法,其中捕獲層中之空腔密度高於或等於1015個空腔/立方公分。
- 如請求項1至3中任一項之方法,其中各半導體層為一矽層。
- 如請求項1至3中任一項之方法,其中該電氣絕緣層為一氧化矽層。
- 如請求項1至3中任一項之方法,其中該電氣絕緣層由介電及/或金屬材料之一堆疊組成。
- 如請求項1至3中任一項之方法,其中該電氣絕緣層之厚度介於5nm與400nm之間,且較佳介於30nm與150nm之間。
- 如請求項1至3中任一項之方法,其中該等氣體離子包含氦 離子。
- 如請求項1至3中任一項之方法,其中該半導體層之該轉印包含:在該供體基材中形成一弱化區以便界定待轉印之該半導體層;在接合之後,沿著該弱化區拆離該供體基材。
- 一種用於製造前側影像感測器之方法,其包含:使用如請求項1至10中任一項之方法製造一基材,將該經轉印半導體層及該額外半導體層一起形成該影像感測器之一作用層;以及在該作用層中形成多個電氣隔離溝槽以便界定多個像素。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1874134A FR3091000B1 (fr) | 2018-12-24 | 2018-12-24 | Procede de fabrication d’un substrat pour un capteur d’image de type face avant |
FR1874134 | 2018-12-24 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW202101545A TW202101545A (zh) | 2021-01-01 |
TWI810422B true TWI810422B (zh) | 2023-08-01 |
Family
ID=67956837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW108147236A TWI810422B (zh) | 2018-12-24 | 2019-12-23 | 用於製造供用於前側影像感測器之基材的方法 |
Country Status (10)
Country | Link |
---|---|
US (1) | US20220059603A1 (zh) |
EP (1) | EP3903341B1 (zh) |
JP (1) | JP7392243B2 (zh) |
KR (1) | KR20210104876A (zh) |
CN (1) | CN113228248A (zh) |
FR (1) | FR3091000B1 (zh) |
IL (1) | IL284308B2 (zh) |
SG (1) | SG11202106829WA (zh) |
TW (1) | TWI810422B (zh) |
WO (1) | WO2020136344A1 (zh) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6083324A (en) * | 1998-02-19 | 2000-07-04 | Silicon Genesis Corporation | Gettering technique for silicon-on-insulator wafers |
TW201218365A (en) * | 2010-10-01 | 2012-05-01 | Omnivision Tech Inc | Method of damage-free impurity doping for CMOS image sensors |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3171322B2 (ja) * | 1997-03-11 | 2001-05-28 | 日本電気株式会社 | Soi基板およびその製造方法 |
US6548382B1 (en) * | 1997-07-18 | 2003-04-15 | Silicon Genesis Corporation | Gettering technique for wafers made using a controlled cleaving process |
DE10131249A1 (de) * | 2001-06-28 | 2002-05-23 | Wacker Siltronic Halbleitermat | Verfahren zur Herstellung eines Films oder einer Schicht aus halbleitendem Material |
JP4910275B2 (ja) * | 2004-09-21 | 2012-04-04 | ソニー株式会社 | 固体撮像素子及びその製造方法 |
FR2890489B1 (fr) * | 2005-09-08 | 2008-03-07 | Soitec Silicon On Insulator | Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant |
US20080070340A1 (en) * | 2006-09-14 | 2008-03-20 | Nicholas Francis Borrelli | Image sensor using thin-film SOI |
JP2010062452A (ja) * | 2008-09-05 | 2010-03-18 | Sumco Corp | 半導体基板の製造方法 |
JP2010114409A (ja) | 2008-10-10 | 2010-05-20 | Sony Corp | Soi基板とその製造方法、固体撮像装置とその製造方法、および撮像装置 |
FR2938119B1 (fr) * | 2008-10-30 | 2011-04-22 | Soitec Silicon On Insulator | Procede de detachement de couches semi-conductrices a basse temperature |
JP5420968B2 (ja) * | 2009-05-07 | 2014-02-19 | 信越化学工業株式会社 | 貼り合わせウェーハの製造方法 |
JP2011014673A (ja) * | 2009-07-01 | 2011-01-20 | Panasonic Corp | Soi基板とその製造方法およびそれを用いた固体撮像装置の製造方法 |
FR2974944B1 (fr) * | 2011-05-02 | 2013-06-14 | Commissariat Energie Atomique | Procédé de formation d'une fracture dans un matériau |
FR2983342B1 (fr) * | 2011-11-30 | 2016-05-20 | Soitec Silicon On Insulator | Procede de fabrication d'une heterostructure limitant la formation de defauts et heterostructure ainsi obtenue |
JP5696081B2 (ja) * | 2012-03-23 | 2015-04-08 | 株式会社東芝 | 固体撮像装置 |
US8736006B1 (en) * | 2013-03-14 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside structure for a BSI image sensor device |
JP6650463B2 (ja) * | 2014-11-18 | 2020-02-19 | グローバルウェーハズ カンパニー リミテッドGlobalWafers Co.,Ltd. | 電荷トラップ層を備えた高抵抗率の半導体・オン・インシュレーターウェハーの製造方法 |
FR3061802B1 (fr) * | 2017-01-11 | 2019-08-16 | Soitec | Substrat pour capteur d'image de type face avant et procede de fabrication d'un tel substrat |
EP3410486B1 (en) * | 2017-06-02 | 2022-08-24 | ams AG | Resonant cavity enhanced image sensor |
CN108598105B (zh) * | 2018-06-26 | 2020-10-13 | 矽照光电(厦门)有限公司 | 一种柔性有源彩色显示模块生产方法 |
-
2018
- 2018-12-24 FR FR1874134A patent/FR3091000B1/fr active Active
-
2019
- 2019-12-23 WO PCT/FR2019/053281 patent/WO2020136344A1/fr unknown
- 2019-12-23 KR KR1020217023211A patent/KR20210104876A/ko unknown
- 2019-12-23 TW TW108147236A patent/TWI810422B/zh active
- 2019-12-23 US US17/418,148 patent/US20220059603A1/en active Pending
- 2019-12-23 IL IL284308A patent/IL284308B2/en unknown
- 2019-12-23 EP EP19848983.3A patent/EP3903341B1/fr active Active
- 2019-12-23 JP JP2021535055A patent/JP7392243B2/ja active Active
- 2019-12-23 SG SG11202106829WA patent/SG11202106829WA/en unknown
- 2019-12-23 CN CN201980085606.0A patent/CN113228248A/zh active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6083324A (en) * | 1998-02-19 | 2000-07-04 | Silicon Genesis Corporation | Gettering technique for silicon-on-insulator wafers |
TW201218365A (en) * | 2010-10-01 | 2012-05-01 | Omnivision Tech Inc | Method of damage-free impurity doping for CMOS image sensors |
Also Published As
Publication number | Publication date |
---|---|
IL284308B2 (en) | 2024-03-01 |
TW202101545A (zh) | 2021-01-01 |
KR20210104876A (ko) | 2021-08-25 |
FR3091000B1 (fr) | 2020-12-04 |
EP3903341B1 (fr) | 2023-01-18 |
IL284308A (en) | 2021-08-31 |
WO2020136344A1 (fr) | 2020-07-02 |
SG11202106829WA (en) | 2021-07-29 |
US20220059603A1 (en) | 2022-02-24 |
IL284308B1 (en) | 2023-11-01 |
CN113228248A (zh) | 2021-08-06 |
JP2022515096A (ja) | 2022-02-17 |
EP3903341A1 (fr) | 2021-11-03 |
JP7392243B2 (ja) | 2023-12-06 |
FR3091000A1 (fr) | 2020-06-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7238583B2 (en) | Back-illuminated imaging device and method of fabricating same | |
US5910672A (en) | Semiconductor device and method of manufacturing the same | |
US6437404B1 (en) | Semiconductor-on-insulator transistor with recessed source and drain | |
US20110031576A1 (en) | Solid-state imaging device and manufacturing method thereof | |
US11552123B2 (en) | Front-side type image sensors | |
TWI785385B (zh) | 用於抑制暗電流的淺溝槽隔離(sti)結構及形成方法 | |
US20020089032A1 (en) | Processing method for forming dislocation-free silicon-on-insulator substrate prepared by implantation of oxygen | |
US5986311A (en) | Semiconductor device having recrystallized source/drain regions | |
US5270221A (en) | Method of fabricating high quantum efficiency solid state sensors | |
JP5499455B2 (ja) | SOI(Silicononinsulator)構造の半導体装置およびその製造方法 | |
JP2007318102A (ja) | Soiウエーハの製造方法 | |
JP2006324688A (ja) | 多層ウエハ用ゲッタ及びその作製法 | |
US20050217566A1 (en) | Method for producing one or more monocrystalline layers, each with a different lattice structure, on one plane of a series of layers | |
US6566680B1 (en) | Semiconductor-on-insulator (SOI) tunneling junction transistor | |
TWI810422B (zh) | 用於製造供用於前側影像感測器之基材的方法 | |
TW201841213A (zh) | 用於前側型成像器之基材及製造該基材之方法 | |
JP5446388B2 (ja) | 集積化半導体装置の製造方法 | |
TWI761422B (zh) | 用於前側型成像器之基材及製造該基材之方法 | |
US7285452B2 (en) | Method to selectively form regions having differing properties and structure | |
KR19990088300A (ko) | Soi-반도체장치및그것의제조방법 | |
EP2281306A1 (en) | Method for electronically pinning a back surface of a back-illuminated imager fabricated on a utsoi wafer | |
KR102666552B1 (ko) | 전면 이미지 센서 및 이러한 이미지 센서를 제조하기 위한 프로세스 | |
US20070152282A1 (en) | Semiconductor Device and Fabrication Method Thereof | |
TW202135146A (zh) | 用於製作感光元件之方法 | |
JPH05160090A (ja) | 半導体基板の製造方法 |