TWI789561B - Dc-dc converter and time signal generator thereof - Google Patents

Dc-dc converter and time signal generator thereof Download PDF

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TWI789561B
TWI789561B TW108142759A TW108142759A TWI789561B TW I789561 B TWI789561 B TW I789561B TW 108142759 A TW108142759 A TW 108142759A TW 108142759 A TW108142759 A TW 108142759A TW I789561 B TWI789561 B TW I789561B
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signal
digital
load current
output voltage
input voltage
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TW202037049A (en
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張志廉
洪偉修
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力智電子股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output

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  • Dc-Dc Converters (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)

Abstract

A DC-DC conversion circuit and a time signal generator thereof are disclosed. The time signal generator is generating a time signal for a DC-DC conversion circuit to convert an input voltage into an output voltage. The DC-DC conversion circuit is coupled to a loading and a loading current flowing through the loading. The time signal generator includes an analog-to-digital converting unit, a compensation unit, a counting unit, a comparing unit and a logic unit. The analog-to-digital converting unit receives an output voltage, an input voltage and the loading current and converts them into corresponding digital signals. The compensation unit receives the digital signals and processes the digital signals to generate a compensation signal. The counting unit provides a counting signal according to a clock signal and a trigger signal. The comparing unit receives the compensation signal and the counting signal to provide a comparison signal. The logic unit receives the trigger signal and the comparison signal to provide the time signal.

Description

直流-直流轉換電路及其時間信號產生器 DC-DC Conversion Circuit and Its Time Signal Generator

本發明與直流對直流轉換電路有關，特別是關於一種直流對直流轉換電路及其時間信號產生器。 The present invention relates to a direct current to direct current conversion circuit, in particular to a direct current to direct current conversion circuit and a time signal generator thereof.

當具有恆定導通時間的直流對直流轉換電路運作於重載穩態時，由於其導通時間為恆定，為了抵消電路中的元件寄生電阻造成的電源轉換損耗，其提供的時間信號的關斷時間會縮短(如圖1A中的關斷時間的長度由TOFF1縮短為TOFF2所示)，開關切換週期變短，而通過輸出電感的電感電流的平均值則會變大(如圖1B中的電感電流由Iind1變為Iind2所示)。 When the DC-to-DC conversion circuit with constant on-time operates in a heavy-load steady state, since its on-time is constant, in order to offset the power conversion loss caused by the parasitic resistance of the components in the circuit, the off-time of the time signal it provides will be changed. shortened (as shown in Figure 1A, the length of the off-time is shortened from TOFF1 to TOFF2), the switching cycle becomes shorter, and the average value of the inductor current passing through the output inductor will become larger (as shown in Figure 1B, the inductor current is changed by Iind1 becomes as shown in Iind2).

然而，時間信號的週期變短，代表著直流對直流轉換電路的輸出級的開關頻率增加，導致直流對直流轉換電路運作於重載穩態時的電源轉換效率變差，此一缺點亟待克服。 However, the shortening of the period of the time signal means that the switching frequency of the output stage of the DC-DC conversion circuit increases, which leads to the deterioration of the power conversion efficiency when the DC-DC conversion circuit operates in a heavy-load steady state. This shortcoming needs to be overcome urgently.

有鑑於此，本發明提供一種直流-直流轉換電路及其時間信號產生器，以解決先前技術所述及的問題。 In view of this, the present invention provides a DC-DC conversion circuit and its timing signal generator to solve the problems mentioned in the prior art.

本發明的一較佳具體實施例為一種時間信號產生器。於此實施例中，時間信號產生器產生時間信號以使直流對直流轉換電路將輸入電壓轉換為輸出電壓。直流對直流轉換電路耦接負載，並有負載電流流經負載。時間信號產生器包括類比數位轉換單元、補償單元、計數單元、比較單元及邏輯單元。類比數位轉換單元分別接收輸出電壓、輸入電壓及負載電流，並分別轉換為數位輸入電壓信號、數位輸出電壓信號及數位負載電流信號。補償單元分別接收數位輸出電壓信號、數位輸入電壓信號及數位負載電流信號，且對數位輸出電壓信號、數位輸入電壓信號及數位負載電流信號進行運算處理，以產生補償信號。計數單元依據時脈信號與觸發信號來提供計數信號。比較單元接收補償信號與計數信號以提供比較信號。邏輯單元接收觸發信號與比較信號以提供時間信號。 A preferred embodiment of the present invention is a time signal generator. In this embodiment, the timing signal generator generates the timing signal so that the DC-DC converting circuit converts the input voltage into an output voltage. The DC-to-DC conversion circuit is coupled to a load, and a load current flows through the load. The time signal generator includes an analog-to-digital conversion unit, a compensation unit, a counting unit, a comparison unit and a logic unit. The analog-to-digital conversion unit respectively receives the output voltage, the input voltage and the load current, and converts them into digital input voltage signals, digital output voltage signals and digital load current signals respectively. The compensation unit respectively receives the digital output voltage signal, the digital input voltage signal and the digital load current signal, and performs arithmetic processing on the digital output voltage signal, the digital input voltage signal and the digital load current signal to generate the compensation signal. The counting unit provides counting signals according to the clock signal and the trigger signal. The comparison unit receives the compensation signal and the count signal to provide a comparison signal. The logic unit receives the trigger signal and the comparison signal to provide a time signal.

在本發明的一實施例中，時間信號與數位輸入電壓信號、數位輸出電壓信號及數位負載電流信號有關。 In an embodiment of the present invention, the time signal is related to the digital input voltage signal, the digital output voltage signal and the digital load current signal.

在本發明的一實施例中，於重載期間，通過負載的負載電流增加，致使與負載電流相關的數位負載電流信號增加。補償單元所產生的補償信號及比較單元所提供的比較信號亦隨之增加。 In one embodiment of the present invention, during the heavy load period, the load current through the load increases, causing the digital load current signal related to the load current to increase. The compensation signal generated by the compensation unit and the comparison signal provided by the comparison unit also increase accordingly.

在本發明的一實施例中，補償單元包括第一乘法器、第二乘法器、加法器及除法器。第一乘法器用以將數位負載電流信號乘以第一常數而得到第一乘積。第二乘法器用以將數位輸入電壓信號乘以第二常數而得到第二乘積。加法器耦接第一乘法器，用以將數位輸出電壓信號加上第 一乘積而得到總和值。除法器耦接加法器及第二乘法器，用以將總和值除以第二乘積而得到補償信號。 In an embodiment of the present invention, the compensation unit includes a first multiplier, a second multiplier, an adder and a divider. The first multiplier is used for multiplying the digital load current signal by a first constant to obtain a first product. The second multiplier is used for multiplying the digital input voltage signal by a second constant to obtain a second product. The adder is coupled to the first multiplier for adding the digital output voltage signal to the first A product to get the total value. The divider is coupled to the adder and the second multiplier, and is used for dividing the sum value by the second product to obtain the compensation signal.

在本發明的一實施例中，時間信號亦隨著總和值增加，且時間信號的增加量與數位負載電流信號的增加量有關。 In an embodiment of the present invention, the time signal also increases with the sum value, and the increase of the time signal is related to the increase of the digital load current signal.

在本發明的一實施例中，補償單元包括第一乘法器、第二乘法器、第一除法器、第二除法器及加法器。第一乘法器用以將數位負載電流信號乘以第一常數而得到第一乘積。第二乘法器用以將數位輸入電壓信號乘以第二常數而得到第二乘積。第一除法器耦接第一乘法器及第二乘法器，用以將負載電流信號除以第二乘積而得到第一商值。第二除法器耦接第二乘法器，用以將數位輸出電壓除以第二乘積而得到第二商值。加法器耦接第一除法器及第二除法器，用以相加第一商值與第二商值而得到補償信號。 In an embodiment of the present invention, the compensation unit includes a first multiplier, a second multiplier, a first divider, a second divider and an adder. The first multiplier is used for multiplying the digital load current signal by a first constant to obtain a first product. The second multiplier is used for multiplying the digital input voltage signal by a second constant to obtain a second product. The first divider is coupled to the first multiplier and the second multiplier, and is used for dividing the load current signal by the second product to obtain a first quotient. The second divider is coupled to the second multiplier, and is used for dividing the digital output voltage by the second product to obtain a second quotient. The adder is coupled to the first divider and the second divider, and is used for adding the first quotient and the second quotient to obtain the compensation signal.

本發明的另一較佳具體實施例為一種直流-直流轉換電路，將輸入電壓轉換為輸出電壓，直流-直流轉換電路耦接負載，並有負載電流流經該負載，直流-直流轉換電路包括輸出級、驅動電路、回授電路及時間信號產生器。輸出級耦接負載，接收至少一驅動信號以將輸入電壓轉換為輸出電壓。驅動電路耦接輸出級，根據時間信號產生至少一驅動信號。回授電路耦接輸出級，根據輸出電壓產生觸發信號。時間信號產生器耦接於回授電路及驅動電路之間，接收輸入電壓、輸出電壓、負載電流及觸發信號，以產生時間信號。時間信號產生器包括補償單元，分別接收與輸出電壓相關的數位輸出電壓信號、與輸入電壓相關的數位輸入電壓信號及與負載電流相關的數位負載電流信號，且對數位輸出電壓信號、數位輸入電壓 信號及數位負載電流信號進行運算處理，以產生補償信號，並根據補償信號提供時間信號。 Another preferred embodiment of the present invention is a DC-DC conversion circuit, which converts the input voltage into an output voltage. The DC-DC conversion circuit is coupled to a load, and a load current flows through the load. The DC-DC conversion circuit includes Output stage, drive circuit, feedback circuit and timing signal generator. The output stage is coupled to the load and receives at least one driving signal to convert the input voltage into an output voltage. The driving circuit is coupled to the output stage and generates at least one driving signal according to the time signal. The feedback circuit is coupled to the output stage and generates a trigger signal according to the output voltage. The timing signal generator is coupled between the feedback circuit and the driving circuit, and receives the input voltage, the output voltage, the load current and the trigger signal to generate the timing signal. The time signal generator includes a compensation unit that respectively receives a digital output voltage signal related to the output voltage, a digital input voltage signal related to the input voltage, and a digital load current signal related to the load current, and the digital output voltage signal, digital input voltage The signal and the digital load current signal are processed to generate a compensation signal, and a time signal is provided according to the compensation signal.

在本發明的另一實施例中，時間信號產生器還包括類比數位轉換單元，耦接補償單元，分別接收輸出電壓、輸入電壓及負載電流，並分別轉換為數位輸出電壓信號、數位輸入電壓信號及數位負載電流信號。 In another embodiment of the present invention, the time signal generator further includes an analog-to-digital conversion unit coupled to the compensation unit to receive the output voltage, input voltage and load current respectively, and convert them into digital output voltage signals and digital input voltage signals respectively. And digital load current signal.

在本發明的另一實施例中，時間信號與數位輸出電壓信號及數位負載電流信號有關。 In another embodiment of the present invention, the time signal is related to the digital output voltage signal and the digital load current signal.

在本發明的另一實施例中，於重載期間，流經負載的負載電流增加，致使與負載電流相關的數位負載電流信號增加，補償單元所產生的補償信號也隨之增加。 In another embodiment of the present invention, during the heavy load period, the load current flowing through the load increases, so that the digital load current signal related to the load current increases, and the compensation signal generated by the compensation unit also increases accordingly.

相較於先前技術，本發明的時間信號產生器能夠藉由與負載電流相關的補償信號來調整其提供的時間信號，因此，當直流對直流轉換電路運作於重載穩態而使得負載電流增加時，本發明的時間信號產生器時間信號所提供的時間信號的導通時間亦隨之增加，藉以維持直流對直流轉換電路的開關頻率恆定而提升直流對直流轉換電路運作於重載穩態時的電源轉換效率。 Compared with the prior art, the time signal generator of the present invention can adjust the time signal provided by the compensation signal related to the load current. Therefore, when the DC-to-DC conversion circuit operates in a heavy-load steady state, the load current increases , the conduction time of the time signal provided by the time signal generator time signal of the present invention also increases accordingly, so as to maintain the switching frequency of the DC-to-DC conversion circuit constant and improve the DC-to-DC conversion circuit when it operates in a heavy-duty steady state. power conversion efficiency.

關於本發明的優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。 The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

Ton1、Ton2:時間信號 Ton1, Ton2: time signal

Toff1、Toff2:關斷時間的長度 Toff1, Toff2: length of off time

Iind1、Iind2:電感電流 Iind1, Iind2: inductor current

2:直流對直流轉換電路 2: DC to DC conversion circuit

1:時間信號產生器 1: Time signal generator

10:類比數位轉換單元 10: Analog to digital conversion unit

11:補償單元 11: Compensation unit

12:計數單元 12: counting unit

14:比較單元 14: Comparison unit

16:邏輯單元 16: logic unit

DR:驅動電路 DR: drive circuit

OS:輸出級 OS: output stage

LD:負載 LD: load

FB:回授電路 FB: feedback circuit

CLK:時脈信號 CLK: clock signal

TR:觸發信號 TR: trigger signal

GND:接地電壓 GND: ground voltage

SVout:數位輸出電壓信號 SVout: digital output voltage signal

Vout:輸出電壓 Vout: output voltage

SVin:數位輸入電壓信號 SVin: digital input voltage signal

Vin:輸入電壓 Vin: input voltage

SIL:數位負載電流信號 SIL: digital load current signal

IL:負載電流 IL: load current

S1:補償信號 S1: Compensation signal

S2:計數信號 S2: counting signal

S3:比較信號 S3: compare signal

Ton:時間信號 Ton: time signal

DS1:第一驅動信號 DS1: the first drive signal

DS2:第二驅動信號 DS2: Second drive signal

M1:第一乘法器 M1: the first multiplier

M2:第二乘法器 M2: second multiplier

DIV:除法器 DIV: divider

DIV1:第一除法器 DIV1: first divider

DIV2:第二除法器 DIV2: second divider

ADD:加法器 ADD: adder

SUM:總和值 SUM: total value

T1、T2、T1’、T2’:導通時間的長度 T1, T2, T1', T2': length of on-time

D1、D2、D1’、D2’:時間信號的週期 D1, D2, D1', D2': period of the time signal

本發明所附圖式說明如下： 圖1A繪示習知的直流對直流轉換電路提供的脈寬調變信號的關斷時間及週期在重載穩態下會縮短的示意圖。 The accompanying drawings of the present invention are described as follows: FIG. 1A is a schematic diagram showing that the off-time and period of a PWM signal provided by a conventional DC-to-DC conversion circuit are shortened under heavy load steady state.

圖1B繪示習知的直流對直流轉換電路的電感電流的平均值在重載穩態下會變大且其週期會變短的示意圖。 FIG. 1B is a schematic diagram illustrating that the average value of the inductor current of the conventional DC-to-DC conversion circuit becomes larger and its period becomes shorter under heavy load steady state.

圖2繪示本發明的一較佳具體實施例中的時間信號產生器應用於直流對直流轉換電路的示意圖。 FIG. 2 is a schematic diagram of a time signal generator applied to a DC-DC conversion circuit in a preferred embodiment of the present invention.

圖3繪示圖2中的時間信號產生器的功能方塊圖。 FIG. 3 is a functional block diagram of the timing signal generator in FIG. 2 .

圖4A繪示數位式的時間信號產生器的一實施例。 FIG. 4A shows an embodiment of a digital time signal generator.

圖4B繪示數位式的時間信號產生器的另一實施例。 FIG. 4B shows another embodiment of the digital time signal generator.

圖5A及圖5B分別繪示習知的數位式時間信號產生器與本發明的數位式時間信號產生器在輕載穩態下所提供的時間信號的示意圖。 5A and FIG. 5B respectively show schematic diagrams of time signals provided by a conventional digital time signal generator and the digital time signal generator of the present invention under light-load steady state.

圖5C及圖5D分別繪示習知的數位式時間信號產生器與本發明的數位式時間信號產生器在重載穩態下的所提供的時間信號的示意圖。 FIG. 5C and FIG. 5D respectively show schematic diagrams of the time signals provided by the conventional digital time signal generator and the digital time signal generator of the present invention under heavy load steady state.

現在將詳細參考本發明的示範性實施例，並在附圖中說明所述示範性實施例的實例。在圖式及實施方式中所使用相同或類似標號的元件/構件是用來代表相同或類似部分。 Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Elements/members with the same or similar numbers used in the drawings and embodiments are used to represent the same or similar parts.

根據本發明的一較佳具體實施例為一種時間信號產生器。於此實施例中，時間信號產生器應用於直流對直流轉換電路，用以產生時間信號。 A preferred embodiment of the present invention is a time signal generator. In this embodiment, the time signal generator is applied to the DC-DC conversion circuit to generate the time signal.

請參照圖2，圖2繪示此實施例中的時間信號產生器應用於直流對直流轉換電路的示意圖。如圖2所示，直流對直流轉換電路2耦接負載LD且有負載電流IL流經負載LD。於重載期間，通過負載LD的負載電流IL會 增加。 Please refer to FIG. 2 . FIG. 2 shows a schematic diagram of applying the time signal generator in this embodiment to a DC-DC conversion circuit. As shown in FIG. 2 , the DC-DC conversion circuit 2 is coupled to a load LD and a load current I L flows through the load LD. During heavy load, the load current IL through the load LD will increase.

直流對直流轉換電路2包含時間信號產生器1、驅動電路DR、輸出級OS及回授電路FB。時間信號產生器1耦接驅動電路DR及回授電路FB。驅動電路DR耦接時間信號產生器1及輸出級OS。輸出級OS耦接輸入電壓Vin、接地電壓GND、驅動電路DR、回授電路FB及負載LD並產生輸出電壓Vout。回授電路FB耦接輸出電壓Vout及時間信號產生器1。 The DC-DC conversion circuit 2 includes a timing signal generator 1, a driving circuit DR, an output stage OS and a feedback circuit FB. The timing signal generator 1 is coupled to the driving circuit DR and the feedback circuit FB. The driving circuit DR is coupled to the timing signal generator 1 and the output stage OS. The output stage OS is coupled to the input voltage Vin, the ground voltage GND, the driving circuit DR, the feedback circuit FB and the load LD to generate the output voltage Vout. The feedback circuit FB is coupled to the output voltage Vout and the time signal generator 1 .

時間信號產生器1分別接收輸入電壓Vin、輸出電壓Vout、負載電流IL、時脈信號CLK與觸發信號TR並提供時間信號Ton至驅動電路DR。驅動電路DR根據時間信號Ton產生第一驅動信號DS1及第二驅動信號DS2至輸出級OS。輸出級OS受第一驅動信號DS1及第二驅動信號DS2驅動而產生輸出電壓Vout。回授電路FB根據輸出電壓Vout產生觸發信號TR至時間信號產生器1。 The timing signal generator 1 respectively receives the input voltage Vin, the output voltage Vout, the load current IL, the clock signal CLK and the trigger signal TR and provides the timing signal Ton to the driving circuit DR. The driving circuit DR generates a first driving signal DS1 and a second driving signal DS2 to the output stage OS according to the time signal Ton. The output stage OS is driven by the first driving signal DS1 and the second driving signal DS2 to generate an output voltage Vout. The feedback circuit FB generates a trigger signal TR to the timing signal generator 1 according to the output voltage Vout.

於實際應用中，輸出級OS包括串接於輸入電壓Vin與接地電壓GND之間的第一開關及第二開關，分別受第一驅動信號D1及第二驅動信號D2驅動而於第一開關及第二開關之間輸出電感電流Iind並產生輸出電壓Vout。 In practical applications, the output stage OS includes a first switch and a second switch connected in series between the input voltage Vin and the ground voltage GND, respectively driven by the first drive signal D1 and the second drive signal D2 to switch between the first switch and the second switch. The inductor current Iind is output between the second switches to generate an output voltage Vout.

請參照圖3，圖3繪示圖2中的時間信號產生器1的功能方塊圖。如圖3所示，時間信號產生器1包括類比數位轉換單元10、補償單元11、計數單元12、比較單元14及邏輯單元16。類比數位轉換單元10耦接至補償單元11。補償單元11及計數單元12均耦接至比較單元14。比較單元14耦接至邏輯單元16。 Please refer to FIG. 3 , which is a functional block diagram of the time signal generator 1 in FIG. 2 . As shown in FIG. 3 , the time signal generator 1 includes an analog-to-digital conversion unit 10 , a compensation unit 11 , a counting unit 12 , a comparison unit 14 and a logic unit 16 . The analog-to-digital conversion unit 10 is coupled to the compensation unit 11 . Both the compensation unit 11 and the counting unit 12 are coupled to the comparison unit 14 . The comparison unit 14 is coupled to the logic unit 16 .

類比數位轉換單元10分別接收輸出電壓Vout、輸入電壓Vin 及負載電流IL，並分別轉換為數位輸出電壓信號SVout、數位輸入電壓信號SVin及數位負載電流信號SIL後提供至補償單元11。 The analog-to-digital conversion unit 10 respectively receives the output voltage Vout and the input voltage Vin and the load current IL, and are respectively converted into a digital output voltage signal SVout, a digital input voltage signal SVin and a digital load current signal SIL, and then provided to the compensation unit 11 .

補償單元11分別接收數位輸出電壓信號SVout、數位輸入電壓信號SVin及數位負載電流信號SIL，並對數位輸出電壓信號SVout、數位輸入電壓信號SVin及數位負載電流信號SIL進行運算處理後產生補償信號S1。計數單元12依據時脈信號CLK與觸發信號TR來提供計數信號S2。 The compensation unit 11 respectively receives the digital output voltage signal SVout, the digital input voltage signal SVin and the digital load current signal SIL, and performs arithmetic processing on the digital output voltage signal SVout, the digital input voltage signal SVin and the digital load current signal SIL to generate the compensation signal S1 . The counting unit 12 provides the counting signal S2 according to the clock signal CLK and the trigger signal TR.

比較單元14分別接收來自補償單元11的補償信號S1以及來自計數單元12的計數信號S2，並根據補償信號S1與計數信號S2提供比較信號S3至邏輯單元16。邏輯單元16分別接收觸發信號TR與比較信號S3，並根據觸發信號TR與比較信號S3提供時間信號Ton至驅動電路DR。 The comparison unit 14 respectively receives the compensation signal S1 from the compensation unit 11 and the count signal S2 from the count unit 12 , and provides a comparison signal S3 to the logic unit 16 according to the compensation signal S1 and the count signal S2 . The logic unit 16 receives the trigger signal TR and the comparison signal S3 respectively, and provides the time signal Ton to the driving circuit DR according to the trigger signal TR and the comparison signal S3 .

於實際應用中，時間信號產生器1的邏輯單元16所提供的時間信號Ton與數位輸入電壓信號SVin、數位輸出電壓信號SVout及數位負載電流信號SIL有關，但不以此為限。 In practical application, the time signal Ton provided by the logic unit 16 of the time signal generator 1 is related to the digital input voltage signal SVin, the digital output voltage signal SVout and the digital load current signal SIL, but not limited thereto.

於輕載期間，負載電流IL造成的補償值會被省略，邏輯單元16提供的時間信號Ton維持不變。於重載期間，通過負載LD的負載電流IL增加，致使與負載電流IL相關的數位負載電流信號SIL增加，而補償單元11根據數位負載電流信號SIL所產生的補償信號S1以及比較單元14根據補償信號S1提供的比較信號S3亦會隨之增加，使得邏輯單元16提供的時間信號Ton亦會隨著比較信號S3增加且時間信號Ton的增加量會與數位負載電流信號SIL的增加量有關，但不以此為限。 During the light load period, the compensation value caused by the load current IL is omitted, and the time signal Ton provided by the logic unit 16 remains unchanged. During the heavy load period, the load current IL passing through the load LD increases, causing the digital load current signal SIL related to the load current IL to increase, and the compensation unit 11 generates the compensation signal S1 according to the digital load current signal SIL and the comparison unit 14 according to the compensation The comparison signal S3 provided by the signal S1 will also increase accordingly, so that the time signal Ton provided by the logic unit 16 will also increase with the comparison signal S3, and the increase of the time signal Ton will be related to the increase of the digital load current signal SIL, but This is not the limit.

請參照圖4A，圖4A繪示數位式的時間信號產生器的一實施例。如圖4A所示，時間信號產生器1包括補償單元11、計數單元12、比較 單元14及邏輯單元16。補償單元11包括第一乘法器M1、第二乘法器M2、加法器ADD及除法器DIV。加法器ADD耦接第一乘法器M1。除法器DIV耦接加法器ADD及第二乘法器M2。 Please refer to FIG. 4A . FIG. 4A shows an embodiment of a digital time signal generator. As shown in Figure 4A, the time signal generator 1 includes a compensation unit 11, a counting unit 12, a comparison Unit 14 and logic unit 16. The compensation unit 11 includes a first multiplier M1, a second multiplier M2, an adder ADD and a divider DIV. The adder ADD is coupled to the first multiplier M1. The divider DIV is coupled to the adder ADD and the second multiplier M2.

第一乘法器M1用以將數位負載電流信號SIL乘以第一常數ki而得到第一乘積(ki*SIL)。第二乘法器M2用以將數位輸入電壓信號SVin乘以第二常數kv而得到第二乘積(kv*SVin)。加法器ADD用以將數位輸出電壓信號SVout加上第一乘積ki*SIL而得到總和值SUM=(SVout+ki*SIL)。除法器DIV用以將總和值SUM除以第二乘積(kv*SVin)而得到補償信號S1，亦即補償信號S1=(SVout+ki*SIL)/(kv*SVin)。 The first multiplier M1 is used to multiply the digital load current signal SIL by a first constant ki to obtain a first product (ki*SIL). The second multiplier M2 is used for multiplying the digital input voltage signal SVin by a second constant kv to obtain a second product (kv*SVin). The adder ADD is used for adding the digital output voltage signal SVout to the first product ki*SIL to obtain a sum value SUM=(SVout+ki*SIL). The divider DIV is used for dividing the sum SUM by the second product (kv*SVin) to obtain the compensation signal S1, that is, the compensation signal S1=(SVout+ki*SIL)/(kv*SVin).

計數單元12依據時脈信號CLK與觸發信號TR來提供計數信號S2。比較單元14分別接收來自補償單元11的補償信號S1以及來自計數單元12的計數信號S2，並根據補償信號S1與計數信號S2提供比較信號S3至邏輯單元16。邏輯單元16分別接收觸發信號TR與比較信號S3，並根據觸發信號TR與比較信號S3提供時間信號Ton至驅動電路DR。 The counting unit 12 provides the counting signal S2 according to the clock signal CLK and the trigger signal TR. The comparison unit 14 respectively receives the compensation signal S1 from the compensation unit 11 and the count signal S2 from the count unit 12 , and provides a comparison signal S3 to the logic unit 16 according to the compensation signal S1 and the count signal S2 . The logic unit 16 receives the trigger signal TR and the comparison signal S3 respectively, and provides the time signal Ton to the driving circuit DR according to the trigger signal TR and the comparison signal S3 .

需說明的是，提供至補償單元11的數位輸出電壓信號SVout、數位輸入電壓信號SVin及數位負載電流信號SIL可由類比數位轉換單元10分別轉換輸出電壓Vout、輸入電壓Vin及負載電流IL而得，但不以此為限。 It should be noted that the digital output voltage signal SVout, the digital input voltage signal SVin and the digital load current signal SIL provided to the compensation unit 11 can be obtained by converting the output voltage Vout, the input voltage Vin and the load current IL respectively by the analog-to-digital conversion unit 10, But not limited to this.

請參照圖4B，圖4B繪示數位式的時間信號產生器的另一實施例。如圖4B所示，時間信號產生器1包括補償單元11、計數單元12、比較單元14及邏輯單元16。補償單元11包括第一乘法器M1、第二乘法器M2、第一除法器DIV1、第二除法器DIV2及加法器ADD。第一乘法器M1耦接第 一除法器DIV1。第二乘法器M2耦接除法器DIV耦接第一除法器DIV1及第二除法器DIV2。第一除法器DIV1及第二除法器DIV2均耦接加法器ADD。 Please refer to FIG. 4B . FIG. 4B shows another embodiment of a digital time signal generator. As shown in FIG. 4B , the time signal generator 1 includes a compensation unit 11 , a counting unit 12 , a comparison unit 14 and a logic unit 16 . The compensation unit 11 includes a first multiplier M1 , a second multiplier M2 , a first divider DIV1 , a second divider DIV2 and an adder ADD. The first multiplier M1 is coupled to the first A divider DIV1. The second multiplier M2 is coupled to the divider DIV and coupled to the first divider DIV1 and the second divider DIV2 . Both the first divider DIV1 and the second divider DIV2 are coupled to the adder ADD.

第一乘法器M1用以將數位負載電流信號SIL乘以第一常數ki而得到第一乘積(ki*SIL)。第二乘法器M2用以將數位輸入電壓SVin信號乘以第二常數kv而得到第二乘積(kv*SVin)。第一除法器DIV1用以將第一乘積(ki*SIL)除以第二乘積(kv*SVin)而得到第一商值(ki*SIL)/(kv*SVin)。第二除法器DIV2用以將數位輸出電壓信號SVout除以第二乘積(kv*SVin)而得到第二商值SVout/(kv*SVin)。加法器ADD用以將第一商值(ki*SIL)/(kv*SVin)與第二商值SVout/(kv*SVin)相加而得到補償信號S1，亦即補償信號S1=(SVout+ki*SIL)/(kv*SVin)。 The first multiplier M1 is used to multiply the digital load current signal SIL by a first constant ki to obtain a first product (ki*SIL). The second multiplier M2 is used to multiply the digital input voltage SVin signal by a second constant kv to obtain a second product (kv*SVin). The first divider DIV1 is used for dividing the first product (ki*SIL) by the second product (kv*SVin) to obtain a first quotient (ki*SIL)/(kv*SVin). The second divider DIV2 is used for dividing the digital output voltage signal SVout by the second product (kv*SVin) to obtain a second quotient SVout/(kv*SVin). The adder ADD is used to add the first quotient value (ki*SIL)/(kv*SVin) and the second quotient value SVout/(kv*SVin) to obtain the compensation signal S1, that is, the compensation signal S1=(SVout+ ki*SIL)/(kv*SVin).

需說明的是，提供至補償單元11的數位輸出電壓信號SVout、數位輸入電壓信號SVin及數位負載電流信號SIL可由類比數位轉換單元10分別轉換輸出電壓Vout、輸入電壓Vin及負載電流IL而得，但不以此為限。 It should be noted that the digital output voltage signal SVout, the digital input voltage signal SVin and the digital load current signal SIL provided to the compensation unit 11 can be obtained by converting the output voltage Vout, the input voltage Vin and the load current IL respectively by the analog-to-digital conversion unit 10, But not limited to this.

接著，請參照圖5A至圖5D。圖5A及圖5B分別繪示習知的數位式時間信號產生器與本發明的數位式時間信號產生器在輕載穩態下所提供的時間信號的示意圖。圖5C及圖5D分別繪示習知的數位式時間信號產生器與本發明的數位式時間信號產生器在重載穩態下的所提供的時間信號的示意圖。 Next, please refer to FIG. 5A to FIG. 5D . 5A and FIG. 5B respectively show schematic diagrams of time signals provided by a conventional digital time signal generator and the digital time signal generator of the present invention under light-load steady state. FIG. 5C and FIG. 5D respectively show schematic diagrams of the time signals provided by the conventional digital time signal generator and the digital time signal generator of the present invention under heavy load steady state.

如圖5A及圖5B所示，在輕載穩態下，因為數位電路的特性，微小的計算誤差(例如輕載狀態下的負載電流造成的補償值)會被省略，所以習知的數位式時間信號產生器所提供的時間信號Ton1的週期D1及導通 時間的長度T1與本發明的數位式時間信號產生器所提供的時間信號Ton2的週期D2及導通時間的長度T2不變，例如兩者的週期均為1000ns且兩者的導通時間的長度均為300ns。 As shown in Figure 5A and Figure 5B, under light-load steady state, due to the characteristics of digital circuits, small calculation errors (such as the compensation value caused by the load current in light-load state) will be omitted, so the conventional digital formula Period D1 and conduction of the time signal Ton1 provided by the time signal generator The length T1 of the time and the period D2 of the time signal Ton2 provided by the digital time signal generator of the present invention and the length T2 of the conduction time are constant, for example, the period of both is 1000 ns and the length of the conduction time of both is 1000 ns. 300ns.

如圖5C所示，在重載穩態下，習知的數位式時間信號產生器所提供的時間信號Ton1的導通時間的長度T1’仍維持在300ns，但這也導致時間信號Ton1的週期D1’從1000ns變成860ns，總共縮短了140ns之多，造成習知的直流對直流轉換電路的開關頻率變高而影響其電源轉換效率。 As shown in FIG. 5C , under the steady state of heavy load, the length T1' of the on-time of the time signal Ton1 provided by the conventional digital time signal generator is still maintained at 300 ns, but this also results in a period D1 of the time signal Ton1 'From 1000ns to 860ns, the total shortening is as much as 140ns, which causes the switching frequency of the conventional DC-to-DC conversion circuit to become higher and affects its power conversion efficiency.

相較之下，如圖5D所示，在重載穩態下，本發明的數位式時間信號產生器所提供的時間信號Ton2的導通時間的長度T2’會隨著負載電流增加而從300ns變成340ns，而時間信號Ton2的週期D2’僅會從1000ns變成995ns，總共僅縮短了5ns而已，故本發明的能維持直流對直流轉換電路的開關頻率恆定而提升其電源轉換效率。 In contrast, as shown in FIG. 5D , under heavy load steady state, the length T2' of the on-time of the time signal Ton2 provided by the digital time signal generator of the present invention will change from 300 ns to 300 ns as the load current increases. 340ns, and the period D2' of the time signal Ton2 will only change from 1000ns to 995ns, which is only shortened by 5ns in total. Therefore, the present invention can maintain the switching frequency of the DC-DC conversion circuit constant and improve its power conversion efficiency.

根據本發明的另一較佳具體實施例為一種直流-直流轉換電路。於此實施例中，直流-直流轉換電路用以將輸入電壓轉換為輸出電壓。 Another preferred embodiment of the present invention is a DC-DC conversion circuit. In this embodiment, the DC-DC conversion circuit is used to convert the input voltage into an output voltage.

如圖2所示，直流-直流轉換電路2耦接負載LD，並有負載電流IL流經負載LD。直流-直流轉換電路2包括輸出級OS、驅動電路DR、回授電路FB及時間信號產生器1。輸出級OS耦接負載LD，用以接收至少一驅動信號DS1~DS2以將輸入電壓Vin轉換為輸出電壓Vout。驅動電路DR耦接輸出級OS，用以根據時間信號Ton產生至少一驅動信號DS1~DS2。回授電路FB耦接輸出級OS，用以根據輸出電壓Vout產生觸發信號TR。時間信號產生器1耦接於回授電路FB及驅動電路DR之間， 用以接收輸入電壓Vin、輸出電壓Vout、負載電流IL及觸發信號TR，以產生時間信號Ton。 As shown in FIG. 2 , the DC-DC conversion circuit 2 is coupled to a load LD, and a load current IL flows through the load LD. The DC-DC conversion circuit 2 includes an output stage OS, a driving circuit DR, a feedback circuit FB and a time signal generator 1 . The output stage OS is coupled to the load LD for receiving at least one driving signal DS1 - DS2 to convert the input voltage Vin into the output voltage Vout. The driving circuit DR is coupled to the output stage OS for generating at least one driving signal DS1˜DS2 according to the time signal Ton. The feedback circuit FB is coupled to the output stage OS for generating the trigger signal TR according to the output voltage Vout. The timing signal generator 1 is coupled between the feedback circuit FB and the driving circuit DR, It is used to receive the input voltage Vin, the output voltage Vout, the load current IL and the trigger signal TR to generate the time signal Ton.

如圖3所示，時間信號產生器1包括補償單元11。補償單元11分別接收與輸出電壓Vout相關的數位輸出電壓信號SVout、輸入電壓Vin相關的數位輸入電壓信號SVin及負載電流IL相關的數位負載電流信號SIL，且對數位輸出電壓信號SVout、數位輸入電壓信號SVin及數位負載電流信號SIL進行運算處理，以產生補償信號S1，並根據補償信號S1提供時間信號Ton。因此，時間信號Ton與數位輸入電壓信號SVin、數位輸出電壓信號SVout及數位負載電流信號SIL有關。 As shown in FIG. 3 , the time signal generator 1 includes a compensation unit 11 . The compensation unit 11 respectively receives the digital output voltage signal SVout related to the output voltage Vout, the digital input voltage signal SVin related to the input voltage Vin, and the digital load current signal SIL related to the load current IL, and compares the digital output voltage signal SVout, the digital input voltage The signal SVin and the digital load current signal SIL are processed to generate a compensation signal S1, and a time signal Ton is provided according to the compensation signal S1. Therefore, the time signal Ton is related to the digital input voltage signal SVin, the digital output voltage signal SVout and the digital load current signal SIL.

此外，時間信號產生器1還包括類比數位轉換單元10。類比數位轉換單元10分別接收輸出電壓Vout、輸入電壓Vin及負載電流IL，並分別轉換為數位輸出電壓信號SVout、數位輸入電壓信號SVin及數位負載電流信號SIL後提供至補償單元11。 In addition, the time signal generator 1 also includes an analog-to-digital conversion unit 10 . The analog-to-digital conversion unit 10 respectively receives the output voltage Vout, the input voltage Vin and the load current IL, and converts them into a digital output voltage signal SVout, a digital input voltage signal SVin and a digital load current signal SIL respectively, and then provides them to the compensation unit 11 .

於重載期間，流經負載LD的負載電流IL增加，致使與負載電流IL相關的數位負載電流信號SIL增加，補償單元11所產生的補償信號S1也隨之增加。至於直流-直流轉換電路2中的其他元件及其運作情形請參照上述實施例，在此不另行贅述。 During the heavy load period, the load current IL flowing through the load LD increases, so that the digital load current signal SIL related to the load current IL increases, and the compensation signal S1 generated by the compensation unit 11 also increases accordingly. As for the other components and their operation in the DC-DC conversion circuit 2 , please refer to the above-mentioned embodiments, and will not be repeated here.

相較於先前技術，本發明的時間信號產生器能夠藉由與負載電流相關的補償信號來調整其提供給直流對直流轉換電路的驅動電路的時間信號，因此，當直流對直流轉換電路運作於重載穩態而使得負載電流增加時，本發明的時間信號產生器時間信號所提供的時間信號中的導通時間亦隨之增加，藉以維持直流對直流轉換電路的開關頻率恆定而提升直流對 直流轉換電路運作於重載穩態時的電源轉換效率。 Compared with the prior art, the time signal generator of the present invention can adjust the time signal provided to the driving circuit of the DC-DC conversion circuit by using the compensation signal related to the load current. Therefore, when the DC-DC conversion circuit operates in When the load current increases due to the heavy load steady state, the conduction time in the time signal provided by the time signal generator time signal of the present invention also increases accordingly, so as to maintain the switching frequency of the DC-to-DC conversion circuit constant and improve the DC-to-DC conversion circuit. The power conversion efficiency of the DC conversion circuit operating in a heavy load steady state.

藉由以上較佳具體實施例的詳述，係希望能更加清楚描述本發明的特徵與精神，而並非以上述所揭露的較佳具體實施例來對本發明的範疇加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請的專利範圍的範疇內。 Through the above detailed description of the preferred embodiments, it is hoped that the characteristics and spirit of the present invention can be described more clearly, and the scope of the present invention is not limited by the preferred embodiments disclosed above. On the contrary, the intention is to cover various changes and equivalent arrangements within the scope of the claimed patent scope of the present invention.

1:時間信號產生器 1: Time signal generator

10:類比數位轉換單元 10: Analog to digital conversion unit

11:補償單元 11: Compensation unit

12:計數單元 12: counting unit

14:比較單元 14: Comparison unit

16:邏輯單元 16: logic unit

CLK:時脈信號 CLK: clock signal

TR:觸發信號 TR: trigger signal

SVout:數位輸出電壓信號 SVout: digital output voltage signal

SVin:數位輸入電壓信號 SVin: digital input voltage signal

SIL:數位負載電流信號 SI L : Digital load current signal

Vout:輸出電壓 Vout: output voltage

Vin:輸入電壓 Vin: input voltage

IL:負載電流 I L : load current

S1:補償信號 S1: Compensation signal

S2:計數信號 S2: counting signal

S3:比較信號 S3: compare signal

Ton:時間信號 Ton: time signal

Claims (10)

一種時間信號產生器，產生一時間信號以使一直流對直流轉換電路將一輸入電壓轉換為一輸出電壓，該直流對直流轉換電路耦接一負載，並有一負載電流流經該負載，該時間信號產生器包括：一類比數位轉換單元，分別接收該輸出電壓、該輸入電壓及該負載電流，並分別轉換為一數位輸出電壓信號、一數位輸入電壓信號及一數位負載電流信號；一補償單元，分別接收該數位輸出電壓信號、該數位輸入電壓信號及該數位負載電流信號，且對該數位輸出電壓信號、該數位輸入電壓信號及該數位負載電流信號進行一運算處理，以產生一補償信號；一計數單元，依據一時脈信號與一觸發信號來提供一計數信號；一比較單元，接收該補償信號與該計數信號以提供一比較信號；以及一邏輯單元，接收該觸發信號與該比較信號以提供該時間信號。 A time signal generator that generates a time signal so that a DC-to-DC conversion circuit converts an input voltage into an output voltage. The DC-to-DC conversion circuit is coupled to a load, and a load current flows through the load. The time The signal generator includes: an analog-to-digital conversion unit, respectively receiving the output voltage, the input voltage and the load current, and respectively converting them into a digital output voltage signal, a digital input voltage signal and a digital load current signal; a compensation unit , respectively receiving the digital output voltage signal, the digital input voltage signal and the digital load current signal, and performing an operation process on the digital output voltage signal, the digital input voltage signal and the digital load current signal to generate a compensation signal ; A counting unit, which provides a count signal according to a clock signal and a trigger signal; a comparison unit, which receives the compensation signal and the count signal to provide a comparison signal; and a logic unit, which receives the trigger signal and the comparison signal to provide the time signal. 如申請專利範圍第1項所述的時間信號產生器，其中該時間信號與該數位輸入電壓信號、該數位輸出電壓信號及該數位負載電流信號有關。 The time signal generator as described in item 1 of the scope of the patent application, wherein the time signal is related to the digital input voltage signal, the digital output voltage signal and the digital load current signal. 如申請專利範圍第1項所述的時間信號產生器，其中於重載期間，流經該負載的該負載電流增加，致使與該負載電流相關的該數位負載電流信號增加，該補償單元所產生的該補償信號及該比較單元所提供的該比較信號亦隨之增加。 The time signal generator as described in item 1 of the patent scope of the application, wherein the load current flowing through the load increases during the heavy load period, causing the digital load current signal related to the load current to increase, and the compensation unit generates The compensation signal and the comparison signal provided by the comparison unit also increase accordingly. 如申請專利範圍第1項所述的時間信號產生器，其中該補償 單元包括：一第一乘法器，用以將該數位負載電流信號乘以一第一常數而得到一第一乘積；一第二乘法器，用以將該數位輸入電壓信號乘以一第二常數而得到一第二乘積；一加法器，耦接該第一乘法器，用以將該數位輸出電壓信號加上該第一乘積而得到一總和值；以及一除法器，耦接該加法器及該第二乘法器，用以將該總和值除以該第二乘積而得到該補償信號。 The time signal generator as described in item 1 of the scope of the patent application, wherein the compensation The unit includes: a first multiplier for multiplying the digital load current signal by a first constant to obtain a first product; a second multiplier for multiplying the digital input voltage signal by a second constant and a second product is obtained; an adder, coupled to the first multiplier, is used to add the digital output voltage signal to the first product to obtain a sum value; and a divider, coupled to the adder and The second multiplier is used for dividing the sum value by the second product to obtain the compensation signal. 如申請專利範圍第4項所述的時間信號產生器，其中該時間信號亦隨著該總和值增加，且該時間信號的增加量與該數位負載電流信號的增加量有關。 The time signal generator as described in claim 4 of the patent application, wherein the time signal also increases with the sum value, and the increase of the time signal is related to the increase of the digital load current signal. 如申請專利範圍第1項所述的時間信號產生器，其中該補償單元包括：一第一乘法器，用以將該數位負載電流信號乘以一第一常數而得到一第一乘積；一第二乘法器，用以將該數位輸入電壓信號乘以一第二常數而得到一第二乘積；一第一除法器，耦接該第一乘法器及該第二乘法器，用以將該負載電流信號除以該第二乘積而得到一第一商值；一第二除法器，耦接該第二乘法器，用以將該數位輸出電壓除以該第二乘積而得到一第二商值；以及 一加法器，耦接該第一除法器及該第二除法器，用以相加該第一商值與該第二商值而得到該補償信號。 The time signal generator as described in item 1 of the patent scope, wherein the compensation unit includes: a first multiplier, which is used to multiply the digital load current signal by a first constant to obtain a first product; a first Two multipliers, used to multiply the digital input voltage signal by a second constant to obtain a second product; a first divider, coupled to the first multiplier and the second multiplier, for the load The current signal is divided by the second product to obtain a first quotient; a second divider, coupled to the second multiplier, is used to divide the digital output voltage by the second product to obtain a second quotient ;as well as An adder, coupled to the first divider and the second divider, is used to add the first quotient and the second quotient to obtain the compensation signal. 一種直流-直流轉換電路，將一輸入電壓轉換為一輸出電壓，該直流-直流轉換電路耦接一負載，並有一負載電流流經該負載，其中該直流-直流轉換電路包括：一輸出級，耦接該負載，接收至少一驅動信號以將該輸入電壓轉換為該輸出電壓；一驅動電路，耦接該輸出級，根據一時間信號產生該至少一驅動信號；一回授電路，耦接該輸出級，根據該輸出電壓產生一觸發信號；以及一時間信號產生器，耦接於該回授電路及該驅動電路之間，接收該輸入電壓、該輸出電壓、該負載電流及該觸發信號，以產生該時間信號；其中，該時間信號產生器包括：一補償單元，分別接收與該輸出電壓相關的一數位輸出電壓信號、與該輸入電壓相關的一數位輸入電壓信號及與該負載電流相關的一數位負載電流信號，且對該數位輸出電壓信號、該數位輸入電壓信號及該數位負載電流信號進行一運算處理，以產生一補償信號，並根據該補償信號提供該時間信號。 A DC-DC conversion circuit converts an input voltage into an output voltage, the DC-DC conversion circuit is coupled to a load, and a load current flows through the load, wherein the DC-DC conversion circuit includes: an output stage, coupled to the load, receiving at least one driving signal to convert the input voltage into the output voltage; a driving circuit, coupled to the output stage, generating the at least one driving signal according to a time signal; a feedback circuit, coupled to the an output stage, generating a trigger signal according to the output voltage; and a timing signal generator, coupled between the feedback circuit and the drive circuit, receiving the input voltage, the output voltage, the load current and the trigger signal, to generate the time signal; wherein, the time signal generator includes: a compensation unit, respectively receiving a digital output voltage signal related to the output voltage, a digital input voltage signal related to the input voltage and a digital input voltage signal related to the load current A digital load current signal, and an operation process is performed on the digital output voltage signal, the digital input voltage signal and the digital load current signal to generate a compensation signal, and the time signal is provided according to the compensation signal. 如申請專利範圍第7項所述的直流-直流轉換電路，其中該時間信號產生器還包括： 一類比數位轉換單元，耦接該補償單元，分別接收該輸出電壓、該輸入電壓及該負載電流，並分別轉換為該數位輸出電壓信號、該數位輸入電壓信號及該數位負載電流信號。 The DC-DC conversion circuit described in item 7 of the scope of patent application, wherein the time signal generator also includes: An analog-to-digital conversion unit, coupled to the compensation unit, respectively receives the output voltage, the input voltage and the load current, and converts them into the digital output voltage signal, the digital input voltage signal and the digital load current signal respectively. 如申請專利範圍第7項所述的直流-直流轉換電路，其中該時間信號與該數位輸出電壓信號及該數位負載電流信號有關。 The DC-DC conversion circuit described in item 7 of the scope of the patent application, wherein the time signal is related to the digital output voltage signal and the digital load current signal. 如申請專利範圍第7項所述的直流-直流轉換電路，其中於一重載期間，流經該負載的該負載電流增加，致使與該負載電流相關的該數位負載電流信號增加，該補償單元所產生的該補償信號也隨之增加。 The DC-DC conversion circuit described in item 7 of the scope of patent application, wherein during a heavy load period, the load current flowing through the load increases, causing the digital load current signal related to the load current to increase, and the compensation unit The resulting compensation signal is also increased accordingly.
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