CN107831820B - Single feedback loop with positive and negative output voltages suitable for voltage converter - Google Patents

Single feedback loop with positive and negative output voltages suitable for voltage converter Download PDF

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CN107831820B
CN107831820B CN201711135206.5A CN201711135206A CN107831820B CN 107831820 B CN107831820 B CN 107831820B CN 201711135206 A CN201711135206 A CN 201711135206A CN 107831820 B CN107831820 B CN 107831820B
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resistor
voltage
error amplifier
pnp transistor
output
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CN107831820A (en
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黄少卿
徐勤媛
李欢
罗永波
宣志斌
肖培磊
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CETC 58 Research Institute
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

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  • Dc-Dc Converters (AREA)

Abstract

The invention relates to a single feedback loop with positive output voltage and negative output voltage suitable for a voltage converter, which comprises an external resistor and a conversion chip, wherein a feedback part circuit in the conversion chip comprises a resistor I and a resistor II, and a first port of the resistor I and a second port of the resistor IReference voltage V generated inside chipREFThe second port of the resistor I is connected with the first port of the resistor II, the second port of the resistor II is grounded, and the connecting node of the resistor I and the resistor II is connected with the feedback pin V of the conversion chipFBConnecting; the converter comprises a control circuit and a power switch tube, and the converter is provided with a pin for receiving an external feedback signal, and the feedback signal is processed by a single feedback circuit inside the converter to generate a stable positive output voltage and/or a stable negative output voltage. According to the invention, through the action of the two internal error amplifiers, the boost converter and the inverting converter can be simultaneously realized under the feedback loop, and the conversion chip only needs one feedback pin port, so that the number of chip pins is saved.

Description

Single feedback loop with positive and negative output voltages suitable for voltage converter
Technical Field
The invention belongs to the internal control technology of a voltage converter, and particularly relates to a single feedback loop which is suitable for the voltage converter and has positive output voltage and negative output voltage.
Background
In the prior art, the voltage converter can output a stable voltage value, which can be higher than, equal to or lower than the input voltage, and the polarity of the output voltage can be positive or negative. Fig. 1A and 1B show two conventional voltage converter applications, wherein fig. 1A illustrates a boost converter circuit structure, and fig. 1B illustrates an inverter converter circuit structure, and the power switch and the control circuit are integrated on a conversion chip 10, which has a plurality of pins for output, and the pins are connected to external unit devices.
The voltage converter comprises an input capacitor 12 and an output capacitor 14, wherein a first input end of the input capacitor 12 is connected with an external power voltage VINThe second input terminal of the input capacitor 12 is grounded; the first input terminal of the output capacitor 14 is connected to the output node VOUTAnd the second input terminal of the output capacitor 14 is groundedThe output node may receive a load to ground.
The function of the voltage converter depends on the architecture and connection of the components external to the conversion chip 10. In the boost converter of fig. 1A, an inductor i 20 and a diode 22 are coupled in series VINAnd VOUTThe connection node between the inductor i 20 and the first diode 22 is connected to the power switch tube inside the switching chip 10 through the pin SW. The first resistor 16 and the second resistor 18 are connected in series between the output node and the ground, the connection node of the first resistor 16 and the second resistor 18 provides a feedback voltage, which is proportional to the output voltage, and the feedback voltage is connected to the circuit inside the conversion chip 10 through the pin FB. In the inverter type converter of FIG. 1B, an inductor I20, a capacitor I24 and an inductor II 26 are connected in series at VINAnd VOUTOne end of the diode 22 is connected to a connection node between the capacitor I24 and the inductor II 26, and the other end of the first diode 22 is grounded. The first resistor 16 and the second resistor 18 are connected in series between the output node and the ground, and the feedback voltage is connected to the control circuit inside the conversion chip 10 through the pin NFB. The capacitor iii 28 is connected in parallel with the first resistor 16.
The internal structure of the integrated conversion chip 10 in both converters is similar, and fig. 2 shows a typical circuit frame structure inside the conversion chip 10. The power switch tube 30 and the third resistor 32 are connected in series between the inductor I20 and the ground, and the current I flowing through the power switch tube 30SWThe on and off of the power switch tube 30 is controlled by the switch control circuit 34 by sampling on the resistor 32, and when the power switch tube 30 is on, the current is from VINFlows into the ground through the inductor I20, the switching tube 30 and the third resistor 32; when the power switch 30 is turned off, the energy stored in the inductor is transferred to the output capacitor 14. By properly controlling the on and off time of the power switch tube, a stable voltage can be obtained at the output end, and in the circuit shown in fig. 1A, the output voltage is greater than the input voltage; in the circuit shown in FIG. 1B, the output voltage is opposite in polarity to the input voltage.
The control circuit 34 comprises a trigger circuit and a power tube driving circuit, and the setting end of the control circuit is connected with a clock signalA pulse wave generated by an oscillator. Under the normal working state, when the rising edge of the clock comes, the clock is sent to the position end to conduct the power switch tube, the current flowing through the power switch tube is increased, and when the reset end of the control circuit receives a signal, the power switch tube is turned off, so that the signal received by the reset end determines the turn-on time of the power switch tube. The reset terminal of the control circuit is connected to the output of the comparator 38. Feedback signal V of output voltageFBConnected to the negative input of the first error amplifier 40, a reference voltage VREFThe positive input of the first error amplifier 40 is connected and a capacitor iv 42 is connected between the output of the first error amplifier 40 and ground.
The voltage V on the capacitor IV 42CIs a variation whose magnitude depends on the output of the first error amplifier 40. When the load increases, the output voltage decreases, VFBThen decreases, after passing through an error amplifier, VCThe voltage increases, therefore, VCThe voltage value is proportional to the output load. VCTo the negative input of comparator 38, to the positive input of which adder 44 is connected. The adder 44 adds the sampling signal I on the power switch tubeSWIs added to the compensation signal. After the rising edge of the clock signal is sent to the position end to conduct the power switch tube, the current flows through the inductor I20, the power switch tube 30 and the sampling resistor 32, ISWThe value of (A) represents the magnitude of the current when ISWAnd the sum of the compensation signal is greater than VCWhen the power switch tube is turned off, the comparator 38 outputs a reset signal to turn off the power switch tube. If the load increases, VCThe time for the power switch tube to be conducted is increased correspondingly, so that V is increasedOUTAnd is maintained at a constant value, which is typical of current mode control.
In a boost converter, the output voltage is positive, positive VFBThe voltage is fed back to the FB pin as shown in fig. 1A. For the inverter type converter in FIG. 1B, the output voltage is negative, and V is negativeFBThe voltage is fed back to the NFB pin. Although the external structures of the two converters are different, the integrated conversion chip in fig. 2 can be applied to both converters, and the conventional implementation is to increase the pin count of the chip, as shown in fig. 3A-3C. FIG. 3A shows three pins A,B. C, wherein the pin A is connected with a reference voltage VREFThe voltage may be generated from an external source or internally on the chip, pin B being connected to the positive input of the internal first error amplifier 40, and pin C being connected to the negative input of the internal first error amplifier 40. A. B, C can be connected in different ways to realize the boost feedback structure shown in fig. 3B and the reverse feedback structure shown in fig. 3C.
In FIG. 3B, pin A and pin B are connected externally, so reference voltage V isREFApplied to the positive input terminal of the error amplifier to output a voltage VOUTThe feedback voltage V generated after voltage division by the first resistor 16 and the second resistor 18FBTo the negative input of the error amplifier. The output terminal of the first error amplifier 40 varies with the load, thereby controlling the on and off of the power switch tube.
In FIG. 3C, pin C is connected to the external ground, and pin B is connected to the connection node V between the first resistor 16 and the second resistor 18NFBThe first resistor 16 and the second resistor 18 are connected in series at a voltage VREFand-VOUTIn the meantime. When the load increases, the absolute value of the output voltage decreases, and the output V of the first error amplifier 40CAnd the on-time of the power switch tube is controlled to change along with the change of the load.
Another integrated conversion chip implementation is shown in fig. 4A-4C, where fig. 4A shows the conversion chip 10 with two pins A, B, pin a is connected to the negative input terminal of the first error amplifier 40, the positive input terminal of the first error amplifier 40 is grounded, and the output terminal of the first error amplifier 40 is connected to the negative input terminal of the second error amplifier 41 through the second diode 43. Pin B is connected to the negative input terminal of the second error amplifier 41, and the positive input terminal of the second error amplifier 41 is connected to the reference voltage VREFThe reference voltage is generated internally by the conversion chip 10, and the output of the second error amplifier 41 generates the voltage VC。
FIG. 4B illustrates the connection of pin A to pin B as a boost converter, pin A being externally connected to a first resistor 16 and a second resistor 18, the node providing a feedbackVoltage VFBPin A and pin B are externally interconnected, so that the voltage V is fed backFBIs connected to the negative input of the second error amplifier 41, VCThe voltage varies with the output load.
FIG. 4C illustrates the connection of pin A to pin B as an inverter converter, pin A being externally connected to a first resistor 16 and a second resistor 18, the node providing a feedback voltage VNFBPin B is externally connected to a second input of a second resistor 18. In an inverter type converter, VOUTIs a negative value, VNFBI.e., a negative value, the first error amplifier 40 outputs a positive voltage value, which is coupled to the negative input of the second error amplifier 41 through the second diode 43. Feeding back voltage V under light loadNFBIs increased, the feedback voltage V is increased under heavy loadNFBWhen the input voltage of pin a becomes more negative under light load, the output voltage of the first error amplifier 40 connected to the negative input terminal of the second error amplifier 41 increases, and V is thereby increasedCThe voltage is reduced, thus VCThe voltage reflects the load variations.
The feedback structures of the two integrated conversion chips described above require additional pins to be externally configured to implement the boost converter and the inverter converter. Fig. 3A-3C illustrate the use of a single error amplifier and three external ports to implement the same chip for different classes of converters, and fig. 4A-4C illustrate the use of two error amplifiers and two external ports to implement the same chip for different classes of converters. A new structure is proposed to minimize the number of chip pins without changing the external configuration when the boost converter and the inverter converter are implemented simultaneously on the same chip.
Disclosure of Invention
The present invention is directed to overcome the disadvantages of the prior art, and to provide a single feedback loop with a positive output voltage and a negative output voltage for a voltage converter, which enables the same chip to simultaneously implement a boost-type conversion output and an inversion-type conversion output with the simplest external configuration and the least number of chip pins.
According to the technique provided by the inventionAccording to the technical scheme, the single feedback loop architecture comprises a conversion chip 10 and an external resistor 1, wherein a first port of the external resistor 1 and an output voltage V of a converterOUTThe second port of the external resistor 1 is connected with the feedback pin V of the conversion chip 10FBAre connected.
The feedback part circuit in the conversion chip 10 comprises a resistor I50 and a resistor II 52, wherein a first port of the resistor I50 and a reference voltage V generated inside the chipREFThe second port of the resistor I50 is connected with the first port of the resistor II 52, the second port of the resistor II 52 is grounded, and the connection node of the resistor I50 and the resistor II 52 is connected with the feedback pin V of the conversion chip 10FBAre connected.
Further comprises a first error amplifier 40 and a second error amplifier 41, wherein the positive input terminal of the first error amplifier 40 is connected with the reference voltage VREFA negative input end of the first error amplifier 40 is connected with a positive input end of the second error amplifier 41, a negative input end of the second error amplifier 41 is grounded, and a node 51, where the negative input end of the first error amplifier 40 is connected with the positive input end of the second error amplifier 41, is connected with a feedback pin end of the conversion chip 10; the first error amplifier 40 is connected with a current source I through a diode I56, the anode of the diode I56 is connected with the current source I, the cathode of the diode I56 is connected with the output of the first error amplifier 40, the second error amplifier 41 is connected with the current source I through a diode II 58, the anode of the diode II 58 is connected with the current source I, the cathode of the diode II 58 is connected with the output of the second error amplifier 41, and the node of the anode of the diode I56 connected with the anode of the diode II 58 is used as an output control signal VC。
The first error amplifier 40 and the second error amplifier 41 are implemented by a first PNP transistor 70, a second PNP transistor 72, a third PNP transistor 74, a fourth PNP transistor 76, a first NPN transistor 78, a second NPN transistor 80, a resistor iii 82, a resistor iv 84, a resistor v 86, a resistor vi 88, a resistor vii 90, and a resistor viii 92. Emitters of the first PNP transistor 70 and the second PNP transistor 72 are connected to a current source II 71, emitters of the third PNP transistor 74 and the fourth PNP transistor 76Connected to a current source III 75, the base of the first PNP transistor 70 is connected to VREFThe bases of the second and third PNP transistors 72 and 74 are interconnected with VFBAnd the base of the fourth PNP transistor 76 is grounded.
The base and collector of the first NPN transistor 78 are interconnected to a current source iv 79, the collector of the second NPN transistor 80 is connected to a current source V81, and the connection node provides an output VCThe base of the first NPN transistor 78 is connected to the base of the second NPN transistor 80, the resistor v 86 and the resistor vii 90 are connected in series between the emitter of the first NPN transistor 78 and ground, the collectors of the second PNP transistor 72 and the third PNP transistor 74 are interconnected to the emitter of the first NPN transistor 78, the collectors of the second PNP transistor 72 and the fourth PNP transistor 76 are interconnected between the resistor vi 88 and the resistor viii 92 through the resistor iii 82 and the resistor iv 84, respectively, and the first NPN transistor 78 and the second NPN transistor 80 are matched with each other to form a current mirror structure.
The invention has the following advantages: under the control of the single feedback loop, the configuration of an external feedback resistor can be fixed, and a boost converter and an inverting converter can be simultaneously realized under the feedback loop under the action of two internal error amplifiers, and a conversion chip only needs one feedback pin port, so that the number of chip pins is saved.
Drawings
Fig. 1A and 1B show a conventional boost voltage converter and an inverter voltage converter.
Fig. 2 is a schematic diagram of an internal part circuit of a conversion chip suitable for use in the voltage converter of fig. 1A and 1B.
Fig. 3A-3C illustrate an external configuration of a conversion chip suitable for a boost-type voltage converter and an inverter-type voltage converter.
Fig. 4A-4C illustrate another external configuration of a conversion chip suitable for a boost-type voltage converter and an inverter-type voltage converter.
Fig. 5 is a schematic diagram of a part of a feedback control design circuit suitable for a boost voltage converter and an inverting voltage converter according to the present invention.
FIG. 6 is a waveform of the feedback voltage to the control voltage in the circuit of FIG. 5 according to the present invention.
FIG. 7 is a diagram of an embodiment of the circuit of FIG. 5 according to the present invention.
Detailed Description
The invention is further illustrated by the following specific figures and examples.
The feedback control scheme shown in the dashed box of FIG. 5 is suitable for use in the converter chip 10 to output the voltage VOUTA feedback voltage V is provided by an external resistor 1 applied to a feedback pin terminal of the conversion chip 10FBV inside the chipREFAnd the resistor I50 and the resistor II 52 are connected in series with the ground, the resistance values of the two resistors are equal, and the connecting node of the resistor I50 and the resistor II 52 is connected with the feedback pin end. Reference voltage VREFConnected to the positive input of the first error amplifier, the negative input of the first error amplifier 40 is connected to the positive input of the second error amplifier 41, the negative input of which is connected to ground. A node 51 at which the negative input of the first error amplifier 40 is connected to the positive input of the second error amplifier 41 is connected to the feedback pin terminal.
Control signal VCThe first error amplifier 40 is connected to a current source i through a diode i 56, the anode of the diode i 56 is connected to the current source i, and the cathode of the diode i 56 is connected to the output of the first error amplifier 40. The second error amplifier 41 is connected to a current source i through a diode ii 58, the anode of the diode ii 58 is connected to the current source i, and the cathode of the diode ii 58 is connected to the output of the second error amplifier 41.
In normal operation, V in the step-up converterFBThe voltage is positive, and V is in the inverter type converterFBThe voltage is negative. In the boost converter, the positive input voltage of the second error amplifier 41 is greater than the negative input voltage, the output voltage is high, the diode II 58 is turned off, and the output pair V of the second error amplifier 41CThe voltage has no effect. When the output is overloaded, VOUTThe voltage is slightly reduced, and a feedback voltage end VFBVoltage lower than VREFVoltage, the output of first error amplifier 40 is raised, due to the action of diode I56Causing more current in current source I to flow into VCIn a node, result in VCThe voltage rises and the boost converter transfers more energy to the output load. When light load is output, VOUTThe voltage slightly rises and the feedback voltage end VFBThe voltage being higher than VREFThe voltage, the output of the first error amplifier 40, decreases, and the energy transferred to the output load side is reduced by the boost converter due to the action of the diode i 56, which causes more current in the current source i to flow into the first error amplifier 40 first, resulting in a decrease in the VC voltage.
In an inverter type converter, VOUTThe voltage being negative, VFBThe voltage is also negative, and the positive input end voltage V of the first error amplifierREFGreater than negative input terminal voltage VFBThe output voltage is high, the diode I56 is turned off, and the output pair V of the first error amplifier 40CThe voltage has no effect. When the output is overloaded, VOUTThe absolute value of the voltage slightly drops, and a feedback voltage end VFBThe voltage is higher than the ground voltage, the output of the second error amplifier 41 is raised, and more current flows into the current source I due to the action of the diode II 58CIn a node, result in VCThe voltage rises and the inverter type converter transfers more energy to the output load. When light load is output, VOUTThe absolute value of the voltage slightly rises, and a voltage end V is fed backFBVoltage lower than VREFThe voltage, the output of the second error amplifier 41 decreases, and more current from the current source I flows into the second error amplifier 41 due to the action of the diode II 58, resulting in VCThe voltage drops and the inverter type converter reduces the energy transferred to the output load side.
The internal resistor II 52 replaces the traditional feedback resistor 18, and the conversion chip only needs one external pin port (V)FB) The method can be simultaneously applied to a boost converter and an inverting converter, and the chip internal resistor I50, the resistor II 52 and the chip external resistor 1 jointly form a feedback network of the two converters.
FIG. 6 shows the feedback voltage V in the circuit of FIG. 5 according to the present inventionFBTo a control voltage VCOf a transmission waveShape, Y-axis represents control voltage VCThe X-axis represents the feedback port voltage VFBWhen V isFBVoltage at VREFWhen, VCWhere the voltage transitions between a and B values due to V caused by the high gain first error amplifier 40 in the boost mode of operationCVoltage and VFBVoltage dependence when VFBVoltage lower than VREFWhen, VCVoltage is equal to B value when VFBThe voltage being higher than VREFWhen, VCThe voltage is equal to the value of a. In the inverting mode of operation, the high gain of the second error amplifier 41 results in a voltage VFBAt a voltage of 0, VCWhere the voltage is switched between a and B values.
FIG. 7 is a diagram of an embodiment of the circuit of FIG. 5 according to the present invention. In fig. 5, the first error amplifier 40 and the second error amplifier 41 are implemented by a first PNP transistor 70, a second PNP transistor 72, a third PNP transistor 74, a fourth PNP transistor 76, a first NPN transistor 78, a second NPN transistor 80, a resistor iii 82, a resistor iv 84, a resistor v 86, a resistor vi 88, a resistor vii 90, and a resistor viii 92. The emitters of the first PNP transistor 70 and the second PNP transistor 72 are connected to a current source II 71, the emitters of the third PNP transistor 74 and the fourth PNP transistor 76 are connected to a current source III 75, and the base of the first PNP transistor 70 is connected to VREFThe bases of the second and third PNP transistors 72 and 74 are interconnected with VFBAnd the base of the fourth PNP transistor 76 is grounded.
The base and collector of the first NPN transistor 78 are interconnected to a current source iv 79, the collector of the second NPN transistor 80 is connected to a current source V81, and the connection node provides an output VCThe base of the first NPN transistor 78 is connected to the base of the second NPN transistor 80, the resistor v 86 and the resistor vii 90 are connected in series between the emitter of the first NPN transistor 78 and ground, the collectors of the second PNP transistor 72 and the third PNP transistor 74 are connected to the emitter of the first NPN transistor 78, the collectors of the second PNP transistor 72 and the fourth PNP transistor 76 are connected to the resistors vi 88 and viii 92 through the resistors iii 82 and iv 84, respectively, and the first NPN transistor 78 and the second NPN transistor 80 are matched with each other to form a current mirror structure。
In normal operation, the current of the current source II 71 flows into the first PNP transistor 70 and the second PNP transistor 72 when V isFBVoltage greater than VREFWhen the voltage is high, most of the current source II 71 flows into the resistor V86 and the resistor VII 90 through the PNP transistor 70, when V isFBVoltage less than VREFWhen the voltage is applied, most of the current source ii 71 flows into the resistor iii 82 and the resistor viii 92 through the second PNP transistor 72. The current of the current source III flows into the third PNP transistor 74 and the fourth PNP transistor 76 when V isFBWhen the voltage is higher than the ground potential voltage, most of the current source III 75 flows into the resistor IV 84 and the resistor VIII 92 through the fourth PNP transistor 76, when V is higher than the ground potential voltageFBWhen the voltage is less than the ground potential voltage, most of the current source iii 75 flows through the third PNP transistor 74 into the resistor v 86 and the resistor vii 90.
The transmission waveforms in the boosting working mode and the inverting working mode in fig. 6 can be realized by reasonably setting the current values of the current source ii 71, the current source iii 75, the current source iv 79 and the current source v 81 and the resistance values of the resistor iii 82, the resistor iv 84, the resistor v 86, the resistor vi 88, the resistor vii 90 and the resistor viii 92. For example, the current values of the current sources II 71 and III 75 are set to 4 μ A, the current values of the current sources IV 79 and V81 are set to 2 μ A, the resistances of the resistor III 82, IV 84, V86 and VI 88 are set to 20 k.OMEGA, and the resistances of the resistor VII 90 and VIII 92 are set to 10 k.OMEGA, V.OMEGAREFSet to 1.25V.
In boost mode of operation, VFBThe voltage is 1.25V, the third PNP transistor 74 is turned off, all 4 μ a current of the current source iii 75 flows into the resistor iv 84 and the resistor viii 92 through the fourth PNP transistor 76, 4 μ a current of the current source ii 71 flows into the resistor V86, the resistor vii 90, the resistor iii 82, and the resistor viii 92 through the first PNP transistor 70(2 μ a) and the second PNP transistor 72(2 μ a), respectively, 2 μ a current of the current source iv 79 flows into the resistor V86 and the resistor vii 90 through the first NPN transistor 78, and 2 μ a current of the current source V81 flows into the resistor vi 88 and the resistor viii 92 through the second NPN transistor 80. Thus, the current flowing through the resistor VIII 92 was 8. mu.A, the current flowing through the resistor VI 88 was 2. mu.A, the current flowing through the resistor VII 90 was 4. mu.A, and the current flowing through the resistor V86 was 4. mu.AA, the emitter voltage of the first NPN transistor 78 is 120mV of the sum of the voltage drop (40mV) of the resistor VII 90 and the voltage drop (80mV) of the resistor V86, the emitter voltage of the second NPN transistor 80 is 120mV of the sum of the voltage drop (80mV) of the resistor VIII 92 and the voltage drop (40mV) of the resistor VI 88, the emitter voltages of the first NPN transistor 78 and the second NPN transistor 80 are consistent, and the collector voltage V of the second NPN transistor 80 is consistentCAt a certain voltage value.
When the output load is reduced, VFBThe voltage increases, the current through the second PNP transistor 72 decreases, the current through the first PNP transistor 70 increases, and thus the current through the resistor viii 92 decreases, VCThe voltage is reduced; when the output load increases, VFBThe voltage decreases, the current through the second PNP transistor 72 increases, the current through the first PNP transistor 70 decreases, and thus the current through the resistor viii 92 increases, VCThe voltage increases.
In the reverse phase mode of operation, VFBThe voltage is 0V, the first PNP transistor 70 is turned off, all 4 muA current of the current source II 71 flows into the resistor III 82 and the resistor VIII 92 through the second PNP transistor 72, 4 muA current of the current source III 75 flows into the resistor V86, the resistor VII 90, the resistor IV 84 and the resistor VIII 92 through the third PNP transistor 74(2 muA) and the fourth PNP transistor 76(2 muA), 2 muA current of the current source IV 79 flows into the resistor V86 and the resistor VII 90 through the first NPN transistor 78, and 2 muA current of the current source V81 flows into the resistor VI 88 and the resistor VIII 92 through the second NPN transistor 80. Therefore, the current flowing through the resistor VIII 92 is 8 μ A, the current flowing through the resistor VI 88 is 2 μ A, the current flowing through the resistor VII 90 is 4 μ A, the current flowing through the resistor V86 is 4 μ A, the emitter voltage of the first NPN transistor 78 is 120mV, which is the sum of the voltage drop (40mV) of the resistor VII 90 and the voltage drop (80mV) of the resistor V86, the emitter voltage of the second NPN transistor 80 is 120mV, which is the sum of the voltage drop (80mV) of the resistor VIII 92 and the voltage drop (40mV) of the resistor VI 88, the emitter voltages of the first NPN transistor 78 and the second NPN transistor 80 are identical, the collector voltage V of the second NPN transistor 80 is equal to the emitter voltage of the first NPN transistor 78, and the emitter voltage ofCAt a certain voltage value.
When the output load increases, VFBThe voltage increases and the current through the third PNP transistor 74 decreases and flows through the fourth PNP transistor 76The current flowing through the resistor viii 92 is increased, VCThe voltage rises; when the output load is reduced, VFBThe voltage decreases, the current through the third PNP transistor 74 increases, the current through the fourth PNP transistor 76 decreases, and therefore the current through resistor viii 92 decreases, VCThe voltage is reduced.
In the present invention, the terms "connected", "connecting", and the like mean electrically connected, and mean directly or indirectly electrically connected unless otherwise specified. The first port and the second port of all the resistors are defined according to the flowing direction of the current, one end of the current passing through the resistor firstly is the first port, and the other end of the current passing through the resistor is the second port.
In light of the foregoing description of the preferred embodiment of the present invention, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the invention. The technical scope of the present invention is not limited to the contents of the specification, and must be determined according to the scope of the claims.

Claims (2)

1. A single feedback loop having a positive output voltage and a negative output voltage for a voltage converter, comprising:
an external resistor (1), a first port of the external resistor (1) and an output voltage V of the converterOUTThe second port of the external resistor (1) is connected with a feedback pin V of the conversion chip (10)FBConnecting;
the circuit comprises a conversion chip (10), wherein a feedback part circuit in the conversion chip (10) comprises a resistor I (50) and a resistor II (52), a first port of the resistor I (50) and a reference voltage V generated inside the chipREFThe second port of the resistor I (50) is connected with the first port of the resistor II (52), the second port of the resistor II (52) is grounded, and the connecting node of the resistor I (50) and the resistor II (52) is connected with the feedback pin V of the conversion chip (10)FBConnecting;
further comprising a first error amplifier (40) and a second error amplifier (41), the positive input of the first error amplifier (40) beingTerminal and reference voltage VREFThe negative input end of the first error amplifier (40) is connected with the positive input end of the second error amplifier (41), the negative input end of the second error amplifier (41) is grounded, and a node (51) of the negative input end of the first error amplifier (40) connected with the positive input end of the second error amplifier (41) is connected with the feedback pin end of the conversion chip (10);
the first error amplifier (40) is connected with a current source I through a diode I (56), the anode of the diode I (56) is connected with the current source I, the cathode of the diode I (56) is connected with the output of the first error amplifier (40), the second error amplifier (41) is connected with the current source I through a diode II (58), the anode of the diode II (58) is connected with the current source I, the cathode of the diode II (58) is connected with the output of the second error amplifier (41), and the node at which the anode of the diode I (56) is connected with the anode of the diode II (58) is used as an output control signal VC。
2. The single feedback loop with positive and negative output voltages for a suitable voltage converter of claim 1, the circuit is characterized in that the first error amplifier (40) and the second error amplifier (41) comprise a first PNP transistor (70), a second PNP transistor (72), a third PNP transistor (74) and a fourth PNP transistor (76), a first NPN transistor (78) and a second NPN transistor (80), a resistor III (82), a resistor IV (84), a resistor V (86), a resistor VI (88), a resistor VII (90) and a resistor VIII (92), the emitters of the first PNP transistor (70) and the second PNP transistor (72) are mutually connected with a current source II (71), the emitters of the third PNP transistor (74) and the fourth PNP transistor (76) are mutually connected with a current source III (75), and the base of the first PNP transistor (70) is connected with V.REFThe bases of the second PNP transistor (72) and the third PNP transistor (74) are interconnected with VFBThe base of the fourth PNP transistor (76) is grounded;
the base and collector of the first NPN transistor (78) are interconnected to a current source IV (79), the collector of the second NPN transistor (80) is connected to a current source V (81), and the connection node provides an output VCThe base of the first NPN transistor (78) is connected with the base of the second NPN transistor (80), and the resistor V (86) and the resistor VII (90) are connected in seriesThe PNP transistor is coupled between the emitter of the first NPN transistor (78) and the ground, the collectors of the second PNP transistor (72) and the third PNP transistor (74) are interconnected with the emitter of the first NPN transistor (78), the collectors of the second PNP transistor (72) and the fourth PNP transistor (76) are interconnected between a resistor VI (88) and a resistor VIII (92) through a resistor III (82) and a resistor IV (84), respectively, and the first NPN transistor (78) and the second NPN transistor (80) are matched with each other to form a current mirror structure.
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