TW202037049A - Time signal generator - Google Patents

Time signal generator Download PDF

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TW202037049A
TW202037049A TW108142759A TW108142759A TW202037049A TW 202037049 A TW202037049 A TW 202037049A TW 108142759 A TW108142759 A TW 108142759A TW 108142759 A TW108142759 A TW 108142759A TW 202037049 A TW202037049 A TW 202037049A
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signal
digital
load current
compensation
time
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TW108142759A
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TWI789561B (en
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張志廉
洪偉修
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力智電子股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output

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  • Dc-Dc Converters (AREA)
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Abstract

A time signal generator generating a time signal for a DC-DC conversion circuit to convert an input voltage into an output voltage is disclosed. The DC-DC conversion circuit is coupled to a loading and a loading current flowing through the loading. The time signal generator includes an analog-to-digital converting unit, a compensation unit, a counting unit, a comparing unit and a logic unit. The analog-to-digital converting unit receives an output voltage, an input voltage and the loading current and converts them into corresponding digital signals. The compensation unit receives the digital signals and processes the digital signals to generate a compensation signal. The counting unit provides a counting signal according to a clock signal and a trigger signal. The comparing unit receives the compensation signal and the counting signal to provide a comparison signal. The logic unit receives the trigger signal and the comparison signal to provide the time signal.

Description

時間信號產生器Time signal generator

本發明與直流對直流轉換電路有關，特別是關於一種應用於直流對直流轉換電路中的時間信號產生器。The invention relates to a DC-to-DC conversion circuit, and particularly relates to a time signal generator applied in a DC-to-DC conversion circuit.

當具有恆定導通時間的直流對直流轉換電路運作於重載穩態時，由於其導通時間為恆定，為了抵消電路中的元件寄生電阻造成的電源轉換損耗，其提供的時間信號的關斷時間會縮短(如圖1A中的關斷時間的長度由TOFF1縮短為TOFF2所示)，開關切換週期變短，而通過輸出電感的電感電流的平均值則會變大(如圖1B中的電感電流由Iind1變為Iind2所示)。When a DC-to-DC conversion circuit with a constant on-time is operating in a heavy-load steady state, since its on-time is constant, in order to offset the power conversion loss caused by the parasitic resistance of the components in the circuit, the off time of the time signal provided by it will be changed. Shorten (as shown in Figure 1A, the length of the turn-off time is shortened from TOFF1 to TOFF2), the switching cycle becomes shorter, and the average value of the inductor current through the output inductor will become larger (the inductor current in Figure 1B is changed from Iind1 becomes as Iind2).

然而，時間信號的週期變短，代表著直流對直流轉換電路的輸出級的開關頻率增加，導致直流對直流轉換電路運作於重載穩態時的電源轉換效率變差，此一缺點亟待克服。However, the shortening of the period of the time signal represents an increase in the switching frequency of the output stage of the DC-to-DC conversion circuit, resulting in poor power conversion efficiency when the DC-to-DC conversion circuit operates in a heavy load steady state. This shortcoming needs to be overcome.

有鑑於此，本發明提供一種時間信號產生器，以解決先前技術所述及的問題。In view of this, the present invention provides a time signal generator to solve the problems mentioned in the prior art.

本發明的一較佳具體實施例為一種時間信號產生器。於此實施例中，時間信號產生器產生時間信號以使直流對直流轉換電路將輸入電壓轉換為輸出電壓。直流對直流轉換電路耦接負載，並有負載電流流經負載。時間信號產生器包括類比數位轉換單元、補償單元、計數單元、比較單元及邏輯單元。類比數位轉換單元分別接收輸出電壓、輸入電壓及負載電流，並分別轉換為數位輸入電壓信號、數位輸出電壓信號及數位負載電流信號。補償單元分別接收數位輸出電壓信號、數位輸入電壓信號及數位負載電流信號，且對數位輸出電壓信號、數位輸入電壓信號及數位負載電流信號進行運算處理，以產生補償信號。計數單元依據時脈信號與觸發信號來提供計數信號。比較單元接收補償信號與計數信號以提供比較信號。邏輯單元接收觸發信號與比較信號以提供時間信號。A preferred embodiment of the present invention is a time signal generator. In this embodiment, the time signal generator generates a time signal to enable the DC-to-DC conversion circuit to convert the input voltage to the output voltage. The DC to DC conversion circuit is coupled to the load, and a load current flows through the load. The time signal generator includes an analog-digital conversion unit, a compensation unit, a counting unit, a comparison unit and a logic unit. The analog-digital conversion unit receives the output voltage, the input voltage and the load current respectively, and respectively converts them into a digital input voltage signal, a digital output voltage signal and a digital load current signal. The compensation unit receives the digital output voltage signal, the digital input voltage signal and the digital load current signal respectively, and performs arithmetic processing on the digital output voltage signal, the digital input voltage signal and the digital load current signal to generate the compensation signal. The counting unit provides a counting signal according to the clock signal and the trigger signal. The comparison unit receives the compensation signal and the count signal to provide a comparison signal. The logic unit receives the trigger signal and the comparison signal to provide a time signal.

在本發明的一實施例中，時間信號與數位輸入電壓信號、數位輸出電壓信號及數位負載電流信號有關。In an embodiment of the present invention, the time signal is related to the digital input voltage signal, the digital output voltage signal, and the digital load current signal.

在本發明的一實施例中，於重載期間，通過負載的負載電流增加，致使與負載電流相關的數位負載電流信號增加。補償單元所產生的補償信號及比較單元所提供的比較信號亦隨之增加。In an embodiment of the present invention, during heavy load, the load current passing through the load increases, causing the digital load current signal related to the load current to increase. The compensation signal generated by the compensation unit and the comparison signal provided by the comparison unit also increase accordingly.

在本發明的一實施例中，補償單元包括第一乘法器、第二乘法器、加法器及除法器。第一乘法器用以將數位負載電流信號乘以第一常數而得到第一乘積。第二乘法器用以將數位輸入電壓信號乘以第二常數而得到第二乘積。加法器耦接第一乘法器，用以將數位輸出電壓信號加上第一乘積而得到總和值。除法器耦接加法器及第二乘法器，用以將總和值除以第二乘積而得到補償信號。In an embodiment of the present invention, the compensation unit includes a first multiplier, a second multiplier, an adder, and a divider. The first multiplier is used to multiply the digital load current signal by a first constant to obtain a first product. The second multiplier is used to multiply the digital input voltage signal by a second constant to obtain a second product. The adder is coupled to the first multiplier for adding the first product to the digital output voltage signal to obtain the sum value. The divider is coupled to the adder and the second multiplier, and is used to divide the sum value by the second product to obtain a compensation signal.

在本發明的一實施例中，時間信號亦隨著總和值增加，且時間信號的增加量與數位負載電流信號的增加量有關。In an embodiment of the present invention, the time signal also increases with the total value, and the increase of the time signal is related to the increase of the digital load current signal.

在本發明的一實施例中，補償單元包括第一乘法器、第二乘法器、第一除法器、第二除法器及加法器。第一乘法器用以將數位負載電流信號乘以第一常數而得到第一乘積。第二乘法器用以將數位輸入電壓信號乘以第二常數而得到第二乘積。第一除法器耦接第一乘法器及第二乘法器，用以將負載電流信號除以第二乘積而得到第一商值。第二除法器耦接第二乘法器，用以將數位輸出電壓除以第二乘積而得到第二商值。加法器耦接第一除法器及第二除法器，用以相加第一商值與第二商值而得到補償信號。In an embodiment of the present invention, the compensation unit includes a first multiplier, a second multiplier, a first divider, a second divider, and an adder. The first multiplier is used to multiply the digital load current signal by a first constant to obtain a first product. The second multiplier is used to multiply the digital input voltage signal by a second constant to obtain a second product. The first divider is coupled to the first multiplier and the second multiplier for dividing the load current signal by the second product to obtain the first quotient. The second divider is coupled to the second multiplier for dividing the digital output voltage by the second product to obtain the second quotient value. The adder is coupled to the first divider and the second divider for adding the first quotient value and the second quotient value to obtain a compensation signal.

相較於先前技術，本發明的時間信號產生器能夠藉由與負載電流相關的補償信號來調整其提供的時間信號，因此，當直流對直流轉換電路運作於重載穩態而使得負載電流增加時，本發明的時間信號產生器時間信號所提供的時間信號的導通時間亦隨之增加，藉以維持直流對直流轉換電路的開關頻率恆定而提升直流對直流轉換電路運作於重載穩態時的電源轉換效率。Compared with the prior art, the time signal generator of the present invention can adjust the time signal provided by the compensation signal related to the load current. Therefore, when the DC-to-DC conversion circuit operates in a heavy load steady state, the load current increases At the same time, the on-time of the time signal provided by the time signal of the time signal generator of the present invention is also increased, so as to maintain the constant switching frequency of the DC-to-DC conversion circuit and improve the operation of the DC-to-DC conversion circuit under heavy load and steady state. Power conversion efficiency.

關於本發明的優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。The advantages and spirit of the present invention can be further understood through the following detailed description of the invention and the accompanying drawings.

現在將詳細參考本發明的示範性實施例，並在附圖中說明所述示範性實施例的實例。在圖式及實施方式中所使用相同或類似標號的元件/構件是用來代表相同或類似部分。Reference will now be made in detail to exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Elements/components with the same or similar numbers used in the drawings and embodiments are used to represent the same or similar parts.

根據本發明的一較佳具體實施例為一種時間信號產生器。於此實施例中，時間信號產生器應用於直流對直流轉換電路，用以產生時間信號。A preferred embodiment according to the present invention is a time signal generator. In this embodiment, the time signal generator is applied to the DC-DC conversion circuit to generate the time signal.

請參照圖2，圖2繪示此實施例中的時間信號產生器應用於直流對直流轉換電路的示意圖。如圖2所示，直流對直流轉換電路2耦接負載LD且有負載電流IL 流經負載LD。於重載期間，通過負載LD的負載電流IL 會增加。Please refer to FIG. 2. FIG. 2 illustrates a schematic diagram of the time signal generator in this embodiment applied to a DC-DC conversion circuit. As shown in FIG. 2, the DC to DC conversion circuit 2 is coupled to the load LD and a load current IL flows through the load LD. During heavy load, the load current IL through the load LD will increase.

直流對直流轉換電路2包含時間信號產生器1、驅動電路DR、輸出級OS及回授電路FB。時間信號產生器1耦接驅動電路DR及回授電路FB。驅動電路DR耦接時間信號產生器1及輸出級OS。輸出級OS耦接輸入電壓Vin、接地電壓GND、驅動電路DR、回授電路FB及負載LD並產生輸出電壓Vout。回授電路FB耦接輸出電壓Vout及時間信號產生器1。The DC-DC conversion circuit 2 includes a time signal generator 1, a driving circuit DR, an output stage OS and a feedback circuit FB. The time signal generator 1 is coupled to the driving circuit DR and the feedback circuit FB. The driving circuit DR is coupled to the time signal generator 1 and the output stage OS. The output stage OS is coupled to the input voltage Vin, the ground voltage GND, the driving circuit DR, the feedback circuit FB and the load LD, and generates an output voltage Vout. The feedback circuit FB is coupled to the output voltage Vout and the time signal generator 1.

時間信號產生器1分別接收輸入電壓Vin、輸出電壓Vout、負載電流IL、時脈信號CLK與觸發信號TR並提供時間信號Ton至驅動電路DR。驅動電路DR根據時間信號Ton產生第一驅動信號DS1及第二驅動信號DS2至輸出級OS。輸出級OS受第一驅動信號DS1及第二驅動信號DS2驅動而產生輸出電壓Vout。回授電路FB根據輸出電壓Vout產生觸發信號TR至時間信號產生器1。The time signal generator 1 respectively receives the input voltage Vin, the output voltage Vout, the load current IL, the clock signal CLK and the trigger signal TR, and provides the time signal Ton to the driving circuit DR. The driving circuit DR generates the first driving signal DS1 and the second driving signal DS2 to the output stage OS according to the time signal Ton. The output stage OS is driven by the first driving signal DS1 and the second driving signal DS2 to generate an output voltage Vout. The feedback circuit FB generates a trigger signal TR to the time signal generator 1 according to the output voltage Vout.

於實際應用中，輸出級OS包括串接於輸入電壓Vin與接地電壓GND之間的第一開關及第二開關，分別受第一驅動信號D1及第二驅動信號D2驅動而於第一開關及第二開關之間輸出電感電流Iind並產生輸出電壓Vout。In practical applications, the output stage OS includes a first switch and a second switch connected in series between the input voltage Vin and the ground voltage GND, which are driven by the first drive signal D1 and the second drive signal D2, respectively, and are connected between the first switch and the second switch. The inductor current Iind is output between the second switches and an output voltage Vout is generated.

請參照圖3，圖3繪示圖2中的時間信號產生器1的功能方塊圖。如圖3所示，時間信號產生器1包括類比數位轉換單元10、補償單元11、計數單元12、比較單元14及邏輯單元16。類比數位轉換單元10耦接至補償單元11。補償單元11及計數單元12均耦接至比較單元14。比較單元14耦接至邏輯單元16。Please refer to FIG. 3, which is a functional block diagram of the time signal generator 1 in FIG. As shown in FIG. 3, the time signal generator 1 includes an analog-to-digital conversion unit 10, a compensation unit 11, a counting unit 12, a comparison unit 14 and a logic unit 16. The analog-to-digital conversion unit 10 is coupled to the compensation unit 11. Both the compensation unit 11 and the counting unit 12 are coupled to the comparison unit 14. The comparison unit 14 is coupled to the logic unit 16.

類比數位轉換單元10分別接收輸出電壓Vout、輸入電壓Vin及負載電流IL，並分別轉換為數位輸出電壓信號SVout、數位輸入電壓信號SVin及數位負載電流信號SIL後提供至補償單元11。The analog-to-digital conversion unit 10 receives the output voltage Vout, the input voltage Vin, and the load current IL respectively, and converts them into a digital output voltage signal SVout, a digital input voltage signal SVin, and a digital load current signal SIL, respectively, and then provides them to the compensation unit 11.

補償單元11分別接收數位輸出電壓信號SVout、數位輸入電壓信號SVin及數位負載電流信號SIL，並對數位輸出電壓信號SVout、數位輸入電壓信號SVin及數位負載電流信號SIL進行運算處理後產生補償信號S1。計數單元12依據時脈信號CLK與觸發信號TR來提供計數信號S2。The compensation unit 11 receives the digital output voltage signal SVout, the digital input voltage signal SVin, and the digital load current signal SIL, respectively, and processes the digital output voltage signal SVout, the digital input voltage signal SVin, and the digital load current signal SIL to generate a compensation signal S1 . The counting unit 12 provides the counting signal S2 according to the clock signal CLK and the trigger signal TR.

比較單元14分別接收來自補償單元11的補償信號S1以及來自計數單元12的計數信號S2，並根據補償信號S1與計數信號S2提供比較信號S3至邏輯單元16。邏輯單元16分別接收觸發信號TR與比較信號S3，並根據觸發信號TR與比較信號S3提供時間信號Ton至驅動電路DR。The comparing unit 14 receives the compensation signal S1 from the compensation unit 11 and the counting signal S2 from the counting unit 12 respectively, and provides a comparison signal S3 to the logic unit 16 according to the compensation signal S1 and the counting signal S2. The logic unit 16 receives the trigger signal TR and the comparison signal S3 respectively, and provides the time signal Ton to the driving circuit DR according to the trigger signal TR and the comparison signal S3.

於實際應用中，時間信號產生器1的邏輯單元16所提供的時間信號Ton與數位輸入電壓信號SVin、數位輸出電壓信號SVout及數位負載電流信號SIL有關，但不以此為限。In practical applications, the time signal Ton provided by the logic unit 16 of the time signal generator 1 is related to the digital input voltage signal SVin, the digital output voltage signal SVout, and the digital load current signal SIL, but not limited to this.

於輕載期間，負載電流IL造成的補償值會被省略，邏輯單元16提供的時間信號Ton維持不變。於重載期間，通過負載LD的負載電流IL增加，致使與負載電流IL相關的數位負載電流信號SIL增加，而補償單元11根據數位負載電流信號SIL所產生的補償信號S1以及比較單元14根據補償信號S1提供的比較信號S3亦會隨之增加，使得邏輯單元16提供的時間信號Ton亦會隨著比較信號S3增加且時間信號Ton的增加量會與數位負載電流信號SIL的增加量有關，但不以此為限。During the light load period, the compensation value caused by the load current IL is omitted, and the time signal Ton provided by the logic unit 16 remains unchanged. During the heavy load period, the load current IL passing through the load LD increases, causing the digital load current signal SIL related to the load current IL to increase, and the compensation unit 11 generates the compensation signal S1 according to the digital load current signal SIL and the comparison unit 14 according to the compensation The comparison signal S3 provided by the signal S1 will also increase, so that the time signal Ton provided by the logic unit 16 will also increase with the comparison signal S3 and the increase in the time signal Ton will be related to the increase in the digital load current signal SIL, but Not limited to this.

請參照圖4A，圖4A繪示數位式的時間信號產生器的一實施例。如圖4A所示，時間信號產生器1包括補償單元11、計數單元12、比較單元14及邏輯單元16。補償單元11包括第一乘法器M1、第二乘法器M2、加法器ADD及除法器DIV。加法器ADD耦接第一乘法器M1。除法器DIV耦接加法器ADD及第二乘法器M2。Please refer to FIG. 4A. FIG. 4A shows an embodiment of a digital time signal generator. As shown in FIG. 4A, the time signal generator 1 includes a compensation unit 11, a counting unit 12, a comparison unit 14, and a logic unit 16. The compensation unit 11 includes a first multiplier M1, a second multiplier M2, an adder ADD, and a divider DIV. The adder ADD is coupled to the first multiplier M1. The divider DIV is coupled to the adder ADD and the second multiplier M2.

第一乘法器M1用以將數位負載電流信號SIL乘以第一常數ki而得到第一乘積(ki*SIL)。第二乘法器M2用以將數位輸入電壓信號SVin乘以第二常數kv而得到第二乘積(kv*SVin)。加法器ADD用以將數位輸出電壓信號SVout加上第一乘積ki*SIL而得到總和值SUM=(SVout+ki*SIL)。除法器DIV用以將總和值SUM除以第二乘積(kv*SVin)而得到補償信號S1，亦即補償信號S1=(SVout+ki*SIL)/ (kv*SVin)。The first multiplier M1 is used to multiply the digital load current signal SIL by a first constant ki to obtain a first product (ki*SIL). The second multiplier M2 is used to multiply the digital input voltage signal SVin by a second constant kv to obtain a second product (kv*SVin). The adder ADD is used to add the digital output voltage signal SVout to the first product ki*SIL to obtain the sum value SUM=(SVout+ki*SIL). The divider DIV is used to divide the sum value SUM by the second product (kv*SVin) to obtain the compensation signal S1, that is, the compensation signal S1=(SVout+ki*SIL)/(kv*SVin).

計數單元12依據時脈信號CLK與觸發信號TR來提供計數信號S2。比較單元14分別接收來自補償單元11的補償信號S1以及來自計數單元12的計數信號S2，並根據補償信號S1與計數信號S2提供比較信號S3至邏輯單元16。邏輯單元16分別接收觸發信號TR與比較信號S3，並根據觸發信號TR與比較信號S3提供時間信號Ton至驅動電路DR。The counting unit 12 provides the counting signal S2 according to the clock signal CLK and the trigger signal TR. The comparing unit 14 receives the compensation signal S1 from the compensation unit 11 and the counting signal S2 from the counting unit 12 respectively, and provides a comparison signal S3 to the logic unit 16 according to the compensation signal S1 and the counting signal S2. The logic unit 16 receives the trigger signal TR and the comparison signal S3 respectively, and provides the time signal Ton to the driving circuit DR according to the trigger signal TR and the comparison signal S3.

需說明的是，提供至補償單元11的數位輸出電壓信號SVout、數位輸入電壓信號SVin及數位負載電流信號SIL可由類比數位轉換單元10分別轉換輸出電壓Vout、輸入電壓Vin及負載電流IL而得，但不以此為限。It should be noted that the digital output voltage signal SVout, digital input voltage signal SVin, and digital load current signal SIL provided to the compensation unit 11 can be obtained by converting the output voltage Vout, input voltage Vin, and load current IL by the analog-digital conversion unit 10, respectively. But not limited to this.

請參照圖4B，圖4B繪示數位式的時間信號產生器的另一實施例。如圖4B所示，時間信號產生器1包括補償單元11、計數單元12、比較單元14及邏輯單元16。補償單元11包括第一乘法器M1、第二乘法器M2、第一除法器DIV1、第二除法器DIV2及加法器ADD。第一乘法器M1耦接第一除法器DIV1。第二乘法器M2耦接除法器DIV耦接第一除法器DIV1及第二除法器DIV2。第一除法器DIV1及第二除法器DIV2均耦接加法器ADD。Please refer to FIG. 4B. FIG. 4B shows another embodiment of a digital time signal generator. As shown in FIG. 4B, the time signal generator 1 includes a compensation unit 11, a counting unit 12, a comparison unit 14, and a logic unit 16. The compensation unit 11 includes a first multiplier M1, a second multiplier M2, a first divider DIV1, a second divider DIV2, and an adder ADD. The first multiplier M1 is coupled to the first divider DIV1. The second multiplier M2 is coupled to the divider DIV and coupled to the first divider DIV1 and the second divider DIV2. The first divider DIV1 and the second divider DIV2 are both coupled to the adder ADD.

第一乘法器M1用以將數位負載電流信號SIL乘以第一常數ki而得到第一乘積(ki*SIL)。第二乘法器M2用以將數位輸入電壓SVin信號乘以第二常數kv而得到第二乘積(kv*SVin)。第一除法器DIV1用以將第一乘積(ki*SIL)除以第二乘積(kv*SVin)而得到第一商值(ki*SIL)/(kv*SVin)。第二除法器DIV2用以將數位輸出電壓信號SVout除以第二乘積(kv*SVin)而得到第二商值SVout/(kv*SVin)。加法器ADD用以將第一商值(ki*SIL)/(kv*SVin)與第二商值SVout/(kv*SVin)相加而得到補償信號S1，亦即補償信號S1=(SVout+ki*SIL)/ (kv*SVin)。The first multiplier M1 is used to multiply the digital load current signal SIL by a first constant ki to obtain a first product (ki*SIL). The second multiplier M2 is used to multiply the digital input voltage SVin signal by a second constant kv to obtain a second product (kv*SVin). The first divider DIV1 is used to divide the first product (ki*SIL) by the second product (kv*SVin) to obtain the first quotient value (ki*SIL)/(kv*SVin). The second divider DIV2 is used to divide the digital output voltage signal SVout by the second product (kv*SVin) to obtain the second quotient value SVout/(kv*SVin). The adder ADD is used to add the first quotient value (ki*SIL)/(kv*SVin) and the second quotient value SVout/(kv*SVin) to obtain the compensation signal S1, that is, the compensation signal S1=(SVout+ ki*SIL)/ (kv*SVin).

需說明的是，提供至補償單元11的數位輸出電壓信號SVout、數位輸入電壓信號SVin及數位負載電流信號SIL可由類比數位轉換單元10分別轉換輸出電壓Vout、輸入電壓Vin及負載電流IL而得，但不以此為限。It should be noted that the digital output voltage signal SVout, digital input voltage signal SVin, and digital load current signal SIL provided to the compensation unit 11 can be obtained by converting the output voltage Vout, input voltage Vin, and load current IL by the analog-digital conversion unit 10, respectively. But not limited to this.

接著，請參照圖5A至圖5D。圖5A及圖5B分別繪示習知的數位式時間信號產生器與本發明的數位式時間信號產生器在輕載穩態下所提供的時間信號的示意圖。圖5C及圖5D分別繪示習知的數位式時間信號產生器與本發明的數位式時間信號產生器在重載穩態下的所提供的時間信號的示意圖。Next, please refer to FIGS. 5A to 5D. 5A and 5B show schematic diagrams of the time signal provided by the conventional digital time signal generator and the digital time signal generator of the present invention under light load and steady state, respectively. 5C and 5D show schematic diagrams of the time signal provided by the conventional digital time signal generator and the digital time signal generator of the present invention under heavy load and steady state, respectively.

如圖5A及圖5B所示，在輕載穩態下，因為數位電路的特性，微小的計算誤差(例如輕載狀態下的負載電流造成的補償值)會被省略，所以習知的數位式時間信號產生器所提供的時間信號Ton1的週期D1及導通時間的長度T1與本發明的數位式時間信號產生器所提供的時間信號Ton2的週期D2及導通時間的長度T2不變，例如兩者的週期均為1000ns且兩者的導通時間的長度均為300ns。As shown in Figures 5A and 5B, in the light-load steady state, due to the characteristics of the digital circuit, small calculation errors (such as the compensation value caused by the load current in the light-load state) will be omitted, so the conventional digital formula The period D1 and on-time length T1 of the time signal Ton1 provided by the time signal generator and the period D2 and on-time length T2 of the time signal Ton2 provided by the digital time signal generator of the present invention remain unchanged, for example, both The period of both is 1000ns and the length of the on-time of both is 300ns.

如圖5C所示，在重載穩態下，習知的數位式時間信號產生器所提供的時間信號Ton1的導通時間的長度T1’仍維持在300ns，但這也導致時間信號Ton1的週期D1’從1000ns變成860ns，總共縮短了140ns之多，造成習知的直流對直流轉換電路的開關頻率變高而影響其電源轉換效率。As shown in FIG. 5C, in the heavy load steady state, the on-time length T1' of the time signal Ton1 provided by the conventional digital time signal generator is still maintained at 300ns, but this also results in the period D1 of the time signal Ton1 'From 1000ns to 860ns, a total of 140ns is shortened, which causes the switching frequency of the conventional DC-to-DC converter circuit to increase and affect its power conversion efficiency.

相較之下，如圖5D所示，在重載穩態下，本發明的數位式時間信號產生器所提供的時間信號Ton2的導通時間的長度T2’會隨著負載電流增加而從300ns變成340ns，而時間信號Ton2的週期D2’僅會從1000ns變成995ns，總共僅縮短了5ns而已，故本發明的能維持直流對直流轉換電路的開關頻率恆定而提升其電源轉換效率。In contrast, as shown in Figure 5D, in the heavy load steady state, the on-time length T2' of the time signal Ton2 provided by the digital time signal generator of the present invention will change from 300ns to 300ns as the load current increases. 340 ns, and the period D2' of the time signal Ton2 will only change from 1000 ns to 995 ns, which is only shortened by 5 ns in total. Therefore, the present invention can maintain the constant switching frequency of the DC-to-DC converter circuit and improve its power conversion efficiency.

相較於先前技術，本發明的時間信號產生器能夠藉由與負載電流相關的補償信號來調整其提供給直流對直流轉換電路的驅動電路的時間信號，因此，當直流對直流轉換電路運作於重載穩態而使得負載電流增加時，本發明的時間信號產生器時間信號所提供的時間信號中的導通時間亦隨之增加，藉以維持直流對直流轉換電路的開關頻率恆定而提升直流對直流轉換電路運作於重載穩態時的電源轉換效率。Compared with the prior art, the time signal generator of the present invention can adjust the time signal provided to the driving circuit of the DC-DC conversion circuit by the compensation signal related to the load current. Therefore, when the DC-DC conversion circuit operates When the load current increases due to the heavy load steady state, the on-time in the time signal provided by the time signal generator of the present invention also increases, so as to maintain the constant switching frequency of the DC-DC conversion circuit and increase the DC-DC The conversion efficiency of the power supply when the conversion circuit operates under heavy load and steady state.

藉由以上較佳具體實施例的詳述，係希望能更加清楚描述本發明的特徵與精神，而並非以上述所揭露的較佳具體實施例來對本發明的範疇加以限制。相反地，其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請的專利範圍的範疇內。Based on the detailed description of the preferred embodiments above, it is hoped that the characteristics and spirit of the present invention can be described more clearly, rather than limiting the scope of the present invention by the preferred embodiments disclosed above. On the contrary, the purpose is to cover various changes and equivalent arrangements within the scope of the patent application for the present invention.

Ton1、Ton2:時間信號 Toff1、Toff2:關斷時間的長度 Iind1、Iind2:電感電流 2:直流對直流轉換電路 1:時間信號產生器 10:類比數位轉換單元 11:補償單元 12:計數單元 14:比較單元 16:邏輯單元 DR:驅動電路 OS:輸出級 LD:負載 FB:回授電路 CLK:時脈信號 TR:觸發信號 GND:接地電壓 SVout:數位輸出電壓信號 Vout:輸出電壓 SVin:數位輸入電壓信號 Vin:輸入電壓 SIL:數位負載電流信號 IL:負載電流 S1:補償信號 S2:計數信號 S3:比較信號 Ton:時間信號 DS1:第一驅動信號 DS2:第二驅動信號 M1:第一乘法器 M2:第二乘法器 DIV:除法器 DIV1:第一除法器 DIV2:第二除法器 ADD:加法器 SUM:總和值 T1、T2、T1’、T2’:導通時間的長度 D1、D2、D1’、D2’:時間信號的週期Ton1, Ton2: Time signal Toff1, Toff2: length of off time Iind1, Iind2: inductor current 2: DC to DC conversion circuit 1: Time signal generator 10: Analog to digital conversion unit 11: Compensation unit 12: Counting unit 14: Comparison unit 16: logic unit DR: drive circuit OS: output stage LD: load FB: feedback circuit CLK: clock signal TR: trigger signal GND: Ground voltage SVout: Digital output voltage signal Vout: output voltage SVin: Digital input voltage signal Vin: input voltage SIL: Digital load current signal IL: Load current S1: Compensation signal S2: counting signal S3: compare signal Ton: Time signal DS1: the first drive signal DS2: second drive signal M1: first multiplier M2: second multiplier DIV: divider DIV1: First divider DIV2: second divider ADD: adder SUM: Sum value T1, T2, T1’, T2’: Length of on-time D1, D2, D1’, D2’: period of time signal

本發明所附圖式說明如下： 圖1A繪示習知的直流對直流轉換電路提供的脈寬調變信號的關斷時間及週期在重載穩態下會縮短的示意圖。 圖1B繪示習知的直流對直流轉換電路的電感電流的平均值在重載穩態下會變大且其週期會變短的示意圖。 圖2繪示本發明的一較佳具體實施例中的時間信號產生器應用於直流對直流轉換電路的示意圖。 圖3繪示圖2中的時間信號產生器的功能方塊圖。 圖4A繪示數位式的時間信號產生器的一實施例。 圖4B繪示數位式的時間信號產生器的另一實施例。 圖5A及圖5B分別繪示習知的數位式時間信號產生器與本發明的數位式時間信號產生器在輕載穩態下所提供的時間信號的示意圖。 圖5C及圖5D分別繪示習知的數位式時間信號產生器與本發明的數位式時間信號產生器在重載穩態下的所提供的時間信號的示意圖。The drawings of the present invention are described as follows: FIG. 1A is a schematic diagram showing that the turn-off time and period of the pulse width modulation signal provided by the conventional DC-to-DC conversion circuit are shortened under heavy load and steady state. FIG. 1B is a schematic diagram showing that the average value of the inductor current of the conventional DC-to-DC conversion circuit becomes larger and its period becomes shorter under heavy load and steady state. FIG. 2 is a schematic diagram of the time signal generator in a preferred embodiment of the present invention applied to a DC-DC conversion circuit. FIG. 3 is a functional block diagram of the time signal generator in FIG. 2. FIG. 4A shows an embodiment of a digital time signal generator. FIG. 4B shows another embodiment of the digital time signal generator. 5A and 5B show schematic diagrams of the time signal provided by the conventional digital time signal generator and the digital time signal generator of the present invention under light load and steady state, respectively. 5C and 5D show schematic diagrams of the time signal provided by the conventional digital time signal generator and the digital time signal generator of the present invention under heavy load and steady state, respectively.

1:時間信號產生器 1: Time signal generator

10:類比數位轉換單元 10: Analog to digital conversion unit

11:補償單元 11: Compensation unit

12:計數單元 12: Counting unit

14:比較單元 14: Comparison unit

16:邏輯單元 16: logic unit

CLK:時脈信號 CLK: clock signal

TR:觸發信號 TR: trigger signal

SVout:數位輸出電壓信號 SVout: Digital output voltage signal

SVin:數位輸入電壓信號 SVin: Digital input voltage signal

SIL:數位負載電流信號 SI L : Digital load current signal

Vout:輸出電壓 Vout: output voltage

Vin:輸入電壓 Vin: input voltage

IL:負載電流 I L : Load current

S1:補償信號 S1: Compensation signal

S2:計數信號 S2: counting signal

S3:比較信號 S3: compare signal

Ton:時間信號 Ton: Time signal

Claims (6)

一種時間信號產生器，產生一時間信號以使一直流對直流轉換電路將一輸入電壓轉換為一輸出電壓，該直流對直流轉換電路耦接一負載，並有一負載電流流經該負載，該時間信號產生器包括： 一類比數位轉換單元，分別接收該輸出電壓、該輸入電壓及該負載電流，並分別轉換為一數位輸出電壓信號、一數位輸入電壓信號及一數位負載電流信號； 一補償單元，分別接收該數位輸出電壓信號、該數位輸入電壓信號及該數位負載電流信號，且對該數位輸出電壓信號、該數位輸入電壓信號及該數位負載電流信號進行一運算處理，以產生一補償信號； 一計數單元，依據一時脈信號與一觸發信號來提供一計數信號； 一比較單元，接收該補償信號與該計數信號以提供一比較信號；以及 一邏輯單元，接收該觸發信號與該比較信號以提供該時間信號。A time signal generator generates a time signal so that a DC-to-DC conversion circuit converts an input voltage into an output voltage. The DC-to-DC conversion circuit is coupled to a load and a load current flows through the load. The signal generator includes: An analog-to-digital conversion unit that receives the output voltage, the input voltage, and the load current respectively, and converts them into a digital output voltage signal, a digital input voltage signal, and a digital load current signal; A compensation unit that receives the digital output voltage signal, the digital input voltage signal, and the digital load current signal, and performs an arithmetic processing on the digital output voltage signal, the digital input voltage signal, and the digital load current signal to generate A compensation signal; A counting unit, which provides a counting signal according to a clock signal and a trigger signal; A comparison unit that receives the compensation signal and the count signal to provide a comparison signal; and A logic unit receives the trigger signal and the comparison signal to provide the time signal. 如申請專利範圍第1項所述的時間信號產生器，其中該時間信號與該數位輸入電壓信號、該數位輸出電壓信號及該數位負載電流信號有關。The time signal generator described in item 1 of the scope of patent application, wherein the time signal is related to the digital input voltage signal, the digital output voltage signal, and the digital load current signal. 如申請專利範圍第1項所述的時間信號產生器，其中於重載期間，流經該負載的該負載電流增加，致使與該負載電流相關的該數位負載電流信號增加，該補償單元所產生的該補償信號及該比較單元所提供的該比較信號亦隨之增加。The time signal generator described in the first item of the scope of patent application, wherein during heavy load, the load current flowing through the load increases, causing the digital load current signal related to the load current to increase, and the compensation unit generates The compensation signal and the comparison signal provided by the comparison unit also increase accordingly. 如申請專利範圍第1項所述的時間信號產生器，其中該補償單元包括： 一第一乘法器，用以將該數位負載電流信號乘以一第一常數而得到一第一乘積； 一第二乘法器，用以將該數位輸入電壓信號乘以一第二常數而得到一第二乘積； 一加法器，耦接該第一乘法器，用以將該數位輸出電壓信號加上該第一乘積而得到一總和值；以及 一除法器，耦接該加法器及該第二乘法器，用以將該總和值除以該第二乘積而得到該補償信號。The time signal generator described in item 1 of the scope of patent application, wherein the compensation unit includes: A first multiplier for multiplying the digital load current signal by a first constant to obtain a first product; A second multiplier for multiplying the digital input voltage signal by a second constant to obtain a second product; An adder, coupled to the first multiplier, for adding the digital output voltage signal to the first product to obtain a total value; and A divider, coupled to the adder and the second multiplier, is used to divide the sum value by the second product to obtain the compensation signal. 如申請專利範圍第4項所述的時間信號產生器，其中該時間信號亦隨著該總和值增加，且該時間信號的增加量與該數位負載電流信號的增加量有關。For the time signal generator described in item 4 of the scope of patent application, the time signal also increases with the total value, and the increase of the time signal is related to the increase of the digital load current signal. 如申請專利範圍第1項所述的時間信號產生器，其中該補償單元包括： 一第一乘法器，用以將該數位負載電流信號乘以一第一常數而得到一第一乘積； 一第二乘法器，用以將該數位輸入電壓信號乘以一第二常數而得到一第二乘積； 一第一除法器，耦接該第一乘法器及該第二乘法器，用以將該負載電流信號除以該第二乘積而得到一第一商值； 一第二除法器，耦接該第二乘法器，用以將該數位輸出電壓除以該第二乘積而得到一第二商值；以及 一加法器，耦接該第一除法器及該第二除法器，用以相加該第一商值與該第二商值而得到該補償信號。The time signal generator described in item 1 of the scope of patent application, wherein the compensation unit includes: A first multiplier for multiplying the digital load current signal by a first constant to obtain a first product; A second multiplier for multiplying the digital input voltage signal by a second constant to obtain a second product; A first divider, coupled to the first multiplier and the second multiplier, for dividing the load current signal by the second product to obtain a first quotient; A second divider, coupled to the second multiplier, for dividing the digital output voltage by the second product to obtain a second quotient; and An adder, coupled to the first divider and the second divider, is used to add the first quotient value and the second quotient value to obtain the compensation signal.
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