TWI734271B - 具有縮減記憶體通道長度之雙側安裝式大型mcm封裝 - Google Patents

具有縮減記憶體通道長度之雙側安裝式大型mcm封裝 Download PDF

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TWI734271B
TWI734271B TW108143068A TW108143068A TWI734271B TW I734271 B TWI734271 B TW I734271B TW 108143068 A TW108143068 A TW 108143068A TW 108143068 A TW108143068 A TW 108143068A TW I734271 B TWI734271 B TW I734271B
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substrate
wiring
module
bottom side
double
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TW108143068A
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TW202040787A (zh
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仲崇華
軍 翟
胡坤忠
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美商蘋果公司
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Abstract

本文描述併入此類雙側安裝式封裝結構的雙側安裝式封裝結構及記憶體模組，其中記憶體封裝係安裝在一模組基材的兩側上。一佈線基材經安裝至該模組基材之一底部側，以提供通用型輸入/輸出佈線及功率佈線，而模組佈線內提供自邏輯晶粒至雙側安裝記憶體封裝的信號佈線。在一實施例中，模組基材係一無芯模組基材，且可比佈線基材更薄。

Description

具有縮減記憶體通道長度之雙側安裝式大型MCM封裝
本文所述之實施例係關於多晶片模組封裝，且更具體地係關於記憶體封裝。
目前，可攜式及行動電子裝置（諸如，行動電話、個人數位助理(personal digital assistant, PDA)、數位相機、可攜式播放器、遊戲、及其他行動裝置）的市場需求要求將更多效能及特徵整合至越來越小的空間中。然而，操作此等裝置所需的記憶體量已顯著增加。
低功率雙資料速率(low power double data rate, LPDDR)標準已長期橫跨在多種市場（包括行動電子產品）中採用，以滿足效能及容量需求。LPDDR平台及下一代(LPDDR-x)常常包括圍繞邏輯晶粒（例如系統單晶片(system on chip, SOC)）的記憶體晶片或封裝之配置，其可包括中央處理單元(central processing unit, CPU)及/或圖形處理單元(graphics processing unit, CPU)。為了滿足增加頻寬的需求，已提出包括堆疊之動態隨機存取記憶體(dynamic random-access memory, DRAM)晶粒的各種3D解決方案，諸如高頻寬記憶體(high bandwidth memory, HBM)及混合記憶體立方體(hybrid memory cube, HMC)。
本文描述雙側式安裝封裝結構以及併入此類雙側安裝式封裝結構的記憶體模組。
在一實施例中，一雙側安裝式封裝結構包括：一模組基材、安裝在該模組基材之一頂部側上的一第一邏輯晶粒、安裝在該模組基材之該頂部側上的一第一複數個記憶體封裝、安裝在該模組基材之一底部側上的一第二複數個記憶體封裝、及安裝至該模組基材之該底部側且在該第一邏輯晶粒正下方的一佈線基材。複數個接觸件係位於該佈線基材之一底部側上。通用型輸入/輸出佈線及電源佈線經提供通過該佈線基材及該模組基材，以連接在該佈線基材之該底部側上的該複數個接觸件及該第一邏輯晶粒。信號佈線係在該模組基材內提供，以將該第一邏輯晶粒與該第一複數個記憶體封裝及該第二複數個記憶體封裝兩者連接。
在一實施例中，一雙側安裝式封裝結構包括：一無芯模組基材、安裝在該無芯模組基材之一頂部側上的一第一邏輯晶粒、安裝在該無芯模組基材之該頂部側上的一第一複數個記憶體封裝、安裝至該無芯模組基材之一底部側上的一第二複數個記憶體封裝、及安裝至該無芯模組基材之該底部側且在該第一邏輯晶粒正下方的一層壓佈線基材。複數個接觸件係位於該層壓佈線基材之一底部側上。第一佈線經提供通過該層壓佈線基材及該無芯模組基材，以連接在該層壓佈線基材之該底部側上的該複數個接觸件及該第一邏輯晶粒。第二佈線經提供在無芯模組基材內，以將該第一邏輯晶粒與該第一複數個記憶體封裝及該第二複數個記憶體封裝兩者連接。
實施例描述雙側安裝式封裝結構及併入此類雙側安裝式封裝結構的記憶體模組，其中記憶體封裝係安裝在一模組基材的兩側上，以縮減整體封裝尺寸及記憶體通道長度。
在一態樣中，已經觀察到：隨著記憶體需求增加，該等記憶體封裝對於整體多晶片模組(multi-chip module, MCM)的封裝尺寸具有顯著影響。較大型的MCM封裝可能造成記憶體通道長度增加及效能退化。此外，基材產出及循環時間可因為層數及進階設計規則的緣故而成為在大型的MCM覆晶球柵陣列(flip chip ball grid array, FCBGA)封裝中的挑戰。
根據實施例，模組基材經垂直整合以縮減記憶體通道長度、縮減整體MCM封裝尺寸並縮減MCM封裝高度。此外，堆疊整合方案可減少模組基材設計複雜度、縮短基材循環時間、及增加基材產出。此可藉由使在一模組基材內之高密度、複雜的細間距信號佈線與在堆疊佈線基材內之較小臨界、較粗間距的板佈線分隔來達成。例如，相較於可具有二十多層以容納所有所需之通用型輸入/輸出佈線、電源佈線、及信號佈線的一較傳統之MCM有芯基材，該模組基材可係一無芯或薄芯基材。根據實施例之該經分隔基材設計可額外地允許MCM封裝高度縮減。
在各種實施例中，參照圖式進行說明。然而，某些實施例可在無這些特定細節之一或多者的情況下實行或可與其他已知的方法及組態結合實行。在下列敘述中，為了提供對實施例的全面瞭解而提出眾多特定細節（例如，特定組態、尺寸、及程序等）。在其他例子中，為了避免不必要地使本實施例失焦，所以並未特別詳細地敘述公知的半導體程序及製造技術。此專利說明書通篇指稱的「一實施例(one embodiment)」係指與該實施例一同描述之具體特徵、結構、組態、或特性係包括在至少一實施例中。因此，此專利說明書通篇於各處出現之詞組「在一實施例中(in one embodiment)」不必然指稱相同實施例。此外，在一或多個實施例中，可以任何合適的方式結合特定特徵、結構、組態、或特性。
如本文所使用之用語「頂部(top)」、「底部(bottom)」、「之下(under)」、「至(to)」、「介於…之間(between)」、及「在…上(on)」可指稱一層相對於其他層之一相對位置。一層在另一層「頂部」、在另一層「之下」、或在另一層「上」，或者一層接合「至」另一層或與另一層「接觸(contact)」可直接與另一層接觸或可具有一或多個中介層。一層介於（多個）層「之間」可直接與該等層接觸或可具有一或多個中介層。
現參照圖1與圖2，圖1提供根據一實施例之沿圖2之線A-A所取得的包括一雙側安裝式封裝結構100的一記憶體模組的截面側視圖圖示。圖2係根據一實施例之雙側安裝式封裝結構100的示意俯視圖圖示。如所繪示，一記憶體模組可包括一電路板200、及安裝在該電路板200上之雙側安裝式封裝結構100。此可使用覆晶接合及焊料凸塊134來達成。
根據實施例之雙側安裝式封裝結構100可包括模組基材102、及安裝在該模組基材102之頂部側103上的第一邏輯晶粒110。雖然繪示的是單個邏輯晶粒110，但可有多個邏輯晶粒110。例如，多個邏輯晶粒110可佔據由在圖2中之第一邏輯晶粒110所繪示之相同周長。一第一複數個記憶體封裝120係安裝在模組基材102之頂部側103上。如圖2所示，第一複數個記憶體封裝120可選地可包括安裝在一或多個邏輯晶粒110之相對側上的第一群組121A及第二群組121B。在模組基材102的底部側105上同樣地安裝一第二複數個記憶體封裝120。該第二複數個記憶體封裝120可安裝在該第一複數個記憶體封裝120正下方，且同樣地可配置在第一群組及第二群組中。
所繪示之例示性記憶體封裝120包括複數個記憶體晶粒124，該複數個記憶體晶粒堆疊在基材129上、與銲線126連接、且封裝在模製材料128中。應理解的是，此係一例示性實施方案，且實施例不限於此特定記憶體封裝組態。根據實施例，記憶體封裝120可係包括一或多個DRAM晶粒的DRAM封裝。此外，雙側安裝式封裝結構100可使用各種記憶體技術實施，該等記憶體技術包括LPDDR、LPDDR-x、HBM、HMC等。
再次參照圖1，一佈線基材130係安裝至模組基材102之底部側105且在第一邏輯晶粒110（或多個邏輯晶粒110）正下方。該佈線基材130之一底部側133上存在複數個接觸件135。銲料凸塊134可經放置在接觸件135上，用於連接至電路板200。
第一佈線係提供通過該佈線基材及該無芯模組基材，以連接在該佈線基材之該底部側上的該複數個接觸件及該第一邏輯晶粒。在一實施例中，通用型輸入/輸出佈線及電源佈線106A延伸通過該佈線基材。此外，通用型輸入/輸出佈線及電源佈線106B延伸通過模組基材102。通用型輸入/輸出佈線及電源佈線106A/B一起將佈線基材130之底部側133上的複數個接觸件135與一或多個邏輯晶粒110連接。
第二佈線係設置在該模組基材內，以將第一邏輯晶粒與第一複數個記憶體封裝及第二複數個記憶體封裝兩者連接。在一實施例中，信號佈線104係位於模組基材102內，以將邏輯晶粒110與第一複數個記憶體封裝120及第二複數個記憶體封裝120兩者在模組基材102之相對側上連接。信號佈線104至各記憶體封裝120的長度可例如對應於記憶體通道長度。因此，可藉由將記憶體封裝120安裝在模組基材102的相對側上來減少記憶體通道長度，而非以多個列或較長列將記憶體封裝安裝在一基材之一相同側上。此外，信號佈線104的長度可使用減少的模組基材102之厚度來縮減。在一些實施例中，模組基材102係一無芯模組基材。此可避免形成通過基材核心之通孔的要求。取而代之地，細線圖案化技術可用於模組基材102內的所有佈線。
根據實施例之佈線基材130可比模組基材102更厚。在一些實施例中，佈線基材130可係一層壓佈線基材，且可係一有芯層壓佈線基材。此可允許成本降低，利用較不昂貴的佈線基材130處理，該佈線基材可額外包括比模組基材102更粗的間距及更寬的線寬。此可達成係因為在（多個）邏輯晶粒110與記憶體封裝120之間的信號佈線104係包含在模組基材102中。因此，模組基材102內的信號佈線104之特徵在於比通過佈線基材130之通用型輸入/輸出佈線及電源佈線106A更細的間距及更窄的線寬。一較厚的佈線基材130可額外提供間隙，該間隙用於在電路板200上安裝以及用於放置離散式整合被動裝置(integrated passive device, IPD) 140，諸如電容器陣列，其可提供各種功能，包括電壓調節至邏輯晶粒110之通用型輸入/輸出佈線及電源佈線。一或多個離散式IPD 140可安裝諸如在佈線基材130之底部側133的位置（該底部側橫向相鄰於複數個焊料凸塊134）及模組基材102之底部側105的位置。離散式IPD 140亦可位於佈線基材130內。
根據實施例之雙側安裝式封裝結構100可包括由於薄模組基材102而用於機械平衡的各種支撐結構。例如，模組基材102可能缺少原本由一厚芯提供的一些機械強度(mechanical robustness)。機械平衡可使用佈線基材130、加強環(stiffener ring) 160、及可選地基材條150之任一者或一組合來達成。在圖1及圖2所繪示之實施例中，一頂部側加強環160經安裝至模組基材102的頂部側103。頂部側加強環160可側向環繞第一複數個記憶體封裝120及（多個）邏輯晶粒110。
在圖1所繪示的實施例中，一或多個基材條150經安裝至模組基材102的底部側105。該一或多個基材條150可側向地圍繞第二複數個記憶體封裝120及佈線基材130。在一實施例中，基材條150係由與佈線基材130相同的基材材料所形成，但此並非係必需的。基材條150可選地可在頂部側加強環160正下方。在一實施例中，基材條150可含有額外的電氣佈線(electrical routing)。因此，可使用焊料凸塊132將基材條150以與佈線基材130同樣的方式安裝，可選地位在接觸件155上以用於電氣佈線。銲料凸塊132可係小於焊料凸塊134的微凸塊。
根據實施例之雙側安裝式封裝結構可包括使用焊料凸塊112安裝在模組基材102之頂部側103上的一或多個邏輯晶粒110。如所示，可施加銲料凸塊112至接觸件114。該（等）經安裝之邏輯晶粒110可與一底部填充材料118緊固。如所示，該（等）邏輯晶粒110係與通用型輸入/輸出佈線及電源佈線106B及信號佈線104電連接。第一及第二複數個記憶體封裝120亦可使用焊料凸塊122安裝在模組基材的頂部側及底部側上，且佈線基材可使用焊料凸塊132安裝至模組基材102的底部側105。同樣地，基材條150可使用焊料凸塊132安裝。根據實施例之焊料凸塊112、122、132可全部係微凸塊且具有比焊料凸塊134更小之用於安裝至電路板200的體積/面積。此外，離散式IPD 140亦可使用焊料凸塊142來安裝，焊料凸塊142可係具有比焊料凸塊112、122、132更小之體積/面積的微凸塊。
在諸如繪示在圖2中之一實施例中，一或多個邏輯晶粒110係安裝在封裝100或模組基材102之一中心上。例如，邏輯晶粒110之側向邊緣111可沿著一或多個x軸（由線X-X所繪示）或y軸（由線Y-Y所繪示）而與封裝100之一對應邊緣101等距（該邊緣可對應於模組基材102之一邊緣）。該邏輯晶粒110可另外繞x軸及/或y軸對稱。在另一實施例中，該（等）一或多個邏輯晶粒110未安裝在封裝110或模組基材102之一中心上。
現請參照圖3，提供根據一實施例之一佈線基材130內之開口131的示意俯視圖。開口131可完全延伸通過佈線基材130。在此一變化中，第二複數個記憶體封裝120係安裝在模組基材102之底部側105上並在佈線基材130中的該對開口131內，且與佈線基材130側向相鄰。以此方式，佈線基材130可提供額外的機械平衡及對於薄模組基材102的支撐。因此，單一佈線基材130可免除包括額外的基材條150。
圖4係又一額外變化。在所提供的特定截面側視圖中，底部側加強環170係安裝至模組基材102之底部側105。該底部側加強環170側向環繞第二複數個記憶體封裝120及佈線基材130。該底部側加強環170可與頂部側加強環160相同。可使用包括黏著劑、焊料等之合適技術附接該頂部側加強環160及該底部側加強環170。
目前為止已描述各種結構組態，其中可藉由將記憶體封裝120安裝在模組基材102的相對側上來減少記憶體通道長度，而非以多個列或較長列將記憶體封裝安裝在一基材之一相同側上。然而，雙側安裝式MCM封裝結構係額外相容於此組態，特別是用於較大的記憶體縮放。圖5係根據包括多列記憶體封裝之一實施例之一雙側安裝式封裝結構的示意俯視圖圖示。實施例不限於僅包括安裝在一或多個邏輯晶粒110之相對側上的記憶體封裝120之第一群組121A及第二群組121B的組態。如所示，記憶體封裝120可放置於一邏輯晶粒110之多於兩個側上且可圍繞該一或多個邏輯晶粒110。此外，多列記憶體封裝120可圍繞一邏輯晶粒110之一或多個側予以配置，且多列記憶體封裝120可完全地圍繞一邏輯晶粒110予以配置。在所繪示的實施例中，記憶體封裝120之外部列或群組可偏離記憶體封裝120的內部列或群組以允許佈線。類似於圖1及圖3所繪示的實施例，多列記憶體封裝120可安裝至模組基材102之兩側。此外，底部側記憶體封裝可如先前所述地位在記憶體封裝的頂部側正下方。
在使用實施例的各種態樣的過程中，所屬技術領域中具有通常知識者將明白上述實施例的組合或變化對於形成雙側安裝式MCM封裝而言係可行的。雖然已經以結構特徵及/或方法動作之特定語言敘述實施例，應了解附加的申請專利範圍不必受限於所述的特定特徵或行為。替代地，所揭示之特定的特徵或動作應理解為可用於說明之申請專利範圍的實施例。
100:雙側安裝式封裝結構/封裝 101:邊緣 102:模組基材 103:頂部側 104:信號佈線 105:底部側 106A:電源佈線 106B:電源佈線 110:邏輯晶粒/封裝 111:側向邊緣 112:焊料凸塊 114:接觸件 118:底部填充材料 120:記憶體封裝 121A:第一群組 121B:第二群組 122:焊料凸塊 124:記憶體晶粒 126:銲線 128:模製材料 129:基材 130:佈線基材 131:開口 132:焊料凸塊 133:底部側 134:銲料凸塊 135:接觸件 140:離散式整合被動裝置(integrated passive device, IPD) 142:焊料凸塊 150:基材條 155:接觸件 160:加強環 170:加強環 200:電路板 A:線 X:線 Y:線
［圖1］係根據一實施例之沿圖2之線A-A所取得的包括一雙側安裝式封裝結構的一記憶體模組的截面側視圖圖示。 ［圖2］係根據一實施例之一雙側安裝式封裝結構的示意俯視圖圖示。 ［圖3］係根據一實施例之佈線基材內之開口的示意俯視圖圖示。 ［圖4］係根據一實施例之沿圖2之線A-A所取得的包括一雙側安裝式封裝結構的一記憶體模組的截面側視圖圖示。 ［圖5］係根據包括多列記憶體封裝之一實施例之一雙側安裝式封裝結構的示意俯視圖圖示。
100:雙側安裝式封裝結構/封裝
101:邊緣
102:模組基材
103:頂部側
104:信號佈線
105:底部側
106A:電源佈線
106B:電源佈線
110:邏輯晶粒
111:側向邊緣
112:焊料凸塊
114:接觸件
118:底部填充材料
120:記憶體封裝
122:焊料凸塊
124:記憶體晶粒
126:銲線
128:模製材料
129:基材
130:佈線基材
132:焊料凸塊
133:底部側
134:銲料凸塊
135:接觸件
140:離散式整合被動裝置(integrated passive device,IPD)
142:焊料凸塊
150:基材條
155:接觸件
160:加強環
200:電路板

Claims (21)

  1. 一種雙側安裝式封裝結構，其包含：一模組基材；一第一邏輯晶粒，其安裝在該模組基材之一頂部側上；一第一複數個記憶體封裝，其安裝在該模組基材之該頂部側上；一第二複數個記憶體封裝，其安裝在該模組基材之一底部側上；一佈線基材，其安裝至該模組基材之該底部側且在該第一邏輯晶粒正下方；複數個接觸件，其係在該佈線基材之一底部側上；通用型輸入/輸出佈線及電源佈線，其等通過該佈線基材及該模組基材以連接在該佈線基材之該底部側上的該複數個接觸件及該第一邏輯晶粒；及信號佈線，其係在該模組基材內以將該第一邏輯晶粒與該第一複數個記憶體封裝及該第二複數個記憶體封裝兩者連接；其中在該模組基材內的該信號佈線之特徵在於比通過該佈線基材之該通用型輸入/輸出佈線及該電源佈線更細的一間距及更窄的線寬。
  2. 如請求項1之雙側安裝式封裝結構，其進一步包含安裝至該模組基材之該頂部側的一頂部側加強環(stiffener ring)，其中該頂部側加強環側向環繞該第一複數個記憶體封裝及該第一邏輯晶粒。
  3. 如請求項2之雙側安裝式封裝結構，其進一步包含安裝至該模組基材之該底部側的一底部側加強環，其中該底部側加強環側向環繞該第二複數個記憶體封裝及該佈線基材。
  4. 如請求項2之雙側安裝式封裝結構，其進一步包含安裝至該模組基材之該底部側的一或多個基材條，其中該一或多個基材條側向地圍繞該第二複數個記憶體封裝及該佈線基材。
  5. 如請求項1之雙側安裝式封裝結構，其進一步包含在該佈線基材中之一對開口，其中該第二複數個記憶體封裝係安裝在該模組基材之該底部側上並在該佈線基材中的該對開口內。
  6. 如請求項5之雙側安裝式封裝結構，其中該第二複數個記憶體封裝係在該第一複數個記憶體封裝正下方。
  7. 如請求項1之雙側安裝式封裝結構，其進一步包含在該佈線基材之該底部側上的複數個焊料凸塊。
  8. 如請求項7之雙側安裝式封裝結構，其中：該第一邏輯晶粒係以焊料凸塊安裝在該模組基材之該頂部側上；該第一複數個記憶體封裝係以焊料凸塊安裝在該模組基材之該頂部側上；該第二複數個記憶體封裝係以焊料凸塊安裝在該模組基材之該底部側上；且該佈線基材係以焊料凸塊安裝至該模組基材之該底部側。
  9. 如請求項8之雙側安裝式封裝結構，其進一步包含一離散整合式被動裝置組件，該離散整合式被動裝置組件安裝在選自由下列所組成之群組的一位置：側向相鄰於該複數個焊料凸塊的該佈線基材之該底部側、該模組基材之該底部側、及該佈線基材內。
  10. 一種雙側安裝式封裝結構，其包含：一無芯模組基材； 一第一邏輯晶粒，其安裝在該無芯模組基材之一頂部側上；一第一複數個記憶體封裝，其安裝在該無芯模組基材之該頂部側上；一第二複數個記憶體封裝，其安裝在該無芯模組基材之一底部側上；一層壓佈線基材，其安裝至該無芯模組基材之該底部側且在該第一邏輯晶粒正下方，其中該層壓佈線基材比該無芯模組基材更厚；複數個接觸件，其係在該層壓佈線基材之一底部側上；第一佈線，其通過該層壓佈線基材及該無芯模組基材以連接在該層壓佈線基材之該底部側上的該複數個接觸件及該第一邏輯晶粒；及第二佈線，其係在該無芯模組基材內以將該第一邏輯晶粒與該第一複數個記憶體封裝及該第二複數個記憶體封裝兩者連接。
  11. 如請求項10之雙側安裝式封裝結構，其中該層壓佈線基材係一有芯基材。
  12. 如請求項10之雙側安裝式封裝結構，其中在該無芯模組基材內的該第二佈線之特徵在於比通過該層壓佈線基材之該第一佈線更細的一間距及更窄的線寬。
  13. 如請求項10之雙側安裝式封裝結構，其進一步包含安裝至該無芯模組基材之該頂部側的一頂部側加強環，其中該頂部側加強環側向環繞該第一複數個記憶體封裝及該第一邏輯晶粒。
  14. 如請求項13之雙側安裝式封裝結構，其進一步包含安裝至該無芯模組基材之該底部側的一底部側加強環，其中該底部加強環側向環繞該第二複數個記憶體封裝及該層壓佈線基材。
  15. 如請求項10之雙側安裝式封裝結構，其進一步包含在該層壓佈線基材中的一對開口，其中該第二複數個記憶體封裝係安裝在該無芯模組基材之該底部側上並在該層壓佈線基材中的該對開口內。
  16. 如請求項15之雙側安裝式封裝結構，其中該第二複數個記憶體封裝係在該第一複數個記憶體封裝正下方。
  17. 如請求項10之雙側安裝式封裝結構，其進一步包含在該層壓佈線基材之該底部側上的複數個焊料凸塊。
  18. 如請求項17之雙側安裝式封裝結構，其進一步包含一離散整合式被動裝置組件，該離散整合式被動裝置組件安裝在選自由下列所組成之群組的一位置：側向相鄰於該複數個焊料凸塊的該層壓佈線基材之該底部側、該無芯模組基材之該底部側、及該層壓佈線基材內。
  19. 一種記憶體模組，其包含：一電路板；一雙側安裝式封裝結構，其安裝在該電路板上，該雙側安裝式封裝結構包含：一模組基材；一第一邏輯晶粒，其安裝在該模組基材之一頂部側上；一第一複數個記憶體封裝，其安裝在該模組基材之該頂部側上；一第二複數個記憶體封裝，其安裝在該模組基材之一底部側上；及一佈線基材，其安裝至該模組基材之該底部側且在該第一邏輯晶粒正下方，其中該佈線基材比該模組基材更厚；複數個接觸件，其係在該佈線基材之一底部側上； 通用型輸入/輸出佈線及電源佈線，其等通過該佈線基材及該模組基材以連接在該佈線基材之該底部側上的該複數個接觸件及該第一邏輯晶粒；及信號佈線，其係在該模組基材內以將該第一邏輯晶粒與該第一複數個記憶體封裝及該第二複數個記憶體封裝兩者連接。
  20. 如請求項19之記憶體模組，其中該模組基材係一無芯模組基材。
  21. 如請求項20之記憶體模組，其中該佈線基材係一有芯層壓基材。
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