TW201826461A - 堆疊型晶片封裝結構 - Google Patents

堆疊型晶片封裝結構 Download PDF

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Publication number
TW201826461A
TW201826461A TW106123454A TW106123454A TW201826461A TW 201826461 A TW201826461 A TW 201826461A TW 106123454 A TW106123454 A TW 106123454A TW 106123454 A TW106123454 A TW 106123454A TW 201826461 A TW201826461 A TW 201826461A
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Taiwan
Prior art keywords
wafer
chip
circuit layer
sealing body
package structure
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TW106123454A
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English (en)
Inventor
徐宏欣
林南君
張簡上煜
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力成科技股份有限公司
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Publication of TW201826461A publication Critical patent/TW201826461A/zh

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Abstract

一種堆疊型晶片封裝結構，其包括第一晶片、第一端子、第一重佈線路層、第一密封體、第二晶片、第二端子、第二重佈線路層以及貫通柱。第一晶片包括第一主動面以及位於第一主動面上的第一接墊。第一端子位於第一接墊上。第一重佈線路層電性連接至第一晶片。第一密封體密封第一晶片，並暴露出第一端子的頂面。第二晶片配置於第一重佈線路層上。第二晶片包括第二主動面以及位於第二主動面上的第二接墊。第二端子位於第二接墊上。第二重佈線路層電性連接至第二晶片。貫通柱電性連接至第一重佈線路層以及第二重佈線路層。

Description

堆疊型晶片封裝結構
本發明是有關於一種晶片封裝結構及其製造方法，且特別是有關於一種堆疊型（stacked type）晶片封裝結構及其製造方法。
近年來，符合市場需求的電子設備以及製造技術的提升正在蓬勃地發展。考量到電腦（computer），通信（communication）以及消費（consumer）等3C電子產品的便攜性以及其不斷成長的需求，傳統的單晶片封裝結構已逐漸不符合市場的需求。也就是說，於產品設計之時，必須考慮到輕、薄、短、小、緊密度、高密度以及低成本的趨勢。因此，有鑑於對輕、薄、短、小以及緊密度的需求，以不同的方式堆疊具有各種功能的積體電路（integrated circuits；IC），以減少封裝產品的尺寸以及厚度，已成為封裝市場的主流策略。目前，具有封裝層疊（package on package；POP）結構或封裝內置封裝（package in package；PIP）結構的封裝產品乃是為了此趨勢而研究開發。
一般而言，封裝中的通孔（via hole）通常藉由雷射光束形成。在這種情況下，雷射光束通過絕緣層，並且由鋁或類似物所製成的晶片接墊可以於雷射光的照射下而被分開。如此一來，會對具有半導體晶片的元件造成破壞性的損壞。此外，隨著電子設備的功能日益複雜及提升，封裝層疊（PoP）結構以及封裝內置封裝（PiP）結構中所需堆疊的晶片數量也日益增加。因此，當務之急，必須控制封裝件以及電接點的厚度，以便於封裝製程中減小晶片封裝結構的厚度。
本發明提供一種堆疊型晶片封裝結構，其具有良好的可靠性、較低的生產成本以及較薄的整體厚度。
本發明提供一種製造堆疊型晶片封裝結構的製造方法，用於製造上述堆疊型晶片封裝結構。
本發明提供一種堆疊型晶片封裝結構的製造方法，所述方法包括以下步驟。配置至少一個第一晶片於載板上，其中第一晶片包括第一主動面以及位於第一主動面上的多個第一接墊，且第一端子位於第一接墊上。形成第一重佈線路層以電性連接至第一晶片。形成第一密封體以密封第一晶片，並暴露出各個第一端子的頂面。配置至少一個第二晶片於第一密封體上，其中第二晶片包括第二主動面以及位於第二主動面上的多個第二接墊，且第二端子位於第二接墊上。形成第二重佈線路層以電性連接至第二晶片。形成多個貫通柱，其中貫通柱電性連接至第一重佈線路層以及第二重佈線路層。
在本發明的一實施例中，配置至少一第一晶片於載板上的步驟以及形成第一密封體以密封第一晶片的步驟先於形成第一重佈線路層的步驟，且形成第一重佈線路層的步驟先於形成多個貫通柱的步驟。
在本發明的一實施例中，形成第一重佈線路層的步驟先於配置至少一第一晶片於載板上的步驟以及形成多個貫通柱的步驟，且配置至少一第一晶片於載板上的步驟以及形成多個貫通柱的步驟先於形成第一密封體以密封第一晶片的步驟。
在本發明的一實施例中，配置至少一第一晶片以使第一主動面面向載板，且位於至少一第一晶片的第一主動面上的多個第一接墊藉由多個第一端子電性連接至第一重佈線路層。
在本發明的一實施例中，配置至少一第二晶片以使位於至少一第二晶片的第二主動面上的多個第二接墊藉由多個第二端子電性連接至第二重佈線路層。
在本發明的一實施例中，配置至少一第二晶片以使位於至少一第二晶片的第二主動面上的多個第二接墊藉由多個第二端子電性連接至第一重佈線路層。
在本發明的一實施例中，配置至少一第一晶片以使第一主動面面離載板，且位於至少一第一晶片的第一主動面上的多個第一接墊藉由多個第一端子電性連接至第二重佈線路層。
本發明更提供一種堆疊型晶片封裝結構，其包括第一晶片、多個第一端子、第一重佈線路層、第一密封體、第二晶片、多個第二端子、第二重佈線路層以及多個貫通柱。各個第一晶片包括第一主動面以及位於第一主動面上的多個第一接墊。第一端子位於第一接墊上。第一重佈線路層電性連接至第一晶片。第一密封體密封第一晶片，並暴露出第一端子的頂面。第二晶片配置於第一密封體上，其中第二晶片包括第二主動面以及位於第二主動面上的多個第二接墊。第二端子位於第二接墊上。第二重佈線路層電性連接至第二晶片。貫通柱電性連接至第一重佈線路層以及第二重佈線路層。
在本發明的一實施例中，堆疊型晶片封裝結構更包括第一底膠，位於第一晶片以及第一重佈線路層之間，其中第一密封體密封第一晶片以及第一底膠。
在本發明的一實施例中，堆疊型晶片封裝結構更包括第二底膠，位於第二晶片以及第二重佈線路層之間，其中第二密封體密封第二晶片以及第二底膠。
基於上述，在本發明中，第一端子形成於第一晶片上，然後第一晶片配置於載板上。然後形成第一密封體以密封第一晶片，且第一重佈線路層形成於第一密封體上以電性連接第一晶片。然後，其上形成有第二端子的第二晶片可以依續堆疊於第一密封體上，且形成第二重佈線路層以電性連接至第二晶片，且形成貫通柱以電性連接至第一重佈線路層以及第二重佈線路層。藉由這樣的結構，可以進一步減小堆疊型晶片封裝結構的厚度。此外，可以省略藉由雷射鑽孔（laser drilling）以形成用於晶片的導通孔（conductive vias）的製程，因而降低堆疊型晶片封裝結構的生產成本，以及因雷射鑽孔而對晶片接墊所引起的損壞。因此，由本發明的方法所製造的堆疊型晶片封裝結構具有良好的可靠性、較低的生產成本以及較薄的整體厚度。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1至圖9是依據本發明一實施例的堆疊型晶片封裝結構的製造方法的剖面示意圖。本實施例中，堆疊型晶片封裝結構的製造方法可以包括以下步驟。首先，請參照圖1，提供第一晶圓11以及第二晶圓12。第一晶圓11包括多個第一基本晶片（primary chip）11a，第二晶圓12包括多個第二基本晶片12a。在各個第一基本晶片11a上形成多個第一端子116，且在各個第二基本晶片12a上形成多個第二端子126。在本實施例中，第一端子116以及第二端子126可以為如圖1所示的一體形成（integrally formed）的導電柱，且第一端子116以及第二端子126的材質可以包括銅。第一端子116以及第二端子126可以為銅柱。在本實施例中，如圖1所示，在第二晶圓12的背面可以貼附有晶粒黏著膜（die attach film；DAF）13，但本發明不限於此。
請參照圖2以及圖3，切割第一晶圓11以分離第一基本晶片11a，且也可以切割第二晶圓12以分離第二基本晶片12a。然後，如圖3所示，自第一基本晶片11a中選取至少一個第一晶片110，並配置於載板10上。請回頭參照圖2，第一晶片110包括第一主動面112以及位於第一主動面112上的多個第一接墊114，且如圖3所示，第一端子116位於第一接墊114上。在本實施例中，第一晶片110是以第一主動面112遠離載板10的方式配置於載板10上，但本發明不限於此。
接著，請參照圖4，形成第一密封體140以密封第一晶片110，並暴露出第一端子116的頂面。在本實施例中，第一密封體140可以先完全覆蓋第一晶片110以及第一端子116。接著，可以對第一密封體140進行研磨製程（grinding process），直到露出第一端子116的頂面。如此一來，第一密封體140的頂面與第一端子116的頂面共面（coplanar）。此外，可以進行某些處理（例如：蝕刻），以進一步移除第一端子116的頂部。因此，如圖3所示，第一端子116的頂面可以低於第一密封體140的頂面。如此一來，可以增加第一端子116以及第一密封體140與後續所形成的重佈線路層（例如，第一重佈線路層130）所接觸的接觸面積，以提升第一端子116，第一密封體140以及第一重佈線路層130之間的接合強度。在一些實施例中，第一端子116的頂面與第一密封體140的頂面之間的高度差範圍為1微米（micrometer；μm）至3微米。為求簡潔，於其餘圖示中，第一端子116的頂面被繪示為與第一密封體140的頂面基本上共面，但本發明不限於此。藉由這樣的結構，可以進一步減小堆疊型晶片封裝結構100的厚度，且可以省略藉由雷射鑽孔形成用於第一晶片110的導通孔的製程，從而降低堆疊型晶片封裝結構100的製造成本。此外，由於於此省略了雷射鑽孔製程，從而可以避免因雷射引起的對第一接墊114的損壞。除此之外，一體形成的第一端子116可以是實心柱，而通過雷射製程所形成的通孔為內部具有空隙的錐形。因此，第一端子116可以具有較好的電性，並且可以減小任何兩相鄰的第一端子116之間的間隙。
接著，請參照圖4，形成第一重佈線路層130以電性連接至第一晶片110。在本實施例中，第一重佈線路層130形成於第一密封體140上，但本發明不限於此。然後，例如藉由電鍍製程（electroplating process）以形成多個貫通柱160。
接著，請參照圖5，自第二基本晶片12a中選取至少一個第二晶片120，並配置於第一重佈線路層130上。在本實施例中，第二晶片120藉由晶粒黏著膜121配置於第一重佈線路層130上。於此，第二晶片120包括第二主動面122以及位於第二主動面122上的多個第二接墊124。如圖5所示，第二端子126位於第二接墊124上。在本實施例中，第二晶片120是以第二主動面122遠離第一重佈線路層130的方式配置於第一重佈線路層130上，但本發明不限於此。貫通柱160圍繞第二晶片120並且電性連接至第一重佈線路層130。
接著，請參照圖6，形成第二重佈線路層150以電性連接至第二晶片120。在本實施例中，可以形成第二密封體170以密封第二晶片120以及貫通柱160。第二密封體170暴露出第二端子126的頂面以及貫通柱160的頂面，且形成第二重佈線路層150於第二密封體170上以電性連接至第二端子126以及貫通柱160。第二重佈線路層150形成於相對於第一重佈線路層130處。也就是說，第一重佈線路層130以及第二重佈線路層150分別位於第一密封體140或第二密封體170的兩相對側上。在本實施例中，第一重佈線路層130以及第二重佈線路層150分別位於第二密封體170的兩相對側上。因此，貫通柱160電性連接至第一重佈線路層130以及第二重佈線路層150，且第一重佈線路層130位於第一密封體140以及第二密封體170之間。在後續的一些實施例中，第一重佈線路層130以及第二重佈線路層150分別位於第一密封體140的兩相對側上。
請參照圖7以及圖8，如圖7所示，移除載板10。然後，可以翻轉堆疊型晶片封裝結構並配置於輔助載板20上，以在第一晶片110以及第一密封體140的背面上進行研磨製程（grinding process）。因此，堆疊型晶片封裝結構100的厚度可以進一步地減小。如圖7所示的結構例如可以藉由離型層25而配置於輔助載板20上。接著，請參照圖9，移除輔助載板20，並且在第二重佈線路層150上形成多個焊球180。此時，基本上完成了堆疊型晶片封裝結構100的製造過程。
圖10至圖14是依據本發明一實施例的堆疊型晶片封裝結構的部分製造方法的剖面示意圖。請參照圖10至圖14，在本實施例中，堆疊型晶片封裝結構100a的製造過程與圖1至圖9所繪示的堆疊型晶片封裝結構100的製造過程類似。其相同或類似的構件以相同或類似的標號表示，且具有相同或類似的功能，並省略描述。堆疊型晶片封裝結構100a以及堆疊型晶片封裝結構100之間的製造過程的主要差異如下。
請參照圖10以及圖11，如圖10所示，第一重佈線路層130形成於載板10上。然後，例如藉由電鍍等製程將貫通柱160形成於第一重佈線路層130上。然後，將自第一基本晶片（例如：如圖2所示的第一基本晶片11a）中的至少一個第一晶片110配置於載板10上。在本實施例中，第一晶片110以覆晶（flip-chip）接合技術藉由第一端子116配置於第一重佈線路層130上，因此第一重佈線路層130位於第一晶片110以及載板10之間。接著，形成第一底膠190於第一晶片110以及第一重佈線路層130之間。
在本實施例中，第一端子116可以是包括銅、鎳和錫銀合金的導電凸塊。第一端子116可以包括銅柱、位於銅柱上的錫銀合金凸塊，以及位於銅柱以及錫銀合金凸塊之間的鎳層，但本發明不限於此。在本實施例中，在切割第一晶圓11以分離第一基本晶片11a之前，可以先在第一晶圓11的各個第一基本晶片11a上形成上述的第一端子116。
請參照圖12，形成第一密封體140以密封第一晶片110、第一底膠190以及貫通柱160。在本實施例中，第一密封體140可以先完全覆蓋第一晶片110以及貫通柱160。接著，可以對第一密封體140進行研磨製程，直到露出貫通柱160的頂面以及第一晶片110的背面。因此，堆疊型晶片封裝結構100a的厚度可以進一步地減小。接著，形成第二重佈線路層150於第一密封體140上，以與貫通柱160電性連接。第二重佈線路層150形成於相對於第一重佈線路層130處。在本實施例中，第一重佈線路層130以及第二重佈線路層150分別位於第一密封體140的兩相對側上。
請參照圖13，以覆晶接合技術，藉由第二端子126將自第二基本晶片（例如：如圖2所示的第二基本晶片12a）中的至少一個第二晶片120配置於第二重佈線路層150上。接著，形成第二底膠190a於第二晶片120以及第二重佈線路層150之間。在本實施例中，第二端子126可以是包括銅、鎳和錫銀合金的導電凸塊。舉例而言，第二端子126可以包括銅柱、位於銅柱上的錫銀合金凸塊，以及位於銅柱以及錫銀合金凸塊之間的鎳層，但本發明不限於此。在本實施例中，在切割第二晶圓12以分離第二基本晶片12a之前，可以先在第二晶圓12的各個第二基本晶片12a上形成上述的第二端子126。在本實施方式中，不需要在第二晶圓12的背面貼附晶粒黏著膜。然後，形成第二密封體170以密封第二晶片120以及第二底膠190a。
接著，請參照圖14，自第一重佈線路層130移除載板10，且焊球180可以形成於從載板10所暴露出的第一重佈線路層130上。此時，基本上完成了堆疊型晶片封裝結構100a的製造過程。
圖15至圖19是依據本發明一實施例的堆疊型晶片封裝結構的部分製造方法的剖面示意圖。請參照圖15至圖19，在本實施例中，堆疊型晶片封裝結構100b的製造過程與圖1至圖9所繪示的堆疊型晶片封裝結構100的製造過程類似。其相同或類似的構件以相同或類似的標號表示，且具有相同或類似的功能，並省略描述。堆疊型晶片封裝結構100b以及堆疊型晶片封裝結構100之間的製造過程的主要差異如下。
請參照圖15，在本實施例中，首先在載板10上形成第一重佈線路層130，然後藉由晶粒黏著膜111將來自於第一基本晶片11a的至少一個第一晶片110貼附於第一重佈線路層130上。在本實施例中，第一端子116是可以一體形成的導電柱，且第一端子116所位於的第一主動面112面向遠離於第一重佈線路層130。在本實施例中，貫通柱160形成於第一重佈線路層130上且圍繞第一晶片110，第一密封體140密封貫通柱160並暴露出第一端子116的頂面以及貫通柱160的頂面。
請參照圖16，形成第二重佈線路層150於第一密封體140上，以與暴露出的第一端子116以及貫通柱160電性連接。因此，貫通柱160電性連接於第一重佈線路層130以及第二重佈線路層150之間。
請參照圖17，例如藉由離型層25以將輔助載板20配置於第二重佈線路層150上，且將載板10自第一重佈線路層130移除。此外，在載板10以及第一重佈線路層130之間也可以具有離型層，因此可以藉由離型層容易地移除載板10。接著，請參照圖18，翻轉圖17的結構，且來自第二基本晶片12a中的至少一個第二晶片120配置於暴露出的第一重佈線路層130上。
在本實施例中，第二晶片120藉由覆晶接合技術配置於第一重佈線路層130上。接著，形成第二底膠190a於第二晶片120以及第一重佈線路層130之間。在本實施例中，第二端子126可以是包括銅、鎳和錫銀合金的導電凸塊。舉例而言，第二端子126可以包括銅柱、位於銅柱上的錫銀合金凸塊，以及位於銅柱以及錫銀合金凸塊之間的鎳層，但本發明不限於此。在本實施例中，在切割第二晶圓12以分離第二基本晶片12a之前，可以先在第二晶圓12的各個第二基本晶片12a上形成上述的第二端子126。在本實施方式中，不需要在第二晶圓12的背面貼附晶粒黏著膜。然後，形成第二密封體170以密封第二晶片120以及第二底膠190a。
接著，如圖19所示，移除輔助載板20以暴露出第二重佈線路層150。接下來，將焊球180設置於第二重佈線路層150上。此時，基本上完成了堆疊型晶片封裝結構100b的製造過程。
圖20至圖24是依據本發明一實施例的堆疊型晶片封裝結構的部分製造方法的剖面示意圖。請參照圖20至圖24，在本實施例中，堆疊型晶片封裝結構100c的製造過程與圖15至圖19所繪示的堆疊型晶片封裝結構100b的製造過程類似。其相同或類似的構件以相同或類似的標號表示，且具有相同或類似的功能，並省略描述。堆疊型晶片封裝結構100c以及堆疊型晶片封裝結構100b之間的製造過程的主要差異如下。
請參照圖20，在本實施例中，形成第一重佈線路層130於載板10上。接著，形成貫通柱160於第一重佈線路層130上。接著，將來自於第一基本晶片11a中的多於一個第一晶片110配置於第一重佈線路層130上。於此繪示了兩個第一晶片110，但本發明不限於此。值得注意的是，配置於第一重佈線路層130上的第一晶片110可以相同或可以彼此不同。也就是說，配置於第一重佈線路層130上的第一晶片110可以是彼此同性質/種類/類型（homogeneous）或彼此不同性質/不同種類/不同類型（heterogeneous），本發明對於配置於第一重佈線路層130上的第一晶片110的性質/種類/類型並不加以限定。在本實施例中，第一晶片110以覆晶（flip-chip）接合技術藉由第一端子116配置於第一重佈線路層130上，且貫通柱160圍繞第一晶片110。第一晶片110的第一主動面112面向第一重佈線路層130，且第一端子116可以是包括銅、鎳和錫銀合金的導電凸塊。舉例而言，第一端子116可以包括銅柱、位於銅柱上的錫銀合金凸塊，以及位於銅柱以及錫銀合金凸塊之間的鎳層，但本發明不限於此。在本實施例中，在切割第一晶圓11以分離第一基本晶片11a之前，可以先在第一晶圓11的各個第一基本晶片11a上形成上述的第一端子116。
接著，形成第一密封體140以密封第一晶片110以及貫通柱160。在本實施例中，第一密封體140可以先完全覆蓋第一晶片110以及貫通柱160。接著，可以對第一密封體140進行研磨製程，直到露出第一晶片110的背面以及貫通柱160的頂面，因而可以進一步減小堆疊型晶片封裝結構100c的厚度。
接著，請參照圖21，形成第二重佈線路層150於第一密封體140上，以與貫通柱160電性連接。因此，貫通柱160電性連接第一重佈線路層130以及第二重佈線路層150。然後，對圖21所示的結構所進行的後續製造過程（繪示於圖22至圖24）基本上相同於圖13以及圖14所繪示的製造過程，故相同或類似的特徵於此不加以贅述。
在本實施例中，可以省略形成第一底膠190的製程。此外，可以形成第二密封體170以密封第二晶片120，或是也可以不形成第二密封體170。於此僅繪示了兩個第二晶片120，但發明對於第二晶片120的數量並不加以限制。類似地，如圖14以及圖19所繪示的堆疊型封裝結構100a、100b中，也可以不形成第二密封體170而不密封第二晶片120。在具有第二密封體170的堆疊型晶片封裝結構100c的實施例中，第二密封體170可以暴露出或不暴露出第二晶片120的背面。類似地，如圖14以及圖19所繪示的堆疊型晶片封裝結構100a、100b中，第二密封體170也可以不暴露出第二晶片120的背面。除此之外，如圖25所示，在第二密封體170暴露出第二晶片120背面的實施例中，可以配置散熱件40於第二密封體170上並與第二晶片120的背面接觸。類似地，於如圖14以及圖19所示的堆疊型晶片封裝結構100a、100b中，散熱件40也可以配置於第二密封體170上，且與第二晶片120的背面接觸。
綜上所述，在本發明中，第一端子形成於第一晶片上，然後第一晶片配置於載板上。然後，形成第一密封體以密封第一晶片，且第一重佈線路層形成於第一密封體上以電性連接第一晶片。然後，其上形成有第二端子的第二晶片可以依續堆疊於第一重佈線路層上，且形成第二重佈線路層以電性連接至第二晶片，且形成貫通柱以電性連接至第一重佈線路層以及第二重佈線路層。
藉由這樣的結構，可以進一步減小堆疊型晶片封裝結構的厚度，且可以省略藉由雷射鑽孔形成用於晶片的導通孔的製程，從而降低堆疊型晶片封裝結構的製造成本。並且，由於於此省略了雷射鑽孔製程，從而可以避免因雷射引起的對晶片的接墊的損壞。此外，本發明的端子是預先形成於晶片上的實心柱，而通過激光工藝形成的通孔是具有內部空隙的錐形形狀。因此，本發明的端子可以具有較好的電性，並且可以減小任何兩相鄰的端子之間的間隙。因此，由本發明的方法所製造的堆疊型晶片封裝結構具有良好的可靠性、較低的生產成本以及較薄的整體厚度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100、100a、100b、100c‧‧‧堆疊型晶片封裝結構
10‧‧‧載板
11‧‧‧第一晶圓
11a‧‧‧第一基本晶片
12‧‧‧第二晶圓
12a‧‧‧第二基本晶片
13、111、121‧‧‧晶粒黏著膜
20‧‧‧輔助載板
25‧‧‧離型層
40‧‧‧散熱件
110‧‧‧第一晶片
112‧‧‧第一主動面
114‧‧‧第一接墊
116‧‧‧第一端子
120‧‧‧第二晶片
122‧‧‧第二主動面
124‧‧‧第二接墊
126‧‧‧第二端子
130‧‧‧第一重佈線路層
140‧‧‧第一密封體
150‧‧‧第二重佈線路層
160‧‧‧貫通柱
170‧‧‧第二密封體
180‧‧‧焊球
190‧‧‧第一底膠
190a‧‧‧第二底膠
圖1至圖9是依據本發明一實施例的堆疊型晶片封裝結構的製造方法的剖面示意圖。 圖10至圖14是依據本發明一實施例的堆疊型晶片封裝結構的部分製造方法的剖面示意圖。 圖15至圖19是依據本發明一實施例的堆疊型晶片封裝結構的部分製造方法的剖面示意圖。 圖20至圖24是依據本發明一實施例的堆疊型晶片封裝結構的部分製造方法的剖面示意圖。 圖25是依據本發明一實施例的堆疊型晶片封裝結構的剖面示意圖。

Claims (10)

  1. 一種堆疊型晶片封裝結構，包括： 第一晶片，其中所述第一晶片包括第一主動面以及位於所述第一主動面上的多個第一接墊； 多個第一端子，位於所述多個第一接墊上； 第一重佈線路層，電性連接至所述第一晶片； 第一密封體，密封所述第一晶片且暴露出各個所述多個第一端子的頂面； 第二晶片，配置於所述第一密封體上，其中所述第二晶片包括第二主動面以及位於所述第二主動面上的多個第二接墊； 多個第二端子，位於所述多個第二接墊上； 第二重佈線路層，電性連接至所述第二晶片；以及 多個貫通柱，電性連接至所述第一重佈線路層以及所述第二重佈線路層。
  2. 如申請專利範圍第1項所述的堆疊型晶片封裝結構，其中所述多個第一端子為一體形成的導電柱，所述第一重佈線路層位在所述第一密封體上，所述第二晶片配置於所述第一重佈線路層上，所述第二主動面面離所述第一重佈線路層，所述多個貫通柱位於所述第一重佈線路層上且圍繞所述第二晶片。
  3. 如申請專利範圍第2項所述的堆疊型晶片封裝結構，更包括： 第二密封體，密封所述第二晶片以及所述多個貫通柱，其中所述第二密封體暴露出各個所述多個第二端子的頂面以及各個所述多個貫通柱的頂面，且所述第二重佈線路層位於所述第二密封體上；以及 多個焊球，位於所述第二重佈線路層上。
  4. 如申請專利範圍第1項所述的堆疊型晶片封裝結構，其中所述第一晶片藉由所述多個第一端子以配置於所述第一重佈線路層上，且所述多個第一端子為包括銅、鎳或錫銀合金的導電凸塊，所述多個貫通柱位於所述第一重佈線路層上，所述第一密封體密封所述多個貫通柱並暴露出各個所述多個貫通柱的頂面，且所述第一重佈線路層位於所述第一密封體上。
  5. 如申請專利範圍第4項所述的堆疊型晶片封裝結構，其中所述第二晶片藉由所述多個第二端子以配置於所述第二重佈線路層上，且所述多個第二端子為包括銅、鎳或錫銀合金的導電凸塊。
  6. 如申請專利範圍第1項所述的堆疊型晶片封裝結構，其中所述第一晶片配置於所述第一重佈線路層上。
  7. 如申請專利範圍第6項所述的堆疊型晶片封裝結構，其中所述多個第一端子為一體形成的導電柱，且所述第一主動面面離所述第一重佈線路層。
  8. 如申請專利範圍第6項所述的堆疊型晶片封裝結構，其中所述第一晶片藉由所述多個第一端子以配置於所述第一重佈線路層上，且所述多個第一端子為包括銅、鎳或錫銀合金的導電凸塊。
  9. 如申請專利範圍第6項所述的堆疊型晶片封裝結構，其中所述多個貫通柱位於所述第一重佈線路層上且圍繞所述第一晶片，且所述第一密封體密封所述多個貫通柱並暴露出所述多個貫通柱的頂面。
  10. 如申請專利範圍第8項所述的堆疊型晶片封裝結構，其中所述第二重佈線路層位於所述第一密封體上，所述第二晶片藉由所述多個第二端子以配置於所述第一重佈線路層上，且所述多個第二端子為包括銅、鎳或錫銀合金的導電凸塊。
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