TWI227552B - Stacked chip package structure - Google Patents

Stacked chip package structure Download PDF

Info

Publication number
TWI227552B
TWI227552B TW092116358A TW92116358A TWI227552B TW I227552 B TWI227552 B TW I227552B TW 092116358 A TW092116358 A TW 092116358A TW 92116358 A TW92116358 A TW 92116358A TW I227552 B TWI227552 B TW I227552B
Authority
TW
Taiwan
Prior art keywords
chip
substrate
scope
electrically connected
item
Prior art date
Application number
TW092116358A
Other languages
Chinese (zh)
Other versions
TW200501347A (en
Inventor
Yu-Fang Tsai
Juang-Kun Kang
Tsung-Yueh Tsai
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW092116358A priority Critical patent/TWI227552B/en
Publication of TW200501347A publication Critical patent/TW200501347A/en
Application granted granted Critical
Publication of TWI227552B publication Critical patent/TWI227552B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

A stacked chip package structure is composed of a plurality of chip package units. Each one unit includes a substrate, a chip, a plurality of wires, a compound, a lead frame and a plurality of solder balls. The chip package unit such as a BGA type chip package with high pin count, and one unit stacks with the other unit by solder balls to shorten the electric length of connecting two chip package units. That is also multiple chip package type we need. In addition, with improvement of structure, the area of stacked chip package can be more miniaturization.

Description

12275521227552

本發明是有關於一種晶片封 一種堆疊式晶片封裝結構。 、構，且特別是有關於 先前良街 五、發明說明（1) w著積體電路（integrated 的高度發展，1C曰加+ t’IC)製程技術 )曰曰 部電路的積集度（utegratlon +斷地向上攀升，栋焊ΤΓ曰 ^ cl ιιυπ 目因而大幅地增加，並將1(]曰曰曰片片之之^部電路的電晶體數 _也縮小。目前導 不斷地推陳出新’例如球格陣列封裝⑽二曰 :片^模㈣晶片封裝結構，其中，球格陣列封裝豆有 =腳數以及高可靠度的優勢，而多晶片封裝模組則具有更 ，、更紐的傳輸路徑以及更佳的電氣特性，並進一步縮小 晶片封裝結構的面積，因而使得該些技術已經用 各種=子產品之中，並成為未來的主流產品。 〜、 請參考第1圖，其繪示習知一種晶片封裝結構的示意 圖。就常見之打線接合（wire bonding)之晶片封裝結構而 言，晶片封裝結構1〇〇主要係由一基板110、一晶片12〇、 多個導線130、一封膠14〇以及多個銲球150所構成。其 中’基板110例如為一陶瓷基板、玻璃基板或塑膠基板， 基板11 0内部具有多層導線層（未繪示）以及多層絕緣層（未 繪示）交替堆疊，而相鄰二導線層之間係以一絕緣層相 隔，且導線層之間係以導電孔（conductive via)或鍍通孔 (Plating Through Hole, PTH)而彼此電性連接。此外，The invention relates to a chip package and a stacked chip package structure. , Structure, and especially about the previous good street V. invention description (1) w integrated circuit (integrated highly developed, 1C + + t'IC) process technology) the degree of accumulation of the circuit (utegratlon + Climbing upwards on the ground, building welding has increased significantly, and the number of transistors in the circuit of 1 () is also reduced. The current guide continues to introduce new ones, such as balls Cell Array Packaging II: Chip ^ die ㈣ chip packaging structure, of which the ball grid array package has the advantages of pin count and high reliability, and the multi-chip package module has more, more transmission paths and Better electrical characteristics, and further reduce the area of the chip packaging structure, so that these technologies have been used in various = sub-products, and become the mainstream products in the future. ~, Please refer to Figure 1, which shows a known type Schematic diagram of the chip packaging structure. As for the common wire bonding chip packaging structure, the chip packaging structure 100 is mainly composed of a substrate 110, a chip 120, a plurality of wires 130, and a glue 14. To It is composed of a plurality of solder balls 150. The substrate 110 is, for example, a ceramic substrate, a glass substrate or a plastic substrate, and the substrate 110 has multiple layers of wire layers (not shown) and multiple layers of insulation (not shown) alternately stacked, and Adjacent two wire layers are separated by an insulating layer, and the wire layers are electrically connected to each other by a conductive via or a plated through hole (PTH). In addition,

10793twf.ptd 第6頁 1227552 五、發明說明（2) 基板1 1 0之頂面11 〇 a以及底面11 0 b分別具有一上接點丨丨2以 及一下接點1 1 4，而上接點1 1 2係藉由基板11 〇内部之導線 層而電性連接於下接點丨丨4。另外，晶片丨2 〇配置於基板 110之頂面ll〇a ’晶片120具有一主動表面（active surface)122 ’而主動表面122之周緣配置多個鋅墊 (bonding pad)124，一般為鋁墊，且導線13〇係以打線接 合的方式連接於晶片120之銲墊124以及基板11〇之上接點 112 ’其中導線1 3〇例如為一金線。 承上所述’封膠1 4 0係包覆導線1 3 0、晶片1 2 0以及基 板110之上接點112，用以保護晶片120以及導線130。銲球 150係配置於基板11〇之下接點114，且銲球15〇之材質例如 ίΐ匕合/等焊接材料。其中，晶片封裝結構100係以銲 =作為連接外部電子裝置(例如印刷電路㈣主機板） 穿面i n，h且知球150例如以面陣列的型態分佈於基板110之 " ，以使此晶片封裝結構1 0 0成為具有高腳數t找 格陣列封裝結構。 X虿回腳數之球 意圖請封其么示習知一種多晶片封裝模組的示 州⑷（b)V日置片在封同裝一技 單元200例如為一碰炊陆J電路板21 〇上，其中晶片封裝 封奘罝- 9nrw 表袼陣列封裝（BGA)型態，且依序將曰p = 裝於印刷電路板210上，而-曰月 2 00 (a)及（b)之間#< 叩—日日片封裝早元 例如動態隨機記憶體（DRAM)模組、。’曰曰片#《之模組，10793twf.ptd Page 6 1227552 V. Description of the invention (2) The top surface 11 〇a and the bottom surface 11 0 b of the substrate 1 1 0 have an upper contact 丨 2 and a lower contact 1 1 4 respectively, and the upper contact 1 1 2 is electrically connected to the lower contact 丨 4 through a wire layer inside the substrate 11 〇. In addition, the wafer 20 is disposed on the top surface 110a of the substrate 110. The wafer 120 has an active surface 122 and the periphery of the active surface 122 is provided with a plurality of zinc pads 124, generally aluminum pads. The wire 13 is connected to the bonding pad 124 of the chip 120 and the contact 112 ′ on the substrate 110 by wire bonding. The wire 1 30 is, for example, a gold wire. The aforementioned “sealing compound 1 40” is used to cover the wire 130, the chip 120, and the contact 112 on the substrate 110 to protect the chip 120 and the wire 130. The solder ball 150 is arranged at the contact 114 below the substrate 110, and the material of the solder ball 150 is, for example, a soldering material. Among them, the chip package structure 100 is soldered as a connection to an external electronic device (such as a printed circuit board or a motherboard) and passes through the surface in, h, and the spheres 150 are distributed on the substrate 110 in the form of a surface array, for example. The chip package structure 100 becomes a grid array package structure with a high pin count t. The ball of the number of X-pins is intended to be sealed. It is shown that a multi-chip package module is known. (B) A V-chip is installed in a package with a technical unit 200, such as a bumper J circuit board 21. In the above, the chip package is sealed-9nrw surface mount array package (BGA) type, and p = is sequentially mounted on the printed circuit board 210, and-between the month 2 00 (a) and (b) # < 叩 —Japanese and Japanese film package early elements such as dynamic random memory (DRAM) modules. ‘耶 anya 片 #" The module,

ri?27552 發明說明（3) 地Ep &柃'主思的疋’當晶片封襞單元之數目赦夕± 心：電路板所需的承載面積也必須加；目=時’相對 =成之後的多晶片封裝模組，其外 力寬，使得組 缩小，四方體結構’且印刷電路板之承載面積：=狀或扁 晶片因此’ $ 了符合現今高腳數之晶片封妒二;相對地 ^杨組封裝結構的潮 J 構以及多 題。 更夕數里之曰曰片封裝結構，將是目前重大的課 容 2於此’本發明的目的就是在提供— 裝、、、口構，用以構裝並堆疊更多數 ^且式日日片 ::裝早兀之上，以達到多晶片模組封裴之早 Λ明的另一目的就是在提供一種 封 利用球格陣列之銲球來連接相 裝結 以達到高腳數之晶片封裝的目的。 4封裝… 封裝本發明提出-種堆疊式覆晶 :片封裝單元主要係由一基板、—晶片、；以線而母： :接：及多個鮮球所構成。其中，基板具有多個 二配置於基板上，且晶片具有多個薛塾：： 刀別連接上接點以及銲墊，而接腳架配置於 二連接於基板之上接點，而接腳架由多個ίΐ接 腳組成，每-導電接腳具有一第一端以及對應之接 10793twf.ptd 參 第8頁ri? 27552 Description of the invention (3) The ground Ep & 主 's main idea' when the number of wafer sealing units is reduced ± heart: the required load area of the circuit board must also be increased; the purpose = time 'relative = after The multi-chip package module has a wide external force, which makes the group smaller, a rectangular parallelepiped structure, and the bearing area of the printed circuit board: = shaped or flat chip. Therefore, '$' meets today's high pin count chip seals; relatively ^ The tide J structure of the Yang group packaging structure and many questions. Even more miles said that the chip package structure will be a major lesson at the moment 2 'The purpose of the present invention is to provide-mounting ,, and mouth structure, used to build and stack more data Japanese film :: Installed on top of the early stage to achieve multi-chip module sealing. The other purpose of the Λ Ming is to provide a package that uses ball grid array solder balls to connect phase-mount knots to achieve high pin count chips. Purpose of encapsulation. 4 Packaging ... Packaging The present invention proposes a stack-type flip chip: a chip packaging unit is mainly composed of a substrate, a wafer, a wire and a mother: a connection: and a plurality of fresh balls. Wherein, the substrate has a plurality of two arranged on the substrate, and the wafer has a plurality of Xue :: The knife is connected to the upper contact and the solder pad, and the pin holder is arranged on the two connected to the contact on the substrate, and the pin holder Consists of multiple ΐ pins, each-conductive pin has a first end and a corresponding connection 10793twf.ptd see page 8

包覆導 其中接 露於封 元之導 性連接 較佳實 屬，且 質相同 ’導電 腳之第一端位 具有一表面金 線、晶 腳架係 膠之外 電接腳 〇 施例所 接腳架 之散熱 接腳之 1227552 五、發明說明（4) 端。另外，封膠係 及基板之上接點， 接腳之第二端係暴 及另一晶片封裝單 片封裝單元彼此電 依照本發明的 如為散熱性佳之金 置多個與接腳架材 之政熱效果。此外 區域上，且導電接 而苐一端之表面還 銲球之間的接合性 本發明因採用 其具有高腳數之優 彼此電性連接，以 度’並達到多晶片 裝結構由於結構上 能更小型化。 片、導電接腳之第一端以 覆蓋於封膠之上，且導電 。鲜球分別連接下接點以 的第二端，以使相疊之晶 述，上述接腳架之材質例 的中央或角洛區域亦可配 片，以提高晶片封裝單元 第二端位於接腳架之中央 於接腳架之周緣區域上， 屬層，用以提高第二端與 球格陣列封裝（BGA)之晶片封裝單元， 且相疊之晶片封$ f元係以鲜球而 鈿短晶片封裝單元之間電氣連 I::裝的目，：此外，堆疊式丄 、變，使侍堆璺完成之後的承載面積 為讓本發明之上述和其他目的、 顯易懂，下文特舉一較佳實 、Λ 、和優點能更明 細說明如下： 實〜例，並配合所附圖式，作詳 真.篇方式 明一較佳實施例之 以及組裝示意圖。 第3Α〜3Β圖繪示本發 片封裝結構的分解示意圖 一種堆疊式晶 請參考第3ΑIt is better to cover the conductive connection exposed to the sealed element, and it is of the same quality. The first end of the conductive feet has a surface gold wire, and the electrical pins other than the crystal feet are glued. The heat dissipation pin of the frame is 1227552. 5. Description of the invention (4). In addition, the sealant system and the contact on the substrate, the second end of the pin and the other chip packaged monolithic package unit are electrically connected to each other according to the present invention. Political heat effect. In addition, the surface of one end is conductive and the bonding between the solder balls on one end of the present invention is because the invention has a high pin count and is electrically connected to each other in order to achieve a multi-chip mounting structure. miniaturization. The first end of the chip and the conductive pin is covered on the sealant and is conductive. The fresh balls are respectively connected to the second ends of the lower contacts to make the crystals overlap. The center or corner area of the material example of the above-mentioned lead frame can also be equipped with a sheet to improve the second end of the chip packaging unit. The center of the frame is on the peripheral area of the pin frame. It is a layer to improve the second end and the ball grid array package (BGA) chip packaging unit, and the stacked chip seals are shortened with fresh balls. The electrical connection between the chip packaging units is as follows: In addition, the stacking type is changed so that the load bearing area after the completion of the stack is to make the above and other purposes of the present invention obvious and easy to understand. The best practice, Λ, and advantages can be explained in more detail as follows: Examples ~, and in conjunction with the attached drawings, make detailed and detailed descriptions of a preferred embodiment and an assembly schematic diagram. Figures 3A ~ 3B show the exploded schematic diagram of the package structure of this chip.

1227552 發明說明（5) 圖堆嚏式曰曰片封裝結構3 0 0主要係由多個晶片封裝單元 302、304、30 6堆叠而成，每一晶片封裝單元3〇2、3〇4、 306主要係由-基板31()、_晶片32()、多個導線33()、一接 腳架340、一封膠348以及多個銲球35〇所構成。其中，基 板310例如為-陶I基板、玻璃基板或塑膠基&，基板31〇 内部具有多層導線層（未繪示）以及多層絕緣層（未繪示）交 替堆疊1而相鄰二導線層之間係以一絕緣層相隔，且導線 層之間係以導電孔或鍍通孔而彼此電性連接。此外，每一 基板310(3)、（13)或（(：）之頂面31(^以及底面31〇13分別具有 一上接·點3 1 2以及一下接點3 1 4，而上接點3丨2係藉由基板 3 1 0内部之導線層而電性連接於下接點3 14。 此外，晶片320配置於基板310之頂面31〇a，晶片32〇 具有一主動表面322，而主動表面3 22之周緣配置多個銲墊 324，一般為鋁墊，且導線33〇係以打線接合的方式連接於 晶片320之銲墊324以及基板310之上接點312 ,苴中導錄 330例如為一金線。 $ 請參考第3A圖以及第4圖，其中第4圖繪示接腳架的俯 視示意圖。本發明之接腳架係由多個導電接腳34〇所組 成。接腳架係配置於基板31〇之頂面31 〇3上，其材質可為 導電性、導熱性佳的金屬，例如為銅，且銅之表面還形一成 一保護層。在較佳情況下，接腳架例如為蓋狀結構，覆蓋 於晶片320、封膠348與導線330之上。 如第3A及4圖所示，每個導電接腳34〇具有一第一端 342以及對應之一第二端344 ,其中第一端342例如分佈於1227552 Description of the invention (5) Heap type package structure 3 0 0 is mainly formed by stacking a plurality of chip packaging units 302, 304, 306, and each chip packaging unit 302, 304, 306 It is mainly composed of a substrate 31 (), a wafer 32 (), a plurality of wires 33 (), a lead frame 340, a piece of glue 348, and a plurality of solder balls 350. The substrate 310 is, for example, a ceramic I substrate, a glass substrate, or a plastic substrate. The substrate 31 has multiple layers of conductive layers (not shown) and multiple layers of insulating layers (not shown) stacked alternately and adjacent two conductive layers. They are separated by an insulating layer, and the conductive wire layers are electrically connected to each other by conductive holes or plated through holes. In addition, each substrate 310 (3), (13), or ((:) has a top surface 31 (^ and a bottom surface 31〇13) having an upper contact · point 3 1 2 and a lower contact 3 1 4 respectively, and an upper contact The point 3 丨 2 is electrically connected to the lower contact 3 14 through the wiring layer inside the substrate 3 1 0. In addition, the chip 320 is disposed on the top surface 31a of the substrate 310, and the chip 320 has an active surface 322. The active surface 3 22 is provided with a plurality of solder pads 324 on the periphery, generally aluminum pads, and the wires 33 are connected to the solder pads 324 of the wafer 320 and the contacts 312 on the substrate 310 by wire bonding. 330 is a gold wire, for example. Please refer to FIG. 3A and FIG. 4, where FIG. 4 shows a schematic top view of the pin holder. The pin holder of the present invention is composed of a plurality of conductive pins 34. The tripod is arranged on the top surface 31 〇3 of the substrate 31. The material can be a metal with good electrical and thermal conductivity, such as copper, and the surface of the copper also forms a protective layer. In a preferred case, The lead frame is, for example, a cover-like structure covering the chip 320, the sealant 348, and the lead 330. As shown in FIGS. 3A and 4, each conductive pin 34 〇 has a first end 342 and a corresponding second end 344, wherein the first end 342 is distributed, for example, in

10793twf.ptd 第10頁 122755210793twf.ptd Page 10 1227552

五、發明說明（6) 接腳架之周緣區域上，而第一端342彎折之後向下延伸至 基板310的周緣，且基板31〇之頂面31〇a對應配置多個連接 墊31 6，以使第一端342可分別藉由連接墊31 6之一而電性 連接於基板3 1 〇之上接點3〗2之一及/或下接點3丨4之一。此 外’第二端344例如分佈於接腳架之中央區域上，且導電 接腳340之第二端344暴露於封膠348之外，並對應連接相 疊之晶片封裝單元。 如第3A圖所示，封膠348係包覆導線330、晶月32〇、 導電接腳340之第一端342以及基板31〇之上接點312，用以 保遵晶片320以及導線330。此外，多個銲球35〇分別配置 於基板310之下接點314，藉由鋒球350對應連接於導電接 腳340之第二端344，以使相疊之晶片封裝單元3〇2、3〇4、 306彼此電性連接。其中，銲球35〇例如為錫鉛合金等焊接 材料，而下接點31 4以及銲球3 5 0例如呈矩形型態分佈於基 板310之中央表面區域上。此外，導電接腳34〇之第二端土 ,344與銲球350之接合處還可具有一表面金屬層以“（如第4 圖所示），用以提高導電接腳34〇第二端344與 的接合性。 ％ 2參考第3Β圖，堆疊完成之後的晶片封裝結構3〇〇 , t在苐1層#之晶片封裝單元302上依序堆疊第2層〜第Ν層之 日日片封裝單元304、306，而N可為2, 3,4…等，其中第2芦 之晶片封裝單元304之銲球350係對應連接於第/層之晶曰 封裝f元304之導電接腳34〇的第二端344，而第3曰層之曰曰晶 封裝單兀30 6之銲球350係對應連接於第2層之晶片封裝^曰單V. Description of the invention (6) On the peripheral edge area of the base, the first end 342 is bent down and extends down to the peripheral edge of the substrate 310, and the top surface 31〇a of the substrate 31 is correspondingly provided with a plurality of connection pads 31 6 So that the first end 342 can be electrically connected to one of the upper contacts 3 and 2 and / or one of the lower contacts 3 and 4 respectively through one of the connection pads 31 16. In addition, the second end 344 is, for example, distributed on the central region of the lead frame, and the second end 344 of the conductive pin 340 is exposed outside the sealant 348 and correspondingly connects the stacked chip packaging units. As shown in FIG. 3A, the sealant 348 covers the wire 330, the crystal moon 32, the first end 342 of the conductive pin 340, and the contact 312 on the substrate 31 to ensure compliance with the chip 320 and the wire 330. In addition, a plurality of solder balls 35 are disposed at the contacts 314 below the substrate 310, and are connected to the second end 344 of the conductive pin 340 through the front ball 350, so that the stacked chip packaging units 3, 2 and 3 〇4, 306 are electrically connected to each other. Among them, the solder ball 350 is a solder material such as a tin-lead alloy, and the lower contacts 31 4 and the solder ball 3 50 are distributed in a rectangular shape on the central surface area of the substrate 310, for example. In addition, the junction of the second end of the conductive pin 34, 344 and the solder ball 350 can also have a surface metal layer "(as shown in Figure 4), to improve the second end of the conductive pin 34. 344 and the adhesion.% 2 Refer to Figure 3B. After the stacking is completed, the chip packaging structure 300, t is sequentially stacked on the chip packaging unit 302 of the first layer #. The packaging units 304, 306, and N can be 2, 3, 4, etc., wherein the solder ball 350 of the chip package unit 304 of the second reed is connected to the conductive pin 34 of the package f element 304 corresponding to the crystal of the first / layer. 〇 the second end 344, and the third layer of the three-dimensional package of the chip package 306 solder ball 350 is corresponding to the chip package connected to the second layer ^ said single

12275521227552

五、發明說明（7) 元304之導電接腳34〇的第二端344，以此 一 多晶片模組封裝的目的。由於堆疊完 推，糟以達到 咖不須藉由習知之承載器提供大面成積之之後的晶… 由第1層之晶片封裝單元302直接提載面，而是 曰、S 〇長條形或扁平形之四方體結構，本發明 曰日片封裝結構300，其外觀大致上為柱狀發且式 積可大幅地縮小，以達到小型化晶片封大裝體之目且的其承載面 列封^發明之堆疊式晶片封裂結構300係以球格陣 封裝(BGA)之結構作為每一晶片封裝單元3〇2、3〇4、 304 ’二f有高腳數之優點，且相疊之晶片封裝單元繼、 4、。。306係直接以銲球35〇而彼此電性連接以縮短晶片 兀302、304、306之間電氣連接的長度，因此可降 ，二片320之間因訊號傳遞路徑太長而導致延遲的現象。 ，外，接腳架具有較高的熱傳係數，能快速吸收晶片所產 及的熱旎，故有助於提高晶片封裝單元3〇2、3〇4、3〇6的 散熱效果。再者，如第4圖所示，接腳架的中央或角落區 ，，可配置多個與接腳架材質相同之散熱片346，同樣能 提高晶片封裝單元302、304、306之散熱效果。 雖然本發明以一較佳實施例說明，但非限定利用相同 封裝尺寸之晶片封裝單元，亦可採用不同尺寸或不同型態 =晶片封裝單元，且個別晶片封裝單元亦可具有不同之功 月，例如利用本發明之堆疊結構’將多個動態隨機記憶體 (DRAM)模組配置於最底層之邏輯電路模組或中央處理器模 組之上’以達到多工運算或多功能之堆疊式晶片封裝結5. Description of the invention (7) The second end 344 of the conductive pin 34 of the element 304 is used for the purpose of a multi-chip module package. Because the stacking is pushed, it is not necessary to achieve the crystal after the large surface area is provided by the conventional carrier ... The surface is directly lifted by the chip packaging unit 302 of the first layer, but the shape is S0. Or flat tetragonal structure, the Japanese-style film packaging structure 300 of the present invention has an approximately columnar hair, and the size can be greatly reduced, so as to achieve the purpose of miniaturizing a chip to enclose a large package and its bearing surface array. The invented stacked wafer cracking structure 300 uses a ball grid array package (BGA) structure as each of the chip packaging units 302, 304, and 304. The two have the advantage of a high pin count and are stacked on top of each other. The chip packaging unit continues. . 306 is directly connected to each other electrically by solder balls 35 to shorten the length of the electrical connection between the chips 302, 304, and 306, so it can be reduced. The delay between the two chips 320 due to the long signal transmission path. In addition, the pin holder has a high heat transfer coefficient, which can quickly absorb the heat generated by the chip, so it helps to improve the heat dissipation effect of the chip packaging units 302, 304, and 306. Furthermore, as shown in FIG. 4, a plurality of heat sinks 346 of the same material as the lead frame can be arranged in the central or corner area of the lead frame, which can also improve the heat dissipation effect of the chip packaging units 302, 304, and 306. Although the present invention is described with a preferred embodiment, it is not limited to use the same package size of the chip packaging unit, and different sizes or different types = chip packaging units can also be used, and individual chip packaging units can also have different power months, For example, the stacked structure of the present invention is used to 'arrange multiple dynamic random memory (DRAM) modules on the lowest logic circuit module or central processing unit module' to achieve multiplexed or multi-functional stacked chips. Package knot

1227552 一" ---- 五、發明說明（8) _ 構另外，晶片與基板電性連接方々 合，亦可採覆晶接合。 〉’不限定於導線接 % •综上所述’本發明之堆疊式晶片封穿έ…士 點· 褒、，、ϋ構具有下列優 1、本發明之堆疊式晶片封 封裝（BGA)之晶片封裝結構，其言齡乃採用球格陣列 疊之晶片封裝單元俜χ锃太 一円腳數之優點，且相 封裝早兀之間電氣連接的長度，並，，以縮紐晶片 湖流趨勢。 θ夕日日片模組封裝的 2本發明之堆疊式晶片封裝社禮 良與突破，使得堆最& & …冓，由於結構上的改 雖然本發明已以一較佳積此更小型化。 以限定本發明，任何孰==揭露如上’然其並非用 .砷和範圍内，當可作些許之更動盘不脫離本發明之精 護範圍當視後附之申$ # :=飾，因此本發明之保 节明專利祀圍所界定者為準。 第13頁 1〇793twf.ptd 12275521227552 I " ---- V. Description of the invention (8) _ Structure In addition, the chip and the substrate are electrically connected together, and flip-chip bonding can also be used. 〉 'Not limited to the% of wire connection. • In summary, the stacked wafer package of the present invention has the following advantages: 1. The structure has the following advantages: 1. The stacked wafer package of the present invention (BGA) The chip packaging structure is based on the advantages of using a ball grid array stacked chip packaging unit 俜 χ 锃, which is too many feet long, and the length of the electrical connection between the early and early stages of the package. θ Evening Japanese chip module package 2 The present invention's stackable chip packaging company ’s courtesy and breakthroughs have made the stack of & & 冓 由于, due to structural changes, although the present invention has been more compact with a better product . In order to limit the present invention, any === disclosure as above, but it is not useful. Within the range of arsenic and scope, when you can make a few changes without departing from the intensive scope of the present invention, see the attached application $ #: = The definition of Baojieming patent siege of the present invention shall prevail. Page 13 1〇793twf.ptd 1227552

第i圖繪示習知一曰 第2圖繪示f矣 ：曰彳裝、，Ό構的示意圖。 曰a 第圖4:2晶片模組封裝結構的示意圖 片封裝結構的分解ΛΓ一較佳實施例之一種堆疊式 m ^ ^解不思圖以及組裝示意圖。 田、、日不接腳架配置於基板上之俯視示意圖。 【圖式標示說明】 10 〇 ·晶片封裝結構 110 :基板 11 0 a :頂面 11 0 b :底面 112 :上接點 114 :下接點 1 2 0 ·晶片 1 2 2 ·主動表面 124 :銲墊 130 :導線 1 4 0 :封膠 150 :銲球 200(a)、（b) ·晶片封裝單元 21 0 :印刷電路板 3 0 0 ·堆疊式晶片封裝結構 302、304、30 6 :晶片封梦 0 一 310(a) >(b) ^(c) ：Figure i shows the first known figure. Figure 2 shows the f 矣: a schematic diagram of the structure. Figure 4: Schematic diagram of the 2 chip module package structure Decomposition of the chip package structure ΛΓ A stacked m ^ ^ solution diagram and assembly schematic diagram of a preferred embodiment. A schematic plan view of a field tripod mounted on a substrate. [Schematic description] 10 〇 · Wafer package structure 110: substrate 11 0 a: top surface 11 0 b: bottom surface 112: top contact 114: bottom contact 1 2 0 · chip 1 2 2 · active surface 124: solder Pad 130: Conductor 1 40: Sealant 150: Solder ball 200 (a), (b) · Chip package unit 21 0: Printed circuit board 3 0 0 · Stacked chip package structure 302, 304, 30 6: Chip seal Dream 0-310 (a) > (b) ^ (c):

1〇793twf.ptd 第14頁 1227552 圖式簡單說明1〇793twf.ptd Page 14 1227552 Illustration

310a •頂面 310b :底面 312 : 上接點 314 下接點 320 晶片 322 主動表面 324 銲墊 330 導線 340 導電接腳 342 第一端 344 第二端 344a :表面金屬層 346 散熱片 348 封膠 350 銲球 10793twf.ptd 第15頁310a • Top surface 310b: Bottom surface 312: Upper contact 314 Lower contact 320 Chip 322 Active surface 324 Welding pad 330 Wire 340 Conductive pin 342 First end 344 Second end 344a: Surface metal layer 346 Heat sink 348 Sealant 350 Solder Ball 10793twf.ptd Page 15

Claims (1)

1227552 六、申請專利範圍 —種堆豎式晶片封裝結構，至少包括： 设數個晶片封裝單一 包括·· 母泛坚日日片封裝單元主要 數個上接點=於頂：及對應之-底面’並具有複 面，而該也上及複數個下接點配置於該底 二上接點係分別電性連接於該些下接點· 性連接；-晶片’配置於該基板之該頂面上並與該基板電 一接腳架，配置於該基板之該頂面上，兮抱卿加 2對電接腳，每一該些導電接腳具有-第-端： 以及Μ —4—m性連接於該基板之該些上接點； 複數個銲球， 晶片封裝單元之該些第 元彼此電性連接。 分別連接該些下接點以及另一該些 二端’以使相疊之該些晶片封裝單 2·如申請專利範圍第1項所述之堆疊式晶片封裝結 構，其中該些第二端位於該接腳架之中央區域上， 第一端位於該接腳架之周緣區域上。 w二 3·如申請專利範圍第1項所述之堆疊式晶片封褒結 構，其中該基板還具有複數個連接墊，位於該基板之表 面，且該些連接墊係分別電性連接於該些第一端以及該此 上接點。 w二 4·如申請專利範圍第1項所述之堆疊式晶片封裝結 構’其中該些晶片封裝單元係呈一球格陣列封裝型態。1227552 6. Scope of patent application—A kind of stack vertical chip package structure, including at least: Set several chip packages to single include the main top contacts of the female pan-Japanese solar chip packaging unit = at the top: and corresponding-bottom surface 'And has a complex surface, and the upper and lower contacts are arranged on the bottom two and the upper contacts are electrically connected to the lower contacts, respectively; -chips' are arranged on the top surface of the substrate A pin holder is arranged on the top surface of the substrate, and is arranged on the top surface of the substrate. Xi Baoqing adds 2 pairs of electrical pins, each of which has a -th end: and M —4 —m. The upper contacts are connected to the substrate; the plurality of solder balls are electrically connected to each other of the chip packaging unit. Connect the lower contacts and the other two ends, respectively, so as to stack the chip packaging sheets 2. The stacked chip packaging structure described in the first patent application scope, wherein the second ends are located at On the central region of the base, the first end is located on the peripheral region of the base. w23. The stacked wafer encapsulation structure described in item 1 of the scope of the patent application, wherein the substrate further has a plurality of connection pads located on the surface of the substrate, and the connection pads are electrically connected to the respective ones. The first end and the upper contact. w2 4. The stacked chip packaging structure described in item 1 of the scope of the patent application, wherein the chip packaging units are in a ball grid array packaging type. 10793twf.ptd10793twf.ptd 1227552 六、申請專利範圍 構5盆^申清專利範圍第1項所述之堆疊式晶片封裝結 ’ /、中該晶片係以導線接合的方式與該基板電性連接。 拔4如申請專利範圍第1項所述之堆疊式晶片封裝牡 構，JL中兮裳_ g ' 〇 性連接。 曰曰片係以覆晶接合的方式與該第一基板電 7. 如 中 請 專 利 構 ，其 中 該 接 腳 架 8. 一 種 堆 疊 結 括 • 一 第 一 晶 片 封 晶 片， 該 第 晶 片 性 連接 且 該 第 —* 一 第 二 晶 片 封 晶 片， 該 第 —— 晶 片 性 連接 ， 該 第 JIL 晶 由 複數 個 導 電 接 腳 一 端以 及 對 應 之 一 二 基板 9 以 及 複 數 個 銲 球 ， 以 使相 疊 之 該 第 ^— 9. 如 中 請 專 利 第 二端 位 於 該 接 腳 接 腳架 之 周 緣 域 第 如申請專利範圍第1項所述之堆疊式晶片封裝結 該些第二端還具有一表面金屬層。 第 端 ^ w ·"…八π ^ ’其中該些第一端電性連接該第 接該些下接點以及該些第二端， 晶片封裝單元彼此電性連接。 如申明專利範圍第8項所述之堆疊結構，其中該第1227552 VI. Application scope of patent structure 5 The application of the stacked chip package junction described in item 1 of the scope of the patent application, said the chip is electrically connected to the substrate by wire bonding. The stacking chip package structure described in item 1 of the scope of patent application, JL _ g '〇 sexual connection. The chip is electrically connected to the first substrate in a flip-chip bonding manner. 7. The patented structure is claimed, in which the pin holder 8. A stacked structure includes a first wafer encapsulating the wafer, the second wafer being sexually connected and the The first— * a second wafer encapsulating the wafer, the first—wafer-type connection, the JIL crystal is composed of one end of a plurality of conductive pins and corresponding one of the two substrates 9 and a plurality of solder balls, so that the first and second wafers overlap each other. — 9. If the patent claims, the second ends are located in the peripheral area of the pin header. The stacked chip package described in item 1 of the patent application scope. The second ends also have a surface metal layer. The first terminal ^ w · ... eight π ^ ′, wherein the first terminals are electrically connected to the first contacts and the second terminals, and the chip packaging units are electrically connected to each other. The stacked structure described in item 8 of the declared patent scope, wherein the 10793twf.ptd 第17頁 1227552 申請專利範圍 一晶片係以導線接合的方式與該第一基板電性連接。 U•如申請專利範圍第8項所述之堆疊結構，其中該第 一晶片係以覆晶接合的方式與該第一基板電性連接。 一曰1 2、如申請專利範圍第8項所述之堆疊結構，其中該第 二晶片係以導線接合的方式與該第二基板電性連接。 曰1 3 ·如申明專利範圍第8項所述之堆叠結構，其中該第 一晶片係以覆晶接合的方式與該第二基板電性連接。 1 4 一種晶片封裝單元，至少包括： 一基板，具有一頂面及對應之一底面，並具有複數個 $點配置於該頂面以及複數個下接點配置於該底面，而 u二上接點係分別電性連接於該些下接點； 接· 片，配置於該基板之該頂面上並與該基板電性連 接腳所3:了二配置於該基板上’該接腳架由複數個導電 廡之一篦-母該些導電接腳分別具有一第一端以及對 心 弟二端，且該些第一端與該基板電性連接。 更 =·如申請專利範圍第項所述之晶 16 固#球’分別配置於該些下接點。 更 包括至^如―申Μ請專利範圍第14項所述之晶片封褒單元 工了夕―散熱片，配置於該接腳架的中央區域上。 更 包括至/請專利範圍第14項所述之晶片封裝單元 散熱片，配置於該接腳架的角落區域上。 其 中兮桩脇如^申請專利範圍第14項所述之晶片封裝單元 中錢腳架之材質係為銅。10793twf.ptd Page 17 1227552 Scope of patent application A chip is electrically connected to the first substrate by wire bonding. U • The stacked structure according to item 8 of the scope of patent application, wherein the first wafer is electrically connected to the first substrate in a flip-chip bonding manner. One said 12. The stack structure according to item 8 of the scope of the patent application, wherein the second chip is electrically connected to the second substrate by wire bonding. 1 · The stacked structure according to item 8 of the declared patent scope, wherein the first chip is electrically connected to the second substrate in a flip-chip bonding manner. 1 4 A chip packaging unit includes at least: a substrate having a top surface and a corresponding bottom surface, and having a plurality of $ points disposed on the top surface and a plurality of lower contacts disposed on the bottom surface, and u2 is connected on top The points are respectively electrically connected to the lower contacts; the contact pieces are arranged on the top surface of the substrate and are electrically connected to the substrate by a pin 3: the two are arranged on the substrate. One of the plurality of conductive 篦 -female conductive pins has a first end and two opposite ends, respectively, and the first ends are electrically connected to the substrate. More = · The crystal 16 solid #spheres as described in item 1 of the scope of the patent application are respectively arranged at the lower contacts. It also includes the chip encapsulation unit described in "Application No. 14 of the Patent Scope", and a heat sink is arranged on the central area of the pin holder. Furthermore, the heat sink of the chip packaging unit as described in item 14 of the patent scope is arranged on the corner area of the pin holder. Among them, the material of the money tripod in the chip packaging unit described in item 14 of the patent application scope is copper. l〇793twf.ptd 第18頁 1227552 六、申請專利範圍 1 9.如申請專利範圍第1 4項所述之晶片封裝單元，其 中該晶片係以導線接合的方式與該基板電性連接。 2 0.如申請專利範圍第1 4項所述之晶片封裝單元，其 中該晶片係以覆晶接合的方式與該基板電性連接。l〇793twf.ptd Page 18 1227552 6. Scope of patent application 1 9. The chip packaging unit described in item 14 of the scope of patent application, wherein the chip is electrically connected to the substrate by wire bonding. 20. The chip packaging unit according to item 14 of the scope of patent application, wherein the chip is electrically connected to the substrate in a flip-chip bonding manner. 10793twf.ptd 第19頁10793twf.ptd Page 19
TW092116358A 2003-06-17 2003-06-17 Stacked chip package structure TWI227552B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW092116358A TWI227552B (en) 2003-06-17 2003-06-17 Stacked chip package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092116358A TWI227552B (en) 2003-06-17 2003-06-17 Stacked chip package structure

Publications (2)

Publication Number Publication Date
TW200501347A TW200501347A (en) 2005-01-01
TWI227552B true TWI227552B (en) 2005-02-01

Family

ID=35696412

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092116358A TWI227552B (en) 2003-06-17 2003-06-17 Stacked chip package structure

Country Status (1)

Country Link
TW (1) TWI227552B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI419270B (en) * 2011-03-24 2013-12-11 Chipmos Technologies Inc Package on package structure
TWI420642B (en) * 2011-10-12 2013-12-21

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI419270B (en) * 2011-03-24 2013-12-11 Chipmos Technologies Inc Package on package structure
TWI420642B (en) * 2011-10-12 2013-12-21

Also Published As

Publication number Publication date
TW200501347A (en) 2005-01-01

Similar Documents

Publication Publication Date Title
US6900528B2 (en) Stacked mass storage flash memory package
US10622289B2 (en) Stacked chip-on-board module with edge connector
US9640515B2 (en) Multiple die stacking for two or more die
US7598617B2 (en) Stack package utilizing through vias and re-distribution lines
TWI311353B (en) Stacked chip package structure
US7834469B2 (en) Stacked type chip package structure including a chip package and a chip that are stacked on a lead frame
TW200939361A (en) Integrated circuit package system with interposer
US20060125093A1 (en) Multi-chip module having bonding wires and method of fabricating the same
US7615858B2 (en) Stacked-type semiconductor device package
TW200933766A (en) Integrated circuit package system with flip chip
TW200926393A (en) Mountable integrated circuit package system with mounting interconnects
KR100255476B1 (en) Ball grid array package
US20070164411A1 (en) Semiconductor package structure and fabrication method thereof
US20080237833A1 (en) Multi-chip semiconductor package structure
TWI227552B (en) Stacked chip package structure
TWI273687B (en) A stacked multiple integrated circuit die package assembly
JP2003133516A (en) Laminated semiconductor device
CN117334662A (en) Multi-die quad flat non-leaded hybrid package
KR20090074493A (en) Stack package
TW200931630A (en) Back-to-back chip assembling side-up package
KR20040048457A (en) Chip stack package

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent