TWI719292B - 電子組件及其製造方法 - Google Patents

電子組件及其製造方法 Download PDF

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TWI719292B
TWI719292B TW107109814A TW107109814A TWI719292B TW I719292 B TWI719292 B TW I719292B TW 107109814 A TW107109814 A TW 107109814A TW 107109814 A TW107109814 A TW 107109814A TW I719292 B TWI719292 B TW I719292B
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Taiwan
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protective layer
conductive pillar
conductive
groove
opening
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TW107109814A
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English (en)
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TW201913901A (zh
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劉瑋瑋
翁煇翔
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日月光半導體製造股份有限公司
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Abstract

本發明提供一種電子組件，其包括一晶粒、一第一保護層、一第二保護層、一第一導電柱及一第二導電柱。該晶粒包括一導電襯墊。該第一保護層經安置於該晶粒上。該第一保護層限定一第一開口以暴露該晶粒之該導電襯墊。該第二保護層經安置於該第一保護層上。該第二保護層限定一第二開口及一第一凹槽。該第二開口暴露該晶粒之該導電襯墊。該第一導電柱經安置於該第二開口內且電連接至該導電襯墊。該第二導電柱經安置於該第一凹槽內。該第一導電柱之一高度實質上等於該第二導電柱之一高度。該第一凹槽之一底部表面經安置於該第一保護層之一頂部表面與該第二保護層之一頂部表面之間。

Description

電子組件及其製造方法
本發明大體上係關於一種電子組件及其製造方法。更具體而言，本發明係關於一種包括導電柱之電子組件及其製造方法。
在電組件中，保護層經安置於晶粒、晶片或晶圓之主動表面上，且該保護層可具有多個開口以使導電襯墊暴露於用於電連接的晶粒之主動表面上。導電柱經安置於經暴露的導電襯墊上以提供外部電連接，而虛設導電柱形成於保護層上以支撐晶粒(且亦維持共面性)以避免晶粒彎曲或破裂。然而，由於虛設導電柱經安置於保護層上，因此虛設導電柱之頂部部分高於導電柱之頂部部分，其可導致導電柱與外部電路或待接合的電路板之間的斷開。另外，由於虛設導電柱及保護層係由不同材料形成，因此其間的連接可相對較弱。
在一或多個實施例中，一種電子組件包括晶粒、第一保護層、第二保護層、第一導電柱及第二導電柱。該晶粒包括導電襯墊。第一保護層經安置於晶粒上。第一保護層限定第一開口以暴露晶粒之導電襯墊。第二保護層經安置於第一保護層上。第二保護層限定第二開口及第一凹槽。第二開口暴露晶粒之導電襯墊。第一導電柱經安置於第二開口內且電連接至導電襯墊。第二導電柱經安置於第一凹槽內。第一導電柱之高度實質上等於第二導電柱之高度。第一凹槽之底部表面經安置於第一保護層之頂部表面與第二保護層之頂部表面之間。 在一或多個實施例中，一種電子組件包括晶粒、第一保護層、第二保護層、第一導電柱及第二導電柱。該晶粒包括導電襯墊。第一保護層經安置於晶粒上。第一保護層限定第一開口以暴露晶粒之導電襯墊。第二保護層經安置於第一保護層上。第二保護層限定穿透第二保護層之第二開口以暴露晶粒之導電襯墊，且限定部分地穿透第二保護層的第一凹槽。第一導電柱經安置於第二開口內且電連接至導電襯墊。第二導電柱經安置於第一凹槽內。 在一或多個實施例中，一種電子組件包括晶粒、第一保護層、第二保護層、第一導電柱及第二導電柱。晶粒包括導電襯墊。第一保護層經安置於晶粒上。第一保護層限定第一開口以暴露晶粒之導電襯墊。第二保護層經安置於第一保護層上。第二保護層限定穿透第二保護層之第二開口以暴露晶粒之導電襯墊及第一凹槽。第一導電柱經安置於第二開口內且電連接至導電襯墊。第二導電柱經安置於第一凹槽內。第二保護層在第一保護層與第二導電柱之間。第一凹槽之寬度小於第二導電柱之寬度。
下文詳細論述本發明的實施例之結構、製造及使用。然而，應瞭解，該等實施例闡明可實施於廣泛多種特定情境中之許多可應用概念。應理解，以下揭示內容提供實施各種實施例之不同特徵的許多不同實施例或實例。下文出於論述之目的而描述組件及裝置之特定實例。當然，此等組件及配置僅為實例且不意欲為限制性的。 下文使用特定語言揭示於附圖中所說明之實施例(或實例)。然而，將理解，該等實施例或實例並不意欲為限制性的。如相關領域中之一般技術者通常將想到，對本發明實施例之任何更改及修飾，以及揭示於本文中之原理的任何其他應用處於本發明之範疇內。 另外，本發明可在各種實例中重複參考數字及/或字母。此重複係出於簡單性及清晰性之目的，且其本身並不指示所論述之各種實施例及/或組態之間的關係。 圖1說明根據本發明之一些實施例的電子組件1之橫截面視圖。電子組件1包括晶粒10 (或晶片)、保護層11、12及導電柱13、14。 晶粒10具有主動表面101及與該主動表面101相對之背表面102 (亦稱為背面)。晶粒10包括在晶粒10之主動表面101上的至少一個導電襯墊10p。晶粒10可包括半導體基板、一或多個積體電路裝置及其中之一或多個疊對互連結構。積體電路裝置可包括諸如電晶體之主動裝置及/或諸如電阻器、電容器、電感器之被動裝置，或其兩者或兩者以上之組合。 保護層11經安置於晶粒10之主動表面101上。保護層11具有或限定開口11h以暴露導電襯墊10p。在一些實施例中，保護層11可覆蓋導電襯墊10p之部分(例如外圍部分)。可替代地，保護層11完全地暴露導電襯墊10p。在一些實施例中，保護層11為鈍化層，其包括氧化矽、氮化矽、氧化鎵、氧化鋁、氧化鈧、氧化鋯、氧化鑭、氧化鉿或另一金屬或非金屬氧化物或氮化物。在一些實施例中，保護層11之厚度呈約1微米(μm)或約0.5 μm至約3 μm。 保護層12經安置於保護層11上。保護層12具有背離保護層11之第一表面121 (或頂部表面)及與第一表面121相對之第二表面122 (或底部表面)。保護層12具有或限定開口12h以暴露開口11h、導電襯墊10p及保護層11之部分。舉例而言，開口12h之寬度大於開口11h之寬度。保護層12具有或限定凹槽12r，該凹槽在保護層12之第一表面121上而並不完全地穿透(或部分地穿透)保護層12。舉例而言，凹槽12r之底部表面12r2定位於保護層11之頂部表面與保護層12之第一表面121之間的垂直高度處。舉例而言，凹槽12r之深度小於保護層12之厚度。在一些實施例中，保護層12為包括聚醯亞胺或其他合適材料(例如感光性材料)之單層。在一些實施例中，保護層12之厚度為約5 μm或約4 μm至約6 μm。在一些實施例中，凹槽12r之深度為約3 μm，且凹槽12r之底部表面12r2與保護層11之間的距離為約2 μm。 導電柱13經安置於保護層11、12之開口11h、12h內且電接觸或連接至晶粒10之主動表面101上的導電襯墊10p。在一些實施例中，晶種層可經安置於導電柱13與導電襯墊10p之間。晶種層亦可視為導電柱13之部分。在一些實施例中，導電柱13可包括銅。然而，諸如鎳及/或鋁或各種金屬之組合的其他導電材料或其他導電材料亦可用於導電柱13中。 導電柱14經安置於保護層12上。導電柱14之部分在保護層12之凹槽12r內以與凹槽12r之側壁12r1及底部表面12r2相接觸。在一些實施例中，導電柱14之寬度大於凹槽12r之寬度。在一些實施例中，晶種層12s經安置於保護層12之部分、凹槽12r之側壁12r1及底部表面12r2上。舉例而言，晶種層12s在導電柱14與保護層12之間。晶種層12s亦可視為導電柱14之部分。在一些實施例中，導電柱14可包括銅。然而，諸如鎳及/或鋁或各種金屬之組合的其他導電材料或其他導電材料亦可用於導電柱14中。在一些實施例中，導電柱14充當虛設導電柱以提供對電子組件1的支撐而非為晶粒10提供電連接。 在一些實施例中，導電柱13之高度H1實質上等於導電柱14之高度H2。由於導電柱13經安置於導電襯墊10p上而導電柱14經安置於保護層12上且在凹槽12r內，因此導電柱14之頂部部分可高於導電柱13之頂部部分。 在對比電子組件中，用於電連接之導電柱經安置於晶粒之導電襯墊上，且虛設導電柱經直接安置於保護層上。然而，由於導電襯墊與保護層之間的高度差，虛設導電柱之頂部部分高於導電柱之頂部部分，其可導致導電柱與外部電路或待接合之電路板之間斷開。另外，由於虛設導電柱及保護層係由不同材料形成，因此其間的連接相對較弱。在展示於本發明之圖1中之實施例中，藉由使凹槽12r形成於保護層12中而並不完全地穿透保護層12且將虛設導電柱14安置於凹槽12r內，可改良虛設導電柱14之頂部部分與用於電連接之導電柱13之間的非共面性。另外，使虛設導電柱14形成於凹槽12r內可增強虛設導電柱14與保護層12之間的接合力。 圖2說明根據本發明之一些實施例的電子組件2之橫截面視圖。電子組件2類似於圖1中之電子組件1，不同之處在於，在圖2中，保護層22之開口22h的寬度小於保護層11之開口11h的寬度，而在圖1中，保護層12之開口12h的寬度大於保護層11之開口11h的寬度。 參考圖2，保護層22經安置於保護層11上且延伸至保護層11之開口11h中以覆蓋導電襯墊10p之部分。導電柱13經安置於保護層22上且在保護層22之開口22h內以電接觸或連接至導電襯墊10p。 圖3說明根據本發明之一些實施例的電子組件3之橫截面視圖。電子組件3類似於圖2中之電子組件2，不同之處在於，在圖3中，保護層22限定多個凹槽12r及32r。 除如圖2中所示之凹槽12r之外，保護層22進一步限定在保護層22之第一表面221上而並不完全地穿透保護層22的凹槽32r。凹槽32r鄰近於凹槽12r且與凹槽12r間隔開。凹槽32r之底部表面32r2在保護層11之頂部表面與保護層22之第一表面221之間。舉例而言，凹槽32r之深度小於保護層22之厚度。在一些實施例中，凹槽32r之深度為約3 μm，且凹槽32r之底部表面32r2與保護層11之間的距離為約2 μm。 導電柱14之部分在保護層12之凹槽12r及32r內以與凹槽12r及32r之側壁12r1、32r1及底部表面12r2、32r2相接觸。在一些實施例中，導電柱14之寬度大於凹槽12r之寬度及凹槽32r之寬度的總和。在一些實施例中，可取決於設計規格來選擇凹槽之數目。增加凹槽之數目可增強虛設導電柱14與保護層12之間的接合力。 圖4說明根據本發明之一些實施例的電子組件4之橫截面視圖。電子組件4類似於圖2中之電子組件2，不同之處在於，在圖4中，凹槽12r具有階梯形側壁12r1'。凹槽12r之階梯形側壁12r1'可增強虛設導電柱14與保護層22之間的接合力。 圖5A、圖5B及圖5C為根據本發明之一些實施例的在各個階段製造的半導體結構之橫截面視圖。各種圖式已經簡化以更好地理解本發明之態樣。 參考圖5A，提供包括晶粒50的多個晶粒50之晶粒條帶(例如晶圓)。晶粒50包括在晶粒50之主動表面上的至少一個導電襯墊50p。每一晶粒50可包括半導體基板、一或多個積體電路裝置及其中的一或多個疊對互連結構。積體電路裝置可包括諸如電晶體之一或多個主動裝置及/或諸如電阻器、電容器、電感器之被動裝置，或其兩者或兩者以上之組合。 保護層51經安置或形成於晶粒50上。保護層51具有或限定開口51h以暴露導電襯墊50p。在一些實施例中，保護層51可覆蓋導電襯墊50p之部分。可替代地，保護層51完全地暴露導電襯墊50p。在一些實施例中，開口51h可藉由例如選路、蝕刻或其他合適工藝形成。在一些實施例中，保護層51為鈍化層，其包括氧化矽、氮化矽、氧化鎵、氧化鋁、氧化鈧、氧化鋯、氧化鑭、氧化鉿或另一金屬或非金屬氧化物或氮化物。在一些實施例中，保護層51之厚度呈約1 μm。 保護層52經安置或形成於保護層51上。保護層52具有背離保護層51之第一表面521 (或頂部表面)及與第一表面521相對之第二表面522 (或底部表面)。在一些實施例中，保護層52包括聚醯亞胺或其他合適材料(例如感光性材料)。在一些實施例中，保護層52之厚度為約5 μm。 參考圖5B，開口52h經形成以完全地穿透保護層52從而暴露導電襯墊50p、開口51h及保護層51之部分。如圖5B中所示，開口52h之寬度大於開口51h之寬度。可替代地，取決於設計規格，開口52h之寬度可小於或實質上等於開口51h之寬度。在一些實施例中，開口52h可藉由光微影、化學蝕刻、雷射鑽孔或其他合適工藝形成。 參考圖5C，凹槽52r經形成於保護層52之第一表面521上而並不完全地穿透保護層52。舉例而言，凹槽52r之底部表面52r2在保護層51之頂部表面與保護層52之第一表面521之間。舉例而言，凹槽52r之深度小於保護層52之厚度。在一些實施例中，凹槽52r之深度為約3 μm，且凹槽52r之底部表面52r2與保護層51之間的距離為約2 μm。在一些實施例中，凹槽52r可藉由光微影、化學蝕刻、雷射鑽孔或其他合適工藝形成。在一些實施例中，可取決於設計規格而形成超過一個凹槽。在一些實施例中，取決於設計規格，凹槽之側壁52r1可為平面或階梯形結構。 在一些實施例中，導電柱可經形成於開口52h內以電接觸或連接至導電襯墊50p，且導電柱可經形成於凹槽52r內以形成如圖1中所示之電子組件1。在一些實施例中，導電柱可藉由例如電鍍或其他合適技術形成。 如本文中所使用，術語「近似地」、「實質上」、「實質的」及「約」用以描述及解釋小變化。當與事件或情形結合使用時，術語可指代其中事件或情形明確發生的例子以及其中事件或情形極近似於發生的例子。舉例而言，當結合數值使用時，該等術語可指代小於或等於該數值的±10%之變化範圍，諸如小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或者小於或等於±0.05%之變化範圍。舉例而言，若兩個數值之間的差異小於或等於該等值之平均值的±10% (諸如，小於或等於±5%、小於或等於±4%、小於或等於±3%、小於或等於±2%、小於或等於±1%、小於或等於±0.5%、小於或等於±0.1%或小於或等於±0.05%)，則可認為該兩個數值「實質上」或「約」為相同或相等的。舉例而言，「實質上」平行可指代相對於0°而言小於或等於±10°之變化範圍，諸如小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°，或者小於或等於±0.05°之變化範圍。舉例而言，「實質上」垂直可指相對於90°而言小於或等於±10°之角變化範圍，諸如小於或等於±5°、小於或等於±4°、小於或等於±3°、小於或等於±2°、小於或等於±1°、小於或等於±0.5°、小於或等於±0.1°，或者小於或等於±0.05°之變化範圍。 若兩個表面之間的移位不大於5 μm、不大於2 μm、不大於1 μm或不大於0.5 μm，則可認為該兩個表面共面或實質上共面。 如本文中所使用，術語「導電(conductive)」、「電導性(electrically conductive)」及「電導率」指代輸送電流之能力。導電材料通常指示呈現對於電流流動之極小或零阻力之彼等材料。電導率之一個量度為西門子每米(S/m)。通常，導電材料為具有近似地大於104 S/m (諸如至少105 S/m或至少106 S/m)之電導率的一種材料。材料之電導率有時可隨溫度而變化。除非另外規定，否則材料之電導率係在室溫下量測。 如本文中所使用，除非上下文另外明確規定，否則單數術語「一(a/an)」及「該」可包括複數個指代物。在對一些實施例之描述中，提供於另一組件「上」或「上方」之組件可涵蓋前一組件直接在後一組件上(例如，與後一組件實體接觸)的情況以及一或多個介入組件位於前一組件與後一組件之間的情況。 儘管已參考本發明之特定實施例描述且說明本發明，但此等描述及說明並不限制本發明。熟習此項技術者可清楚地理解，可進行各種改變，且可在實施例內替代等效組件而不脫離如由所附申請專利範圍所限定之本發明的真實精神及範疇。說明可不必按比例繪製。歸因於製造程序之類中的變數，本發明中之藝術再現與實際設備之間可存在區別。可存在並未特定說明的本發明之其他實施例。應將本說明書及圖式視為說明性而非限制性的。可做出修改，以使特定情形、材料、物質組成、方法或程序適應於本發明之目標、精神及範疇。所有此類修改意欲在此處所附之申請專利範圍之範疇內。儘管已參考按特定次序執行之特定操作來描述本文中所揭示的方法，但可理解，在不脫離本發明之教示的情況下，可組合、細分，或重新定序此等操作以形成等效方法。因此，除非在本文中特定指示，否則操作之次序及分組並非對本發明之限制。
1‧‧‧電子組件2‧‧‧電子組件3‧‧‧電子組件4‧‧‧電子組件10‧‧‧晶粒10p‧‧‧導電襯墊11‧‧‧保護層11h‧‧‧開口12‧‧‧保護層12h‧‧‧開口12r‧‧‧凹槽12r1‧‧‧側壁12r1'‧‧‧階梯形側壁12r2‧‧‧底部表面12s‧‧‧晶種層13‧‧‧導電柱14‧‧‧導電柱22‧‧‧保護層22h‧‧‧開口32r‧‧‧凹槽32r1‧‧‧側壁32r2‧‧‧底部表面50‧‧‧晶粒50p‧‧‧導電襯墊51‧‧‧保護層51h‧‧‧開口52‧‧‧保護層52h‧‧‧開口52r‧‧‧凹槽52r1‧‧‧側壁52r2‧‧‧底部表面101‧‧‧主動表面102‧‧‧背表面121‧‧‧第一表面/頂部表面122‧‧‧第二表面/底部表面221‧‧‧第一表面521‧‧‧第一表面/頂部表面522‧‧‧第二表面/底部表面H1‧‧‧高度H2‧‧‧高度
當結合附圖閱讀時，根據以下詳細描述最佳地理解本發明之態樣。應注意，各種特徵可能未按比例繪製，且各種特徵之尺寸可出於論述清晰起見而任意增大或減小。 圖1說明根據本發明之一些實施例的電子組件之橫截面視圖； 圖2說明根據本發明之一些實施例的電子組件之橫截面視圖； 圖3說明根據本發明之一些實施例的電子組件之橫截面視圖； 圖4說明根據本發明之一些實施例的電子組件之橫截面視圖；以及 圖5A、圖5B及圖5C說明根據本發明之一些實施例的製造電子組件之方法之各種階段。 貫穿該等圖式及詳細描述使用共同參考數字以指示相同或類似元件。本發明將自結合附圖進行的以下詳細描述而更顯而易見。
1‧‧‧電子組件
10‧‧‧晶粒
10p‧‧‧導電襯墊
11‧‧‧保護層
11h‧‧‧開口
12‧‧‧保護層
12h‧‧‧開口
12r‧‧‧凹槽
12r1‧‧‧側壁
12r2‧‧‧底部表面
12s‧‧‧晶種層
13‧‧‧導電柱
14‧‧‧導電柱
101‧‧‧主動表面
102‧‧‧背表面
121‧‧‧第一表面/頂部表面
122‧‧‧第二表面/底部表面
H1‧‧‧高度
H2‧‧‧高度

Claims (11)

  1. 一種電子組件，其包含：一晶粒，其包括一導電襯墊；安置於該晶粒上之一第一保護層，該第一保護層界定一第一開口以暴露該晶粒之該導電襯墊；安置於該第一保護層上之一第二保護層，該第二保護層界定一第二開口及一第一凹槽，該第二開口暴露該晶粒之該導電襯墊；一第一導電柱，其安置於該第二開口內且電連接至該導電襯墊；及一第二導電柱，其安置於該第一凹槽內，其中該第一導電柱之一高度實質上等於該第二導電柱之一高度，該第一凹槽之一深度小於該第二保護層之一厚度，該第二導電柱經由該第一凹槽之一底部表面及該第一凹槽之複數個側壁上的一晶種層直接接觸該第二保護層，且該第一開口之一寬度小於該第二開口之一寬度。
  2. 如請求項1之電子組件，其中該第一凹槽之一寬度小於該第二導電柱之一寬度。
  3. 如請求項1之電子組件，其中該第二保護層具有背離該第一保護層之一頂部表面及與該第二保護層之該頂部表面相對的一底部表面；且該第一凹槽具有該底部表面及在該第一凹槽之該底部表面與該第二保護層之該頂部表面之間延伸的該等複數個側壁。
  4. 如請求項3之電子組件，其中該第二導電柱亦安置於該第二保護層之該頂部表面。
  5. 如請求項4之電子組件，其進一步包含在該第二導電柱與該第二保護層之該頂部表面之間的該晶種層。
  6. 一種電子組件，其包含：一晶粒，其包括一導電襯墊；安置於該晶粒上之一第一保護層，該第一保護層界定一第一開口以暴露該晶粒之該導電襯墊；安置於該第一保護層上之一第二保護層，該第二保護層界定穿透該第二保護層之一第二開口以暴露該晶粒之該導電襯墊，且界定一第一凹槽；一第一導電柱，其安置於該第二開口內且電連接至該導電襯墊；及一第二導電柱，其安置於該第一凹槽內，其中該第二保護層位於該第一保護層與該第二導電柱之間，該第一凹槽之一寬度小於該第二導電柱之一寬度，該第二保護層為一單層，該第一導電柱與該第一保護層及該第二保護層分離(detached)；相對於界定該第一開口的該第一保護層，該第二保護層傾斜(inclined)並且側向地凹陷(laterally recessed)；且界定該第二開口的該第二保護層與該第一導電柱之間的一間距大於界定該第一開口的該第一保護層與該第一導電柱之間的一間距。
  7. 如請求項6之電子組件，其中該第一凹槽之一深度小於該第二保護層之一厚度。
  8. 如請求項6之電子組件，其中該第二保護層具有背離該第一保護層之一第一表面及與該第一表面相對的一第二表面；且該第一凹槽具有一底部表面及在該第一凹槽之該底部表面與該第二保護層之該第一表面之間延伸的一側壁。
  9. 如請求項8之電子組件，其中該第二導電柱安置於該第二保護層之該第一表面、該第一凹槽之該底部表面及該第一凹槽之該側壁上。
  10. 如請求項9之電子組件，其進一步包含在該第二導電柱與該第二保護層之該第一表面、該第一凹槽之該底部表面及該第一凹槽之該側壁之間的一晶種層。
  11. 如請求項6之電子組件，其中該第一導電柱之一高度實質上等於該第二導電柱之一高度。
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