TWI715792B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI715792B
TWI715792B TW106123800A TW106123800A TWI715792B TW I715792 B TWI715792 B TW I715792B TW 106123800 A TW106123800 A TW 106123800A TW 106123800 A TW106123800 A TW 106123800A TW I715792 B TWI715792 B TW I715792B
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semiconductor
die
logic die
conductive
active surface
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TW106123800A
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TW201832323A (zh
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林柏均
朱金龍
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南亞科技股份有限公司
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Abstract

本揭露係關於一種半導體裝置及其製造方法，該半導體裝置具有以面對面方式堆疊的複數個半導體晶粒。藉由面對面方式垂直堆疊不同功能的晶粒，在不同功能的該等晶粒之間實施一面對面通訊(face-to-face communication)。此外，相較於具有以橫向相鄰方式配置之不同功能晶粒的半導體裝置，本揭露之技術以面對面方式垂直堆疊不同功能的晶粒，因而降低半導體裝置的面積。再者，相較於具有以橫向相鄰方式配置之不同功能晶粒的訊號路徑，本揭露之技術以面對面方式垂直堆疊之不同功能晶粒之訊號路徑較短；因此，本揭露之技術以面對面方式垂直堆疊的不同功能晶粒可應用於高速電子裝置。

Description

半導體裝置及其製造方法
本揭露係關於一種半導體裝置及其製造方法，特別關於一種具有以面對面(face-to-face)方式堆疊之複數個半導體晶粒的半導體裝置及其製造方法。
半導體元件對於許多現代應用而言是重要的。隨著電子技術的進展，半導體元件的尺寸越來越小，而功能越來越大且整合的電路量越來越多。由於半導體元件的尺度微小化，目前晶片上覆晶片(chip-on-chip)技術廣泛用於製造半導體元件。在此半導體封裝的生產中，實施許多製造步驟。
然而，在微小化規模中，半導體元件的製造變得越來越複雜。製造半導體元件的複雜度增加可能造成缺陷，例如電互連不良、產生破裂、或是組件脫層。據此，修飾半導體元件的結構與製造製程仍有許多挑戰。
上文之「先前技術」說明僅係提供背景技術，並未承認上文之「先前技術」說明揭示本揭露之標的，不構成本揭露之先前技術，且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露的實施例提供一種半導體裝置，包括：一半導體邏輯晶粒，具有一第一主動面以及自該半導體邏輯晶粒的該第一主動面延伸至一背面的一內部傳導件；一半導體記憶體晶粒，堆疊至該半導體邏輯晶粒上，其中該半導體邏輯晶粒的該第一主動面面對該半導體記憶體晶粒的一第二主動面；以及一凸塊結構，電連接該第一主動面上的一第一終端至該第二主動面上的一第二終端。
在本揭露的一些實施例中，該半導體裝置另包括一模製件，囊封該半導體邏輯晶粒與該半導體記憶體晶粒。
在本揭露的一些實施例中，該半導體裝置另包括穿過該模製件的一傳導插塞。
在本揭露的一些實施例中，該傳導插塞垂直穿過該模製件。
在本揭露的一些實施例中，該半導體裝置另包括一物件，以及該半導體邏輯晶粒的該背面附接至該物件。
在本揭露的一些實施例中，該物件包括一重佈線層。
在本揭露的一些實施例中，該半導體邏輯晶粒包括一基板與一電互連，以及該內部傳導件包括穿過該基板的一傳導插塞。
在本揭露的一些實施例中，該傳導插塞垂直穿過該基板。
在本揭露的一些實施例中，該半導體記憶體晶粒電連接至該半導體邏輯晶粒，實質上沒有一接合線存在於該半導體記憶體晶粒與該半導體邏輯晶粒之間。
本揭露的另一實施例提供一種半導體裝置的製造方法，包括：附接一半導體記憶體晶粒至一載體基板；以一面對面方式堆疊一半導體邏輯晶粒至該半導 體記憶體晶粒上；形成一模製件於該載體基板上方，其中該模製件環繞該半導體記憶體晶粒與該半導體邏輯晶粒；以及移除該載體基板。
在本揭露的一些實施例中，該製造方法另包括：形成一物件於該半導體記憶體晶粒的一背面上方，其中該物件實現該半導體裝置的一橫向信號路徑。
在本揭露的一些實施例中，形成該物件包括形成一重佈線層。
在本揭露的一些實施例中，該製造方法另包括形成複數個傳導凸塊於該物件上方。
在本揭露的一些實施例中，該製造方法另包括在形成該模製件於該載體基板上方之前，形成一傳導插塞於該載體基板上方。
在本揭露的一些實施例中，該半導體邏輯晶粒具有一第一主動面，該半導體記憶體晶粒具有一第二主動面，以及該半導體邏輯晶粒附接至該半導體記憶體晶粒時，該半導體邏輯晶粒的該第一主動面面對該半導體記憶體晶粒的該第二主動面。
在本揭露的一些實施例中，該半導體邏輯晶粒具有一內部傳導件，自該半導體邏輯晶粒的該第一主動面延伸至一背面。
在本揭露的一些實施例中，該半導體記憶體晶粒電連接至該半導體邏輯晶粒，實質上沒有一街和現存在於該半導體記憶體晶粒與該半導體邏輯晶粒之間。
本揭露係關於一種半導體裝置及其製造方法，該半導體裝置具有以面對面方式堆疊的複數個半導體晶粒。藉由以面對面方式垂直堆疊之不同功能晶粒，在不同功能晶粒之間實施面對面通訊。此外，相較於具有以橫向相鄰方式配置之不同功能晶粒的半導體裝置，本揭露之技術以面對面方式 垂直堆疊不同功能的晶粒，因而降低半導體裝置的面積。再者，相較於具有以橫向相鄰方式配置之不同功能晶粒的訊號路徑，本揭露之技術以面對面方式垂直堆疊之不同功能晶粒之訊號路徑較短；因此，本揭露之技術以面對面方式垂直堆疊的不同功能晶粒可應用於高速電子裝置。
上文已相當廣泛地概述本揭露之技術特徵及優點，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
10A:半導體裝置
10B:半導體裝置
11:重佈線層
11A:傳導線
11B:傳導線
11C:傳導線
13A:半導體記憶體晶粒
13B:半導體邏輯晶粒
15:模製件
15A:傳導插塞
100A:半導體裝置
100B:半導體裝置
110A:半導體邏輯晶粒
110B:半導體記憶體晶粒
111A:第一主動面
111B:第二主動面
113A:第一背面
113B:第二背面
115:模製件
115A:傳導插塞
117:電凸塊結構
200:物件
201:傳導凸塊
203:傳導線
205:介電堆疊
400:載體基板
401:遮罩層
403:開口
405:單粒化工具
1101A:基板
1101B:基板
1103A:電互連
1103B:電互連
1105A:第一終端
1105B:第二終端
1171:凸塊
1173:焊料
1191:傳導插塞
1193:接線
119:內部傳導件
參閱詳細說明與申請專利範圍結合考量圖式時，可得以更全面了解本申請案之揭示內容，圖式中相同的元件符號係指相同的元件。
圖1為剖面示意圖，例示本揭露比較例的半導體裝置。
圖2為剖面示意圖，例示本揭露實施例的半導體裝置。
圖3為分解示意圖，說明圖2所示之半導體裝置。
圖4為剖面示意圖，例示本揭露比較例的半導體裝置。
圖5為剖面示意圖，例示本揭露實施例的半導體裝置。
圖6為流程圖，例示本揭露實施例之半導體裝置的製造方法。
圖7至圖13為示意圖，例示本揭露實施例藉由圖6之方法製造半導體裝置的製程。
本揭露之以下說明伴隨併入且組成說明書之一部分的圖式，說明本揭露之實施例，然而本揭露並不受限於該實施例。此外，以下的實施例可適當整合以下實施例以完成另一實施例。
「一實施例」、「實施例」、「例示實施例」、「其他實施例」、「另一實施例」等係指本揭露所描述之實施例可包含特定特徵、結構或是特性，然而並非每一實施例必須包含該特定特徵、結構或是特性。再者，重複使用「在實施例中」一語並非必須指相同實施例，然而可為相同實施例。
本揭露係關於一種半導體結構裝置及其製造方法，該半導體裝置具有複數個以面對面方式堆疊的半導體晶粒。為了使得本揭露可被完全理解，以下說明提供詳細的步驟與結構。顯然，本揭露的實施不會限制該技藝中的技術人士已知的特定細節。此外，已知的結構與步驟不再詳述，以免不必要地限制本揭露。本揭露的較佳實施例詳述如下。然而，除了詳細說明之外，本揭露亦可廣泛實施於其他實施例中。本揭露的範圍不限於詳細說明的內容，而是由申請專利範圍定義。
圖1為剖面示意圖，例示本揭露比較例的半導體裝置10A。半導體裝置10A包含：重佈線層11；位於重佈線層11上的半導體記憶體晶粒13A與半導體邏輯晶粒13B；模製件15，囊封重佈線層11上的半導體記憶體晶粒13A與半導體邏輯晶粒13B；以及附接至重佈線層11的複數個傳導凸塊17。在一些實施例中，傳導凸塊17位於重佈線層11的底側上，而半導體記憶體晶粒13A與半導體邏輯晶粒13B位於重佈線層11的上側。
在一些實施例中，藉由重佈線層11中的傳導線11A與傳導凸塊17，實現半導體記憶體晶粒13A的垂直信號路徑，藉由重佈線層11中的傳導線11B與傳導凸塊17，實現半導體邏輯晶粒13B的垂直信號路徑，以及藉由重 佈線層11中的傳導線11C實現半導體記憶體晶粒13A與半導體邏輯晶粒13B之間的橫向信號路徑，而不使用傳導凸塊17。
圖2為剖面示意圖，例示本揭露實施例的半導體裝置100A，以及圖3為分解示意圖，說明圖2所示之半導體裝置100A。在一些實施例中，半導體裝置100A包括：物件200；附接至物件200的半導體邏輯晶粒110A；以面對面方式附接至半導體邏輯晶粒110A的半導體記憶體晶粒110B；以及模製件115，囊封半導體邏輯晶粒110A與半導體記憶體晶粒110B。
在一些實施例中，半導體邏輯晶粒110A包括基板1101A以及在基板1101A上的電互連1103A，半導體記憶體晶粒110B包括基板1101B以及在基板1101B上的電互連1103B。在一些實施例中，半導體邏輯晶粒110A具有第一主動面111A(電互連1103A的正面)與第一背面113A，以及半導體記憶體晶粒110B具有第二主動面111B(電互連1103B的正面)與第二背面113B。在一些實施例中，在面對面堆疊中，半導體邏輯晶粒110A的第一主動面111A面對半導體記憶體晶粒110B的第二主動面111B。
在一些實施例中，基板1101A與基板1101B可為矽基板、絕緣體上覆半導體(semiconductor-on-insulator，SOI)基板、或包括半導體材料的任何架構；以及電互連1103A與電互連1103B包括介電材料以及由例如Ti、Al、Ni、鎳釩(NiV)、Cu、或銅合金製成的傳導元件。在一些實施例中，模製件115可為單層膜或複合堆疊。在一些實施例中，模製件115包含各種材料，例如模塑料、模塑底膠填充(molding underfill)、環氧化合物、樹脂、或類似物。在一些實施例中，模製件115具有高傳熱性、低吸濕速度以及高抗彎強度(flexural strength)。
在一些實施例中，半導體邏輯晶粒110A包含積體電路(IC)或半導體組件，例如電晶體、電容器、電阻器、二極體、光二極體、熔絲、以及類似物，經配置以進行一或多種功能，其中在本揭露中為清楚說明而未繪示該IC與半導體組件。在一些實施例中，半導體記憶體晶粒110B為記憶體晶片，例如DRAM(動態隨機存取記憶體)晶片，半導體邏輯晶粒110A為邏輯晶粒，例如CPU(中心處理單元)/GPU(圖形處理單元)晶片。已知記憶體晶片包括用於定址(addressing)記憶體胞元的位址輸入終端、用於輸入資料至記憶體胞元且自記憶體胞元輸出資料的資料輸入/輸出終端、以及電源供應終端。
在一些實施例中，半導體邏輯晶粒110A包括複數個第一終端1105A於第一主動面111A上，半導體記憶體晶粒110B包括複數個第二終端1105B於第二主動面111B上，以及第一終端1105A經由電凸塊結構117而電連接至第二終端，該電凸塊結構117包含凸塊1171與焊料1173，實質上沒有接合線存在於半導體記憶體晶粒110B與半導體邏輯晶粒110A之間。
在一些實施例中，半導體邏輯晶粒110A具有複數個內部傳導件119，自半導體邏輯晶粒110A的第一主動面111A延伸至第一背面113A。在一些實施例中，內部傳導件119包括垂直穿過基板1101A的傳導插塞1191(貫穿矽插塞)以及電互連1103A中的接線(wire)1193。
在一些實施例中，物件200為重佈線層。在一些實施例中，重佈線層包括介電堆疊205以及位於介電堆疊205中的一些傳導線203。傳導線203具有第一傳導終端於上側用於電連接至傳導插塞1191，以及第二傳導終端於底側用於電連接至傳導凸塊201。傳導線203亦用於形成該等傳導插塞 1191之間的電連接。在一些實施例中，傳導線203由銅、金、銀、鎳、焊料、錫、鉛、鎢、鋁、鈦、鈀、或其合金製成。
在一些實施例中，以面對面方式垂直堆疊具有不同功能的晶粒(例如半導體邏輯晶粒110A與半導體記憶體晶粒110B)，在不同功能的晶粒之間實施面對面通訊(face-to-face communication)。此外，相較於具有以橫向相鄰方式配置之不同功能晶粒(半導體記憶體晶粒13A與半導體邏輯晶粒13B)的半導體裝置10A，以面對面方式垂直堆疊不同功能的晶粒(半導體邏輯晶粒110A與半導體記憶體晶粒110B)降低半導體裝置100A的佔據面積。再者，相較於具有以橫向相鄰方式配置之不同功能晶粒的訊號路徑，具有以面對面方式垂直堆疊的不同功能晶粒之訊號路徑較短；因此，本揭露之以面對面方式垂直堆疊的不同功能晶粒可應用於高速電子裝置。
圖4為剖面示意圖，例示本揭露比較例之半導體裝置10B。圖4所示之半導體裝置10B與圖1所示之半導體裝置10A實質相同，差別在於貫穿模塑插塞(through molding via)的設計。在圖1中，半導體裝置10A的模製件15沒有貫穿模塑插塞，然而在圖4中，一些傳導插塞(貫穿模塑插塞)15A配置於圖4之半導體裝置10B的模製件15中。在一些實施例中，傳導插塞15A貫穿模製件15，以形成垂直信號路徑於底側上的物件200與另一物件之間，該另一物件例如在傳導插塞15A之上側的電路基板。
圖5為剖面示意圖，例示本揭露實施例之半導體裝置100B。圖5所示之半導體裝置100B與圖2所示之半導體裝置100A實質相同，差別在於貫穿模塑插塞的設計。在圖2中，半導體裝置100A的模製件115沒有貫穿模塑插塞，然而在圖5中，一些傳導插塞(貫穿模塑插塞)115A配置於半導體裝置100B的模製件115中。在一些實施例中，該等傳導插塞115A貫穿模製件115 以形成垂直信號路徑於底側上的物件200與另一物件之間，該另一物件例如在傳導插塞115A之上側的電路基板。
在本揭露中，亦揭露一種半導體裝置的製造方法。在一些實施例中，可藉由圖6所示之方法300形成半導體裝置。方法300包含一些操作，並且描述與說明不被視為操作順序的限制。方法300包含一些步驟(301、303、305、307、309與311)。
圖7至圖13為示意圖，例示本揭露實施例藉由圖6之方法製造半導體裝置的製程。在步驟301中，形成傳導插塞115A於載體基板400上方，如圖7與圖8所示。在一些實施例中，形成傳導插塞115A包含形成遮罩層401，具有開口403於載體基板400上方，如圖7所示，以傳導材料填充開口403，而後自載體基板400移除遮罩層401以形成傳導插塞115A於載體基板400上方，如圖8所示。
在步驟303中，半導體記憶體晶粒110B附接至載體基板400，如圖9所示。在一些實施例中，半導體記憶體晶粒110B包括基板1101B以及在基板1101B上的電互連1103B，其中電互連1103B的正面(半導體記憶體晶粒110B的主動面111B)面朝上，以及基板1101B的背面(半導體記憶體晶粒110B的背面113B)附接至載體基板400。
在步驟305中，具有凸塊結構117的半導體邏輯晶粒110A以面對面方式堆疊至半導體記憶體晶粒110B上，凸塊結構117介於半導體邏輯晶粒110A與半導體記憶體晶粒110B之間，如圖10所示。在一些實施例中，半導體邏輯晶粒110A包括基板1101A以及在基板1101A上的電互連1103A，其中電互連1103A的正面(半導體邏輯晶粒110A的主動面111A)面朝下，因 而半導體邏輯晶粒110A的主動面111A面對半導體記憶體晶粒110B的主動面，亦即面對面堆疊。
在步驟307中，於載體基板400上方形成模製件115，如圖11所示。在一些實施例中，在模製件115形成於載體基板400上方之前，於載體基板400上方形成或附接傳導插塞115A、半導體邏輯晶粒110A與半導體記憶體晶粒110B；因此，模製件115環繞傳導插塞115A、半導體邏輯晶粒110A與半導體記憶體晶粒110B。
在步驟309中，在半導體邏輯晶粒110A的背面113A上方形成物件200，例如重佈線層，如圖12所示。在一些實施例中，藉由沉積、微影與蝕刻製程，形成該重佈線層。此外，在該重佈線層上方形成一些傳導凸塊201。在一些實施例中，在形成模製件115之後，形成該重佈線層。
在步驟311中，移除載體基板400，並且進行單粒化製程，將半導體裝置100B切割為分隔的(separated)半導體封裝。在一些實施例中，以晶粒切割或單粒化工具405，進行單粒化製程，例如使用機械或雷射鋸，切割穿過個別晶片或晶粒之間的基板。在一些實施例中，雷射鋸使用氬(Ar)為基礎的離子雷射束工具。
本揭露係關於一種半導體裝置及其製造方法，該半導體裝置具有以面對面方式堆疊的複數個半導體晶粒。藉由以面對面方式垂直堆疊之不同功能晶粒，在不同功能晶粒之間實施面對面通訊。此外，相較於具有以橫向相鄰方式配置之不同功能晶粒的半導體裝置，本揭露之技術以面對面方式垂直堆疊不同功能的晶粒，因而降低半導體裝置的面積。再者，相較於具有以橫向相鄰方式配置之不同功能晶粒的訊號路徑，本揭露之技術以面對 面方式垂直堆疊之不同功能晶粒之訊號路徑較短；因此，本揭露之技術以面對面方式垂直堆疊的不同功能晶粒可應用於高速電子裝置。
本揭露的一實施例提供一種半導體裝置，包含具有一第一主動面的一半導體邏輯晶粒以及自該半導體邏輯晶粒之該第一主動面延伸至一背面的一內部傳導件；一半導體記憶體晶粒堆疊至該半導體邏輯晶粒上，其中該半導體邏輯晶粒的該第一主動面面對該半導體記憶體晶粒的一第二主動面；以及一凸塊結構，電連接該第一主動面上的一第一終端至該第二主動面上的一第二終端。
本揭露的另一實施例提供一種半導體裝置的製造方法，包含：附接一半導體記憶體晶粒至一載體基板；以一面對面方式堆疊一半導體邏輯晶粒至該半導體記憶體晶粒上；形成一模製件於該載體基板上，其中該模製件環繞該半導體記憶體晶粒與該半導體邏輯晶粒；以及移除該載體基板。
雖然已詳述本揭露及其優點，然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如，可用不同的方法實施上述的許多製程，並且以其他製程或其組合替代上述的許多製程。
再者，本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此，此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
100A‧‧‧半導體裝置
110A‧‧‧半導體邏輯晶粒
110B‧‧‧半導體記憶體晶粒
111A‧‧‧第一主動面
111B‧‧‧第二主動面
113A‧‧‧第一背面
113B‧‧‧第二背面
115‧‧‧模製件
117‧‧‧電凸塊結構
200‧‧‧物件
201‧‧‧傳導凸塊
203‧‧‧傳導線
205‧‧‧介電堆疊
1101A‧‧‧基板
1103A‧‧‧電互連
1191‧‧‧傳導插塞

Claims (10)

  1. 一種半導體裝置，包括：一半導體邏輯晶粒，具有一第一主動面與一內部傳導件，該內部傳導件自該半導體邏輯晶粒的該第一主動面延伸至一背面；一半導體記憶體晶粒，堆疊至該半導體邏輯晶粒上，其中該半導體邏輯晶粒的該第一主動面面對該半導體記憶體晶粒的一第二主動面；一凸塊結構，電連接該第一主動面上的一第一終端至該第二主動面上的一第二終端；一模製件，囊封該半導體邏輯晶粒與該半導體記憶體晶粒；以及一第一傳導插塞，穿過該模製件；其中該半導體裝置另包括一物件，該物件包括一重佈線層，其中該半導體邏輯晶粒的該背面附接至該物件之該重佈線層，且該重佈線層包含介電堆疊及位於該介電堆疊中之複數個傳導線，該複數個傳導線具有用於電連接至該第一傳導插塞之傳導終端。
  2. 如請求項1所述之半導體裝置，其中該第一傳導插塞垂直穿過該模製件。
  3. 如請求項1所述之半導體裝置，其中該半導體邏輯晶粒包括一基板與一電互連，以及該內部傳導件包括穿過該基板的一第二傳導插塞。
  4. 如請求項5所述之半導體裝置，其中該第二傳導插塞垂直穿過該基板。
  5. 如請求項1所述之半導體裝置，其中該半導體記憶體晶粒電連接至該半導體邏輯晶粒，實質上沒有一接合線存在於該半導體記憶體晶粒與該半導體邏輯晶粒之間。
  6. 一種半導體裝置的製造方法，包括：附接一半導體記憶體晶粒至一載體基板；以一面對面方式堆疊一半導體邏輯晶粒至該半導體記憶體晶粒上；形成一傳導插塞於該載體基板上方；形成一模製件於該載體基板上，其中該模製件環繞該傳導插塞、該半導體記憶體晶粒與該半導體邏輯晶粒；以及移除該載體基板；其中該製造方法另包含：形成一物件於該半導體邏輯晶粒的一背面上方，其中該物件實現該半導體裝置的一橫向信號路徑，其中形成該物件包括形成一重佈線層，且其中該重佈線層包含介電堆疊及位於該介電堆疊中之複數個傳導線，該複數個傳導線具有用於電連接至該傳導插塞之傳導終端。
  7. 如請求項6所述之製造方法，另包括：形成複數個傳導凸塊於該物件上方。
  8. 如請求項6所述之製造方法，其中該半導體邏輯晶粒具有一第一主動面，該半導體記憶體晶粒具有一第二主動面，以及該半導體邏輯晶粒附接 至該半導體記憶體晶粒時，該半導體邏輯晶粒的該第一主動面面對該半導體記憶體晶粒的該第二主動面。
  9. 如請求項8所述之製造方法，其中該半導體邏輯晶粒具有一內部傳導件，自該半導體邏輯晶粒的該第一主動面延伸至一背面。
  10. 如請求項6所述之製造方法，其中該半導體記憶體晶粒電連接至該半導體邏輯晶粒，實質上沒有一接合線存在於該半導體記憶體晶粒與該半導體邏輯晶粒之間。
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