CN108447859A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN108447859A
CN108447859A CN201710616913.XA CN201710616913A CN108447859A CN 108447859 A CN108447859 A CN 108447859A CN 201710616913 A CN201710616913 A CN 201710616913A CN 108447859 A CN108447859 A CN 108447859A
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China
Prior art keywords
crystal grain
semiconductor
logic
face
semiconductor device
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CN201710616913.XA
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English (en)
Inventor
林柏均
朱金龙
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Nanya Technology Corp
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Nanya Technology Corp
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Publication of CN108447859A publication Critical patent/CN108447859A/zh
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Abstract

本公开涉及一种半导体装置及其制造方法，该半导体装置具有以面对面方式堆迭的多个半导体晶粒。通过面对面方式垂直堆迭不同功能的晶粒，在不同功能的所述晶粒之间实施一面对面通信(face‑to‑face communication)。此外，相较于具有以横向相邻方式配置的不同功能晶粒的半导体装置，本公开的技术以面对面方式垂直堆迭不同功能的晶粒，因而降低半导体装置的面积。再者，相较于具有以横向相邻方式配置的不同功能晶粒的信号路径，本公开的技术以面对面方式垂直堆迭的不同功能晶粒的信号路径较短；因此，本公开的技术以面对面方式垂直堆迭的不同功能晶粒可应用于高速电子装置。

Description

半导体装置及其制造方法
技术领域
本公开涉及一种半导体装置及其制造方法，特别关于一种具有以面对面(face-to-face)方式堆迭的多个半导体晶粒的半导体装置及其制造方法。
背景技术
半导体元件对于许多现代应用而言是重要的。随着电子技术的进展，半导体元件的尺寸越来越小，而功能越来越大且整合的电路量越来越多。由于半导体元件的尺度微小化，目前芯片上覆芯片(chip-on-chip)技术广泛用于制造半导体元件。在此半导体封装的生产中，实施许多制造步骤。
然而，在微小化规模中，半导体元件的制造变得越来越复杂。制造半导体元件的复杂度增加可能造成缺陷，例如电互连不良、产生破裂、或是组件脱层。据此，修饰半导体元件的结构与制造制程仍有许多挑战。
上文的「现有技术」说明仅是提供背景技术，并未承认上文的「现有技术」说明公开本公开的标的，不构成本公开的现有技术，且上文的「现有技术」的任何说明均不应作为本公开的任一部分。
发明内容
本公开的实施例提供一种半导体装置，包括：一半导体逻辑晶粒，具有一第一主动面以及自该半导体逻辑晶粒的该第一主动面延伸至一背面的一内部传导件；一半导体存储器晶粒，堆迭至该半导体逻辑晶粒上，其中该半导体逻辑晶粒的该第一主动面面对该半导体存储器晶粒的一第二主动面；以及一凸块结构，电连接该第一主动面上的一第一终端至该第二主动面上的一第二终端。
在本公开的一些实施例中，该半导体装置另包括一模制件，囊封该半导体逻辑晶粒与该半导体存储器晶粒。
在本公开的一些实施例中，该半导体装置另包括穿过该模制件的一传导插塞。
在本公开的一些实施例中，该传导插塞垂直穿过该模制件。
在本公开的一些实施例中，该半导体装置另包括一物件，以及该半导体逻辑晶粒的该背面附接至该物件。
在本公开的一些实施例中，该物件包括一重布线层。
在本公开的一些实施例中，该半导体逻辑晶粒包括一基板与一电互连，以及该内部传导件包括穿过该基板的一传导插塞。
在本公开的一些实施例中，该传导插塞垂直穿过该基板。
在本公开的一些实施例中，该半导体存储器晶粒电连接至该半导体逻辑晶粒，实质上没有一接合线存在于该半导体存储器晶粒与该半导体逻辑晶粒之间。
本公开的另一实施例提供一种半导体装置的制造方法，包括：附接一半导体存储器晶粒至一载体基板；以一面对面方式堆迭一半导体逻辑晶粒至该半导体存储器晶粒上；形成一模制件于该载体基板上方，其中该模制件环绕该半导体存储器晶粒与该半导体逻辑晶粒；以及移除该载体基板。
在本公开的一些实施例中，该制造方法另包括：形成一物件于该半导体存储器晶粒的一背面上方，其中该物件实现该半导体装置的一横向信号路径。
在本公开的一些实施例中，形成该物件包括形成一重布线层。
在本公开的一些实施例中，该制造方法另包括形成多个传导凸块于该物件上方。
在本公开的一些实施例中，该制造方法另包括在形成该模制件于该载体基板上方之前，形成一传导插塞于该载体基板上方。
在本公开的一些实施例中，该半导体逻辑晶粒具有一第一主动面，该半导体存储器晶粒具有一第二主动面，以及该半导体逻辑晶粒附接至该半导体存储器晶粒时，该半导体逻辑晶粒的该第一主动面面对该半导体存储器晶粒的该第二主动面。
在本公开的一些实施例中，该半导体逻辑晶粒具有一内部传导件，自该半导体逻辑晶粒的该第一主动面延伸至一背面。
在本公开的一些实施例中，该半导体存储器晶粒电连接至该半导体逻辑晶粒，实质上没有一接合线存在于该半导体存储器晶粒与该半导体逻辑晶粒之间。
本公开涉及一种半导体装置及其制造方法，该半导体装置具有以面对面方式堆迭的多个半导体晶粒。通过以面对面方式垂直堆迭的不同功能晶粒，在不同功能晶粒之间实施面对面通信。此外，相较于具有以横向相邻方式配置的不同功能晶粒的半导体装置，本公开的技术以面对面方式垂直堆迭不同功能的晶粒，因而降低半导体装置的面积。再者，相较于具有以横向相邻方式配置的不同功能晶粒的信号路径，本公开的技术以面对面方式垂直堆迭的不同功能晶粒的信号路径较短；因此，本公开的技术以面对面方式垂直堆迭的不同功能晶粒可应用于高速电子装置。
上文已相当广泛地概述本公开的技术特征及优点，俾使下文的本公开详细描述得以获得优选了解。构成本公开的权利要求标的的其它技术特征及优点将描述于下文。本公开所属技术领域技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或制程而实现与本公开相同的目的。本公开所属技术领域技术人员亦应了解，这类等效建构无法脱离所附的权利要求所界定的本公开的构思和范围。
附图说明
参阅详细说明与权利要求结合考量附图时，可得以更全面了解本申请的公开内容，附图中相同的元件符号是指相同的元件。
图1为剖面示意图，例示本公开比较例的半导体装置。
图2为剖面示意图，例示本公开实施例的半导体装置。
图3为分解示意图，说明图2所示的半导体装置。
图4为剖面示意图，例示本公开比较例的半导体装置。
图5为剖面示意图，例示本公开实施例的半导体装置。
图6为流程图，例示本公开实施例的半导体装置的制造方法。
图7至图13为示意图，例示本公开实施例通过图6的方法制造半导体装置的制程。
附图标记说明：
10A 半导体装置
10B 半导体装置
11 重布线层
11A 传导线
11B 传导线
11C 传导线
13A 半导体存储器晶粒
13B 半导体逻辑晶粒
15 模制件
15A 传导插塞
100A 半导体装置
100B 半导体装置
110A 半导体逻辑晶粒
110B 半导体存储器晶粒
111A 第一主动面
111B 第二主动面
113A 第一背面
113B 第二背面
115 模制件
115A 传导插塞
117 电凸块结构
200 物件
201 传导凸块
203 传导线
205 介电堆迭
400 载体基板
401 遮罩层
403 开口
405 单粒化工具
1101A 基板
1101B 基板
1103A 电互连
1103B 电互连
1105A 第一终端
1105B 第二终端
1171 凸块
1173 焊料
1191 传导插塞
1193 接线
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的附图，说明本公开的实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
「一实施例」、「实施例」、「例示实施例」、「其他实施例」、「另一实施例」等是指本公开所描述的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用「在实施例中」一语并非必须指相同实施例，然而可为相同实施例。
本公开涉及一种半导体结构装置及其制造方法，该半导体装置具有多个以面对面方式堆迭的半导体晶粒。为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制该技艺中的技术人士已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的优选实施例详述如下。然而，除了详细说明之外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于详细说明的内容，而是由权利要求定义。
图1为剖面示意图，例示本公开比较例的半导体装置10A。半导体装置10A包含：重布线层11；位于重布线层11上的半导体存储器晶粒13A与半导体逻辑晶粒13B；模制件15，囊封重布线层11上的半导体存储器晶粒13A与半导体逻辑晶粒13B；以及附接至重布线层11的多个传导凸块17。在一些实施例中，传导凸块17位于重布线层11的底侧上，而半导体存储器晶粒13A与半导体逻辑晶粒13B位于重布线层11的上侧。
在一些实施例中，通过重布线层11中的传导线11A与传导凸块17，实现半导体存储器晶粒13A的垂直信号路径，通过重布线层11中的传导线11B与传导凸块17，实现半导体逻辑晶粒13B的垂直信号路径，以及通过重布线层11中的传导线11C实现半导体存储器晶粒13A与半导体逻辑晶粒13B之间的横向信号路径，而不使用传导凸块17。
图2为剖面示意图，例示本公开实施例的半导体装置100A，以及图3为分解示意图，说明图2所示的半导体装置100A。在一些实施例中，半导体装置100A包括：物件200；附接至物件200的半导体逻辑晶粒110A；以面对面方式附接至半导体逻辑晶粒110A的半导体存储器晶粒110B；以及模制件115，囊封半导体逻辑晶粒110A与半导体存储器晶粒110B。
在一些实施例中，半导体逻辑晶粒110A包括基板1101A以及在基板1101A上的电互连1103A，半导体存储器晶粒110B包括基板1101B以及在基板1101B上的电互连1103B。在一些实施例中，半导体逻辑晶粒110A具有第一主动面111A(电互连1103A的正面)与第一背面113A，以及半导体存储器晶粒110B具有第二主动面111B(电互连1103B的正面)与第二背面113B。在一些实施例中，在面对面堆迭中，半导体逻辑晶粒110A的第一主动面111A面对半导体存储器晶粒110B的第二主动面111B。
在一些实施例中，基板1101A与基板1101B可为硅基板、绝缘体上覆半导体(semiconductor-on-insulator，SOI)基板、或包括半导体材料的任何架构；以及电互连1103A与电互连1103B包括介电材料以及由例如Ti、Al、Ni、镍钒(NiV)、Cu、或铜合金制成的传导元件。在一些实施例中，模制件115可为单层膜或复合堆迭。在一些实施例中，模制件115包含各种材料，例如模塑料、模塑底胶填充(molding underfill)、环氧化合物、树脂、或类似物。在一些实施例中，模制件115具有高传热性、低吸湿速度以及高抗弯强度(flexuralstrength)。
在一些实施例中，半导体逻辑晶粒110A包含集成电路(IC)或半导体组件，例如晶体管、电容器、电阻器、二极管、光二极管、熔丝、以及类似物，经配置以进行一或多种功能，其中在本公开中为清楚说明而未示出的该IC与半导体组件。在一些实施例中，半导体存储器晶粒110B为存储器芯片，例如DRAM(动态随机存取存储器)芯片，半导体逻辑晶粒110A为逻辑晶粒，例如CPU(中心处理单元)/GPU(图形处理单元)芯片。已知存储器芯片包括用于定址(addressing)存储器胞元的位址输入终端、用于输入数据至存储器胞元且自存储器胞元输出数据的数据输入/输出终端、以及电源供应终端。
在一些实施例中，半导体逻辑晶粒110A包括多个第一终端1105A于第一主动面111A上，半导体存储器晶粒110B包括多个第二终端1105B于第二主动面111B上，以及第一终端1105A经由电凸块结构117而电连接至第二终端，该电凸块结构117包含凸块1171与焊料1173，实质上没有接合线存在于半导体存储器晶粒110B与半导体逻辑晶粒110A之间。
在一些实施例中，半导体逻辑晶粒110A具有多个内部传导件119，自半导体逻辑晶粒110A的第一主动面111A延伸至第一背面113A。在一些实施例中，内部传导件119包括垂直穿过基板1101A的传导插塞1191(贯穿硅插塞)以及电互连1103A中的接线(wire)1193。
在一些实施例中，物件200为重布线层。在一些实施例中，重布线层包括介电堆迭205以及位于介电堆迭205中的一些传导线203。传导线203具有第一传导终端于上侧用于电连接至传导插塞1191，以及第二传导终端于底侧用于电连接至传导凸块201。传导线203亦用于形成所述传导插塞1191之间的电连接。在一些实施例中，传导线203由铜、金、银、镍、焊料、锡、铅、钨、铝、钛、钯、或其合金制成。
在一些实施例中，以面对面方式垂直堆迭具有不同功能的晶粒(例如半导体逻辑晶粒110A与半导体存储器晶粒110B)，在不同功能的晶粒之间实施面对面通信(face-to-face communication)。此外，相较于具有以横向相邻方式配置的不同功能晶粒(半导体存储器晶粒13A与半导体逻辑晶粒13B)的半导体装置10A，以面对面方式垂直堆迭不同功能的晶粒(半导体逻辑晶粒110A与半导体存储器晶粒110B)降低半导体装置100A的占据面积。再者，相较于具有以横向相邻方式配置的不同功能晶粒的信号路径，具有以面对面方式垂直堆迭的不同功能晶粒的信号路径较短；因此，本公开的以面对面方式垂直堆迭的不同功能晶粒可应用于高速电子装置。
图4为剖面示意图，例示本公开比较例的半导体装置10B。图4所示的半导体装置10B与图1所示的半导体装置10A实质相同，差别在于贯穿模塑插塞(through molding via)的设计。在图1中，半导体装置10A的模制件15没有贯穿模塑插塞，然而在图4中，一些传导插塞(贯穿模塑插塞)15A配置于图4的半导体装置10B的模制件115中。在一些实施例中，传导插塞115A贯穿模制件115，以形成垂直信号路径于底侧上的物件200与另一物件之间，该另一物件例如在传导插塞115A的上侧的电路基板。
图5为剖面示意图，例示本公开实施例的半导体装置100B。图5所示的半导体装置100B与图2所示的半导体装置100A实质相同，差别在于贯穿模塑插塞的设计。在图2中，半导体装置100A的模制件115没有贯穿模塑插塞，然而在图5中，一些传导插塞(贯穿模塑插塞)115A配置于半导体装置100B的模制件115中。在一些实施例中，所述传导插塞115A贯穿模制件115以形成垂直信号路径于底侧上的物件200与另一物件之间，该另一物件例如在传导插塞115A的上侧的电路基板。
在本公开中，亦公开一种半导体装置的制造方法。在一些实施例中，可通过图6所示的方法300形成半导体装置。方法300包含一些操作，并且描述与说明不被视为操作顺序的限制。方法300包含一些步骤(301、303、305、307、309与311)。
图7至图13为示意图，例示本公开实施例通过图6的方法制造半导体装置的制程。在步骤301中，形成传导插塞115A于载体基板400上方，如图7与图8所示。在一些实施例中，形成传导插塞115A包含形成遮罩层401，具有开口403于载体基板400上方，如图7所示，以传导材料填充开口403，而后自载体基板400移除遮罩层401以形成传导插塞115A于载体基板400上方，如图8所示。
在步骤303中，半导体存储器晶粒110B附接至载体基板400，如图9所示。在一些实施例中，半导体存储器晶粒110B包括基板1101B以及在基板1101B上的电互连1103B，其中电互连1103B的正面(半导体存储器晶粒110B的主动面111B)面朝上，以及基板1101B的背面(半导体存储器晶粒110B的背面113B)附接至载体基板400。
在步骤305中，具有凸块结构117的半导体逻辑晶粒110A以面对面方式堆迭至半导体存储器晶粒110B上，凸块结构117介于半导体逻辑晶粒110A与半导体存储器晶粒110B之间，如图10所示。在一些实施例中，半导体逻辑晶粒110A包括基板1101A以及在基板1101A上的电互连1103A，其中电互连1103A的正面(半导体逻辑晶粒110A的主动面111A)面朝下，因而半导体逻辑晶粒110A的主动面111A面对半导体存储器晶粒110B的主动面，亦即面对面堆迭。
在步骤307中，于载体基板400上方形成模制件115，如图11所示。在一些实施例中，在模制件115形成于载体基板400上方之前，于载体基板400上方形成或附接传导插塞115A、半导体逻辑晶粒110A与半导体存储器晶粒110B；因此，模制件115环绕传导插塞115A、半导体逻辑晶粒110A与半导体存储器晶粒110B。
在步骤309中，在半导体逻辑晶粒110A的背面113A上方形成物件200，例如重布线层，如图12所示。在一些实施例中，通过沉积、微影与蚀刻制程，形成该重布线层。此外，在该重布线层上方形成一些传导凸块201。在一些实施例中，在形成模制件115之后，形成该重布线层。
在步骤311中，移除载体基板400，并且进行单粒化制程，将半导体装置100B切割为分隔的(separated)半导体封装。在一些实施例中，以晶粒切割或单粒化工具405，进行单粒化制程，例如使用机械或激光锯，切割穿过个别芯片或晶粒之间的基板。在一些实施例中，激光锯使用氩(Ar)为基础的离子激光束工具。
本公开涉及一种半导体装置及其制造方法，该半导体装置具有以面对面方式堆迭的多个半导体晶粒。通过以面对面方式垂直堆迭的不同功能晶粒，在不同功能晶粒之间实施面对面通信。此外，相较于具有以横向相邻方式配置的不同功能晶粒的半导体装置，本公开的技术以面对面方式垂直堆迭不同功能的晶粒，因而降低半导体装置的面积。再者，相较于具有以横向相邻方式配置的不同功能晶粒的信号路径，本公开的技术以面对面方式垂直堆迭的不同功能晶粒的信号路径较短；因此，本公开的技术以面对面方式垂直堆迭的不同功能晶粒可应用于高速电子装置。
本公开的一实施例提供一种半导体装置，包含具有一第一主动面的一半导体逻辑晶粒以及自该半导体逻辑晶粒的该第一主动面延伸至一背面的一内部传导件；一半导体存储器晶粒堆迭至该半导体逻辑晶粒上，其中该半导体逻辑晶粒的该第一主动面面对该半导体存储器晶粒的一第二主动面；以及一凸块结构，电连接该第一主动面上的一第一终端至该第二主动面上的一第二终端。
本公开的另一实施例提供一种半导体装置的制造方法，包含：附接一半导体存储器晶粒至一载体基板；以一面对面方式堆迭一半导体逻辑晶粒至该半导体存储器晶粒上；形成一模制件于该载体基板上，其中该模制件环绕该半导体存储器晶粒与该半导体逻辑晶粒；以及移除该载体基板。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离权利要求所定义的本公开的构思与范围。例如，可用不同的方法实施上述的许多制程，并且以其他制程或其组合替代上述的许多制程。
再者，本申请的范围并不受限于说明书中所述的制程、机械、制造、物质组成物、手段、方法与步骤的特定实施例。本领域技术人员可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质相同结果的现存或是未来发展的制程、机械、制造、物质组成物、手段、方法、或步骤。据此，这些制程、机械、制造、物质组成物、手段、方法、或步骤是包含于本申请的权利要求内。

Claims (17)

1.一种半导体装置，包括：
一半导体逻辑晶粒，具有一第一主动面与一内部传导件，该内部传导件自该半导体逻辑晶粒的该第一主动面延伸至一背面；
一半导体存储器晶粒，堆迭至该半导体逻辑晶粒上，其中该半导体逻辑晶粒的该第一主动面面对该半导体存储器晶粒的一第二主动面；以及
一凸块结构，电连接该第一主动面上的一第一终端至该第二主动面上的一第二终端。
2.如权利要求1所述的半导体装置，另包括一模制件，囊封该半导体逻辑晶粒与该半导体存储器晶粒。
3.如权利要求1所述的半导体装置，另包括穿过该模制件的一传导插塞。
4.如权利要求3所述的半导体装置，其中该传导插塞垂直穿过该模制件。
5.如权利要求1所述的半导体装置，另包括一物件，其中该半导体逻辑晶粒的该背面附接至该物件。
6.如权利要求5所述的半导体装置，其中该物件包括一重布线层。
7.如权利要求1所述的半导体装置，其中该半导体逻辑晶粒包括一基板与一电互连，以及该内部传导件包括穿过该基板的一传导插塞。
8.如权利要求7所述的半导体装置，其中该传导插塞垂直穿过该基板。
9.如权利要求1所述的半导体装置，其中该半导体存储器晶粒电连接至该半导体逻辑晶粒，实质上没有一接合线存在于该半导体存储器晶粒与该半导体逻辑晶粒之间。
10.一种半导体装置的制造方法，包括：
附接一半导体存储器晶粒至一载体基板；
以一面对面方式堆迭一半导体逻辑晶粒至该半导体存储器晶粒上；
形成一模制件于该载体基板上，其中该模制件环绕该半导体存储器晶粒与该半导体逻辑晶粒；以及
移除该载体基板。
11.如权利要求10所述的制造方法，另包括：形成一物件于该半导体存储器晶粒的一背面上方，其中该物件实现该半导体装置的一横向信号路径。
12.如权利要求10所述的制造方法，其中形成该物件包括形成一重布线层。
13.如权利要求10所述的制造方法，另包括：形成多个传导凸块于该物件上方。
14.如权利要求10所述的制造方法，另包括：在形成该模制件于该载体基板上方之前，形成一传导插塞于该载体基板上方。
15.如权利要求10所述的制造方法，其中该半导体逻辑晶粒具有一第一主动面，该半导体存储器晶粒具有一第二主动面，以及该半导体逻辑晶粒附接至该半导体存储器晶粒时，该半导体逻辑晶粒的该第一主动面面对该半导体存储器晶粒的该第二主动面。
16.如权利要求15所述的制造方法，其中该半导体逻辑晶粒具有一内部传导件，自该半导体逻辑晶粒的该第一主动面延伸至一背面。
17.如权利要求10所述的制造方法，其中该半导体存储器晶粒电连接至该半导体逻辑晶粒，实质上没有一接合线存在于该半导体存储器晶粒与该半导体逻辑晶粒之间。
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Application publication date: 20180824