CN112151516A - 封装 - Google Patents

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Publication number
CN112151516A
CN112151516A CN202010273699.4A CN202010273699A CN112151516A CN 112151516 A CN112151516 A CN 112151516A CN 202010273699 A CN202010273699 A CN 202010273699A CN 112151516 A CN112151516 A CN 112151516A
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CN
China
Prior art keywords
chip
semiconductor wafer
package
integrated circuit
dielectric layer
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Pending
Application number
CN202010273699.4A
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English (en)
Inventor
陈明发
叶松峯
刘醇鸿
史朝文
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority claimed from US16/737,929 external-priority patent/US11562983B2/en
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN112151516A publication Critical patent/CN112151516A/zh
Pending legal-status Critical Current

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Abstract

一种封装包括集成电路。所述集成电路包括第一芯片、第二芯片、第三芯片及第四芯片。第二芯片及第三芯片并排设置在第一芯片上。第二芯片及第三芯片混合接合到第一芯片。第四芯片熔融接合到第二芯片及第三芯片中的至少一者。

Description

封装
技术领域
本发明实施例涉及一种封装。更具体来说，本发明实施例涉及一种具有熔融接合结构以及混合接合结构的封装。
背景技术
例如手机及其他移动电子装备等各种电子设备中所使用的半导体装置及集成电路通常被制造在单个半导体晶片(semiconductor wafer)上。可在晶片级(wafer level)上对晶片(wafer)的管芯进行处理并与其他半导体装置或管芯封装在一起，且已针对晶片级封装(wafer level packaging)开发出各种技术及应用。多个半导体装置的集成已成为所述领域的一个挑战。
发明内容
一种封装包括集成电路。所述集成电路包括第一芯片、第二芯片、第三芯片及第四芯片。第二芯片及第三芯片并排设置在第一芯片上。第二芯片及第三芯片混合接合到第一芯片。第四芯片熔融接合到第二芯片及第三芯片中的至少一者。
附图说明
结合附图阅读以下详细说明，能最好地理解本发明的各方面。注意，根据行业中的标准惯例，各种特征未按比例绘制。事实上，为论述的清晰起见，可任意地增大或减小各种特征的尺寸。
图1A至图1P是根据本公开一些实施例的封装的制造工艺的示意性剖视图。
图2A至图2L是根据本公开一些替代性实施例的封装的制造工艺的示意性剖视图。
图3A至图3Q是根据本公开一些替代性实施例的封装的制造工艺的示意性剖视图。
图4A至图4Q是根据本公开一些替代性实施例的封装的制造工艺的示意性剖视图。
图5A至图5B是根据本公开一些替代性实施例的封装的制造工艺的示意性剖视图。
附图标号说明
10、20、30、40、60：封装
100、200、300、400：芯片
102、102a、202、202a、302、302a、402：半导体衬底
104、204、304、312、404、700、700a、700b：内连线结构
106、206、306、314、406、DI：介电层
108、208、308、316、408：导体
210、310：半导体穿孔
500、500a：绝缘包封体
600：绝缘穿孔
800、800a、800b：钝化层
900、900a、900b：导通孔
900’：焊料
1000：导电结构
1100：包封体
1200：重布线结构
1202：层间介电层
1204：重布线导电图案
1300、1400、1500：导电端子
A100、A300、A400：有源表面
AD：粘合层
BF1、BF2、BF3、BF4、BF5：接合膜
C1、C2、C3、C4、C5、C6：载体
D1、D2、D3、D4、D5、D6：集成电路
DB：剥离层
G、G1：间隙
H100、H200、H300、H400：厚度
P1、P2、P3、P4、P5：封装结构
R100、R200、R300、R400：后表面
S200a、S300a、S300b：表面
SUB：电路衬底
UF：底部填充胶
W1、W2、W3：半导体晶片
具体实施方式
以下公开内容提供许多不同的实施例或实例以实施所提供主题的不同特征。下文阐述组件及排列的具体实例以使本发明简明。当然，这些仅是实例且不旨在进行限制。例如，在以下说明中，第一特征形成在第二特征之上或形成在第二特征上可包括第一特征与第二特征形成为直接接触的实施例，且还可包括附加特征可形成在第一特征与第二特征之间以使得第一特征与第二特征可不直接接触的实施例。另外，本发明可在各种实例中重复使用附图标号及/或字母。此种重复是出于简明及清晰目的，且自身并不规定所论述的各种实施例和/或配置之间的关系。
此外，为便于说明起见，本文中可使用例如“在…之下(beneath)”、“低于(below)”、“下部(lower)”、“在…上方(above)”、“上部(upper)”等空间相对性用语来阐述如图中所示的一个元件或特征与另一(其他)元件或特征的关系。除图中所绘示的取向以外，所述空间相对性用语还旨在囊括装置在使用或操作中的不同取向。可以其他方式对设备进行取向(旋转90度或处于其他取向)，且同样地可对本文中所使用的空间相对性描述语加以相应地解释。
本公开还可包括其他的特征及工艺。例如，可包括测试结构来辅助对三维(threedimensional，3D)封装或三维集成电路(three dimensional integrated circuit，3DIC)装置进行验证测试。所述测试结构可包括例如形成在重布线层(redistribution layer，RDL)中或形成在衬底上的测试垫，所述测试垫允许对3D封装或3DIC进行测试，允许使用探针及/或探针卡等。可对中间结构及最终结构执行验证测试。另外，本文中所公开的结构及方法可结合包括对已知良好管芯(known good die)进行中间验证的测试方法来使用，以提高良率并降低成本。
图1A至图1P是根据本公开一些实施例的封装10的制造工艺的示意性剖视图。参照图1A，提供半导体晶片(semicondcutor wafer)W1。半导体晶片W1包括半导体衬底102a、内连线结构104、介电层106及多个导体108。在一些实施例中，半导体衬底102a可为硅衬底。在一些实施例中，半导体衬底102a可包括形成在其中的有源组件(例如，晶体管等)及/或无源组件(例如，电阻器、电容器、电感器等)。如图1A中所示，内连线结构104设置在半导体衬底102a上，且介电层106覆盖内连线结构104。在一些实施例中，内连线结构104可包括嵌入在介电材料中的多个导电图案。在一些实施例中，导体108嵌入在介电层106中。例如，导体108被介电层106横向包封。导体108通过内连线结构104与半导体衬底102a电连接。例如，导体108可通过内连线结构104与半导体衬底102a中的有源组件及/或无源组件电连接。在一些实施例中，导体108的材料可为铜或其他合适的金属材料，而介电层106的材料可为氧化硅、氮化硅、氮氧化硅或其他合适的介电材料。
在一些实施例中，可通过在内连线结构104上沉积介电材料层且将介电材料层图案化以在介电材料层中形成多个开口来形成介电层106。形成在介电层106中的开口暴露出内连线结构104的导电图案的部分。在介电层106被图案化之后，可在介电层106以及内连线结构104中被介电层106的开口暴露的导电图案的部分上沉积导电材料层。接着，执行研磨工艺(例如，化学机械研磨工艺)以部分地移除导电材料层，直到暴露出介电层106的顶表面为止。在执行研磨工艺之后，在介电层106的开口中形成导体108。
如图1A中所示，在半导体晶片W1上形成接合膜BF1。例如，将接合膜BF1形成为覆盖介电层106及导体108。在一些实施例中，接合膜BF1可包括管芯贴合膜(die attach film，DAF)或具有粘合性质的其他材料。
参照图1B，将半导体晶片W1上下颠倒翻面且放置在载体C1上。在一些实施例中，载体C1可为例如硅载体等半导体载体。然而，本公开不限于此。在一些替代性实施例中，载体C1可为玻璃载体。在一些实施例中，通过接合膜BF1将半导体晶片W1贴合到载体C1。在将半导体晶片W1接合到载体C1之后，对半导体晶片W1进行薄化。例如，可移除半导体衬底102a的一部分以形成半导体衬底102，以便减小半导体晶片W1的总体厚度。
参照图1C，提供半导体晶片W2。在一些实施例中，半导体晶片W2可为不具有有源组件及无源组件的块状(bulk)半导体晶片。例如，半导体晶片W2可为其中未形成任何有源或无源组件的本征(intrinsic)硅晶片。然而，本公开不限于此。在一些替代性实施例中，半导体晶片W2可包括形成在其中的有源组件及/或无源组件。如图1C中所示，在半导体晶片W2上形成接合膜BF2。在一些实施例中，接合膜BF2可包括管芯贴合膜(DAF)或具有粘合性质的其他材料。在一些实施例中，接合膜BF2的厚度可介于约0.01μm(微米)到约2μm之间的范围内。在一些实施例中，可可选地在半导体晶片W2中形成多个半导体穿孔(throughsemiconductors via，TSV；未示出)。
参照图1D，将图1C中所示的半导体晶片W2及接合膜BF2上下颠倒翻面且贴合到图1B中所示的结构。即，将半导体晶片W2贴合到半导体晶片W1。在一些实施例中，通过接合膜BF2将半导体晶片W2粘合到半导体晶片W1的半导体衬底102。在一些实施例中，可通过熔融接合(fusion bonding)来实现半导体晶片W2与半导体晶片W1之间的接合。熔融接合工艺可包括亲水熔融接合工艺，其中可用的工作温度约大于或实质上等于约100摄氏度，且可用的工作压力约大于或实质上等于约1kg/cm2(千克/平方厘米)。在一些实施例中，熔融接合工艺不涉及金属对金属接合(metal to metal bonding)。在一些实施例中，接合膜BF2与半导体衬底102之间的熔融接合界面实质上为平的。例如，熔融接合界面的粗糙度(roughness)为
Figure BDA0002444029570000041
(埃)到
Figure BDA0002444029570000042
在一些实施例中，由于半导体晶片W2及半导体晶片W1均呈晶片形式，因此半导体晶片W2与半导体晶片W1的接合被称为“晶片到晶片接合(wafer-to-waferbonding)”。
参照图1D及图1E，从半导体晶片W1移除载体C1及接合膜BF1。此后，对半导体晶片W1、半导体晶片W2及接合膜BF2进行单体化以形成多个芯片100及多个芯片200。在一些实施例中，单体化工艺通常涉及利用旋转刀片或激光束进行切割。换句话说，单体化工艺是例如激光切削工艺、机械切削工艺或其他合适的工艺。在一些实施例中，每一芯片100可为动态随机存取存储器(Dynamic Random Access Memory，DRAM)、电阻式随机存取存储器(Resistive Random Access Memory，RRAM)、静态随机存取存储器(Static Random AccessMemory，SRAM)。DRAM的实例包括高带宽存储器(High Bandwidth Memory，HBM)、宽输入/输出(Wide I/O，WIO)存储器、低功率双倍数据速率(Low-Power Double Date Rate，LPDDR)DRAM等。在一些实施例中，每一芯片100包括半导体衬底102、内连线结构104、介电层106及导体108。在一些实施例中，导体108的顶表面及介电层106的顶表面可被统称为芯片100的有源表面A100。另一方面，芯片100的与有源表面A100相对的表面可被称为芯片100的后表面R100。如图1E中所示，导体108的顶表面与介电层106的顶表面实质上位于相同的水平高度处，以提供适宜用于混合接合(hybrid bonding)的有源表面A100。同时，芯片200通过接合膜BF2贴合到芯片100的后表面R100。换句话说，芯片100熔融接合到芯片200。在一些实施例中，芯片100的侧壁与芯片200的侧壁对齐。在一些实施例中，芯片200是不具有有源组件及无源组件的虚设芯片(dummy chip)。即，在随后形成的电子装置的操作期间，芯片200被去能/不起作用。然而，本公开不限于此。在一些替代性实施例中，芯片200可包括形成在其中的有源组件及/或无源组件。即，依据设计要求，芯片200可对随后形成的电子装置的操作具有贡献。在一些实施例中，芯片200可被称为“机电热(Mechanical-Electrical-Thermal，MET)芯片”。
参照图1F，提供半导体晶片W3。半导体晶片W3包括半导体衬底302a、内连线结构304、介电层306、多个导体308及多个半导体穿孔(TSV)310。在一些实施例中，半导体衬底302a、内连线结构304、介电层306及导体308分别相似于图1A中的半导体晶片W1的半导体衬底102a、内连线结构104、介电层106及导体108，因此本文中不再对其予以赘述。在一些实施例中，TSV 310嵌入在半导体衬底302a中且不被显露出。TSV 310与内连线结构304电连接。在一些实施例中，导体308的顶表面及介电层306的顶表面可被统称为半导体晶片W3的有源表面A300。另一方面，半导体晶片W3的与有源表面A300相对的表面可被称为半导体晶片W3的后表面R300。如图1F中所示，导体108的顶表面与介电层106的顶表面实质上位于相同的水平高度处，以提供适宜用于混合接合的有源表面A300。
在一些实施例中，将图1E中所示贴合有芯片200的芯片100拾取并放置到半导体晶片W3的有源表面A300上，使得芯片100与半导体晶片W3电连接。在一些实施例中，芯片100与半导体晶片W3混合接合。例如，将芯片100放置成使得芯片100的有源表面A100与半导体晶片W3的有源表面A300接触，且半导体晶片W3的导体308实质上与芯片100的导体108对齐且与芯片100的导体108直接接触。
在一些实施例中，为促进芯片100与半导体晶片W3之间的混合接合，可执行对芯片100及半导体晶片W3的接合表面(即，有源表面A100及有源表面A300)的表面准备。例如，表面准备可包括表面清洁及活化。可在有源表面A100、A300上执行表面清洁，以移除导体108、308及介电层106、306的顶表面上的颗粒。在一些实施例中，例如，可通过湿式清洁(wetcleaning)来清洁有源表面A100、A300。不仅颗粒被移除，而且形成在导体108、308的顶表面上的原生氧化物(native oxide)也可被移除。例如，可通过湿式清洗工艺中所使用的化学品来移除形成在导体108、308的顶表面上的原生氧化物。
在清洁芯片100的有源表面A100及半导体晶片W3的有源表面A300之后，可执行对介电层106、306的顶表面的活化，以产生高接合强度。在一些实施例中，可执行等离子体活化来处理介电层106、306的顶表面。当介电层106的经活化顶表面与介电层306的经活化顶表面接触时，芯片100的介电层106与半导体晶片W3的介电层306被预接合。
在将芯片100预接合到半导体晶片W3上之后，执行对芯片100与半导体晶片W3的混合接合。芯片100与半导体晶片W3的混合接合可包括用于介电质接合的热处理及用于导体接合的热退火(thermal annealing)。在一些实施例中，执行用于介电质接合的热处理以加强介电层106、306之间的接合。例如，用于介电质接合的热处理可在范围介于约100摄氏度至约150摄氏度的温度下执行。在执行用于介电质接合的热处理之后，执行用于导体接合的热退火以促进导体108、308之间的接合。例如，用于导体接合的热退火可在范围介于约300摄氏度至约400摄氏度的温度下执行。用于导体接合的热退火的工艺温度高于用于介电质接合的热处理的工艺温度。在执行用于导体接合的热退火之后，介电层106接合到介电层306，且导体108接合到导体308。在一些实施例中，芯片100的导体108及半导体晶片W3的导体308可分别为导通孔(例如，铜通孔)、导电垫(例如，铜垫)或其组合。例如，导体108、308之间的导体接合可为通孔到通孔接合(via-to-via bonding)、垫到垫接合(pad-to-padbonding)或通孔到垫接合(via-to-pad bonding)。在一些实施例中，导体108的侧壁与导体308的侧壁对齐。
如图1F中所示，除芯片100以外，也将芯片400拾取并放置在半导体晶片W3的有源表面A300上，使得芯片400与半导体晶片W3电连接。在一些实施例中，芯片400与芯片100并排设置在半导体晶片W3上，所述两者之间具有间隙G。在一些实施例中，从俯视图来看，芯片400的侧壁不与芯片100的侧壁及芯片200的侧壁对齐。在一些实施例中，芯片400包括半导体衬底402、内连线结构404、介电层406及多个导体408。半导体衬底402、内连线结构404、介电层406及导体408分别相似于芯片100的半导体衬底102、内连线结构104、介电层106及导体108，因此本文中不再对其予以赘述。在一些实施例中，芯片400能够执行逻辑功能。例如，芯片400可为中央处理器(Central Process Unit，CPU)芯片、图形处理单元(GraphicProcess Unit，GPU)芯片、现场可编程门阵列(Field-Programmable Gate Array，FPGA)等。在一些实施例中，导体408的顶表面及介电层406的顶表面可被统称为芯片400的有源表面A400。另一方面，芯片400的与有源表面A400相对的表面可被称为芯片400的后表面R400。如图1F中所示，导体408的顶表面与介电层406的顶表面实质上位于相同的水平高度处，以提供适宜用于混合接合的有源表面A400。在一些实施例中，芯片400混合接合到半导体晶片W3。例如，芯片400可通过与芯片100及半导体晶片W3的接合方式相似的方式接合到半导体晶片W3，因此本文中不再对其予以赘述。如图1F中所示，介电层406混合接合到介电层306，且导体408混合接合到导体308。在一些实施例中，导体308的侧壁与导体408的侧壁对齐。
参照图1F及图1G，形成绝缘包封体500以填充间隙G。例如，形成绝缘包封体500以横向包封芯片100、200及400。在一些实施例中，绝缘包封体500包括模制化合物、模制底部填充胶、树脂(例如环氧树脂)等。在一些替代性实施例中，绝缘包封体500可包括氧化硅及/或氮化硅。在一些实施例中，可通过化学气相沉积(chemical vapor deposition，CVD)、等离子体增强型化学气相沉积(plasma-enhanced chemical vapor deposition，PECVD)、原子层沉积(atomic layer deposition，ALD)等形成绝缘包封体500。在一些实施例中，绝缘包封体500可不具有填料(filler)。在一些实施例中，绝缘包封体500可被称为“间隙填充氧化物(gap fill oxide)”。在一些实施例中，可在芯片200的后表面R200、芯片400的后表面R400及绝缘包封体500上执行平坦化工艺(planarization process)，以进一步减小随后形成的封装的总体厚度。在一些实施例中，平坦化工艺包括机械研磨工艺及/或化学机械研磨(chemical mechanical polishing，CMP)工艺。
在一些实施例中，可可选地在绝缘包封体500中形成一个或多个绝缘穿孔(through insulating via，TIV)600。在一些实施例中，TIV 600穿透绝缘包封体500且与半导体晶片W3电连接。例如，TIV 600与导体308直接接触，使得半导体衬底302a中的有源组件及/或无源组件可依序通过内连线结构304及导体308电连接到TIV 600。在一些实施例中，TIV 600可由导电材料制成。举例来说，TIV 600的材料可包括例如铜、铜合金等金属材料。在一些实施例中，可在绝缘包封体500形成之前形成TIV 600。然而，本公开不限于此。在一些替代性实施例中，可在绝缘包封体500形成之后形成TIV 600。例如，可通过在绝缘包封体500中形成多个开口且将导电材料填充到绝缘包封体500的开口中来形成TIV 600。
在一些实施例中，芯片400的厚度H400实质上等于芯片100的厚度H100与芯片200的厚度H200的和。应注意的是，与芯片100、200相比，芯片100与芯片200之间的接合膜BF2相对薄，因此接合膜BF2的厚度可忽略不计。在一些实施例中，芯片400的厚度H400为约10μm到约120μm。换句话说，芯片100、200的厚度H100、H200的和的范围也介于约10μm到约120μm之间。在一些实施例中，即使当芯片400需要某一厚度时，仍可通过采用芯片200来灵活调整芯片100的厚度H100。即，芯片100的厚度H100的不足可通过芯片200的厚度H200来补偿。
参照图1G及图1H，将图1G中所示的结构上下颠倒翻面且贴合到载体C2。图1H中的载体C2可相似于图1B中的载体C1，因此本文中不再对其予以赘述。此后，在半导体晶片W3的后表面R300上执行平坦化工艺。在一些实施例中，平坦化工艺包括机械研磨工艺及/或CMP工艺。在一些实施例中，对半导体晶片W3的半导体衬底302a进行研磨，直到显露出TSV 310为止，以便形成半导体衬底302。例如，在平坦化工艺之后，TSV 310穿透半导体衬底302。TSV310使得能够在半导体晶片W3的前侧与背侧之间实现电通信。在一些实施例中，在显露出TSV 310之后，可进一步研磨半导体晶片W3，以减小半导体晶片W3的总体厚度。
参照图1I，在半导体晶片W3的后表面R300上形成内连线结构700、钝化层800及多个导通孔900。内连线结构700包括嵌入在介电材料中的多个导电图案。在一些实施例中，内连线结构700与半导体晶片W3的TSV 310电连接。例如，内连线结构700的导电图案可与半导体晶片W3的TSV 310直接接触。
钝化层800及导通孔900形成在内连线结构700上。在一些实施例中，导通孔900形成在内连线结构700的导电图案上且与内连线结构700的导电图案直接接触。即，导通孔900依序通过内连线结构700、TSV 310、内连线结构304及导体308与芯片100及400电连接。在一些实施例中，导通孔900由导电材料制成，且镀覆在内连线结构700的导电图案上。举例来说，导通孔900的材料可包括铜、铜合金等。在一些实施例中，钝化层800被形成为覆盖导通孔900。在一些实施例中，钝化层800的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(benzocyclobutene，BCB)、聚苯并恶唑(polybenzoxazole，PBO)或任何其他合适的聚合物系介电材料。举例来说，钝化层800可通过例如旋转涂布、CVD、PECVD等合适的制作技术来形成。如图1I中所示，导通孔900被钝化层800很好地保护。然而，本公开不限于此。在一些替代性实施例中，钝化层800可暴露出导通孔900。
参照图1I及图1J，移除载体C2，且在图1I中所示的结构上执行单体化工艺，以获得多个集成电路D1。在一些实施例中，单体化工艺通常涉及利用旋转刀片或激光束进行切割。换句话说，单体化工艺是例如激光切削工艺、机械切削工艺或其他合适的工艺。在一些实施例中，单体化工艺将半导体晶片W3分割成多个芯片300。即，每一芯片300包括半导体衬底302、内连线结构304、介电层306、导体308及TSV 310。在一些实施例中，芯片300能够执行逻辑功能。例如，芯片300可为中央处理器(CPU)芯片、图形处理单元(GPU)芯片、现场可编程门阵列(FPGA)等。在一些实施例中，芯片300的厚度H300的范围介于约10μm到约50μm之间。
在一些实施例中，由于多个芯片(芯片100、200、300及400)被集成到单个集成电路D1中，因此集成电路D1可被称为“集成芯片上***(system on integrated chips，SOIC)”。如图1J中所示，芯片100与芯片400并排设置在芯片300上。芯片100与芯片400混合接合到芯片300。另一方面，芯片100通过接合膜BF2熔融接合到芯片200。在一些实施例中，芯片200可由与芯片100、300及400相同的材料制成。因此，可减少集成电路D1或随后形成的封装的不同组件之间的热膨胀系数(Coefficient of Thermal Expansion，CTE)的失配(mismatch)。因此，由集成电路D1或随后形成的封装的制造工艺产生的翘曲(warpage)可被最小化，从而提高良率。此外，在一些实施例中，芯片200还可用作散热机构，以在随后形成的封装的操作期间增加散热速率。在一些实施例中，集成电路D1进一步包括绝缘包封体500、TIV 600、内连线结构700、钝化层800及导通孔900。绝缘包封体500横向包封芯片100、200及400。TIV600穿透包封体500且与芯片300电连接。内连线结构700、钝化层800及导通孔900与芯片100、200及400相对地设置在芯片300上。在一些实施例中，集成电路D1可用于各种应用。例如，集成电路D1可用作集成扇出(integrated fan-out，InFO)封装中的管芯。以下将阐述InFO封装的制造工艺。
参照图1K，提供上面堆叠有剥离层DB及介电层DI的载体C3。在一些实施例中，剥离层DB形成在载体C3的上表面上，且剥离层DB位于载体C3与介电层DI之间。例如，载体C3可为玻璃衬底，且剥离层DB可为形成在玻璃衬底上的光热转换(light-to-heat conversion，LTHC)释放层。然而，本公开不限于此，且其他合适的材料可适用于载体C3及剥离层DB。在一些实施例中，介电层DI的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、BCB、PBO或任何其他合适的聚合物系介电材料。介电层DI可通过例如旋转涂布、CVD、PECVD等合适的制作技术来形成。在一些实施例中，介电层DI可具有粘合性质以粘合随后形成的元件。
如图1K中所示，在介电层DI上形成多个导电结构1000。在一些实施例中，形成导电结构1000的方法包括以下步骤。首先，在介电层DI上形成晶种材料层(未示出)。在一些实施例中，晶种材料层包括通过溅镀工艺(sputtering process)形成的钛/铜复合层。随后，在晶种材料层上形成具有开口的光刻胶层(未示出)。光刻胶层的开口暴露出随后形成的导电结构1000的预期位置。此后，执行镀覆工艺以在被光刻胶层的开口暴露出的晶种材料层上形成金属材料层(例如，铜层)。接着移除光刻胶层及下伏的晶种材料层，以形成导电结构1000。然而，本公开不限于此。在一些替代性实施例中，可通过将预制的导电结构拾取并放置到介电层DI上来形成导电结构1000。
参照图1L，将图1J中所示的集成电路D1拾取并放置到介电层DI上。集成电路D1被放置成使得导电结构1000环绕集成电路D1。如图1L中所示，通过粘合层AD将集成电路D1贴合(或粘合)到介电层DI。粘合层AD可为管芯贴合膜等。尽管在图1L中示出一个集成电路D1，然而本公开不限于此。在一些替代性实施例中，可将多于一个集成电路D1拾取并放置到介电层DI上。
参照图1M，在介电层DI上形成包封体1100，以横向包封集成电路D1及导电结构1000。例如，包封体1100与芯片300的侧壁直接接触，以横向包封芯片300。在一些实施例中，包封体1100可通过以下步骤形成。首先，在介电层DI上形成包封材料(未示出)，以覆盖集成电路D1及导电结构1000。包封材料是模制化合物、模制底部填充胶、树脂(例如环氧树脂)等。在一些实施例中，包封材料可进一步包括填料。包封材料可通过例如压缩模制工艺(compression molding process)等模制工艺形成。在形成包封材料之后，对包封材料及集成电路D1的钝化层800进行研磨，直到暴露出导电结构1000的顶表面及导通孔900的顶表面为止。在一些实施例中，通过机械研磨工艺及/或CMP工艺来研磨包封材料。在一些实施例中，在包封材料及钝化层800的研磨工艺期间，导通孔900的部分及导电结构1000的部分也被轻微研磨。如图1M中所示，导电结构1000的顶表面、钝化层800的顶表面及导通孔900的顶表面与包封体1100的顶表面实质上共面。在一些实施例中，钝化层800的顶表面及导通孔900的顶表面可被称为集成电路D1的有源表面。
参照图1N，在集成电路D1、导电结构1000及包封体1100上形成重布线结构1200及多个导电端子1300。在一些实施例中，重布线结构1200与集成电路D1的导通孔900以及导电结构1000电连接。重布线结构1200包括交替堆叠的多个层间介电层1202及多个重布线导电图案1204。重布线导电图案1204与集成电路D1的导通孔900以及嵌入在包封体1100中的导电结构1000电连接。在一些实施例中，最底部的层间介电层1202具有暴露出导通孔900的顶表面及导电结构1000的顶表面的多个接触开口。最底部的重布线导电图案1204延伸到最底部的层间介电层1202的接触开口中，以与导通孔900的顶表面及导电结构1000的顶表面物理接触(physical contact)。
如图1N中所示，最顶部的重布线导电图案1204包括多个接垫。在一些实施例中，前述接垫可包括用于球安装的多个球下金属(under-ball metallurgy，UBM)图案。在一些实施例中，重布线导电图案1204的材料包括铝、钛、铜、镍、钨及/或其合金。重布线导电图案1204可通过例如电镀、沉积及/或光刻(photolithography)及刻蚀(etching)来形成。在一些实施例中，层间介电层1202的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、BCB、PBO或其他合适的聚合物系介电材料。层间介电层1202可通过例如旋转涂布、CVD、PECVD等合适的制作技术来形成。
在一些实施例中，导电端子1300放置在重布线结构1200中最顶部的重布线导电图案1204(UBM图案)上。在一些实施例中，导电端子1300包括焊球。在一些实施例中，导电端子1300可通过植球工艺(ball placement process)或其他合适的工艺放置在UBM图案上。
参照图1N及图1O，从剥离层DB剥离形成在包封体1100的底表面上的介电层DI，使得介电层DI与载体C3分离。在一些实施例中，可通过紫外激光辐照剥离层DB(例如，LTHC释放层)，使得剥离层DB及载体C3可从介电层DI剥落。随后，将所述结构上下颠倒翻面且将介电层DI图案化以形成多个开口。在一些实施例中，开口暴露出导电结构1000。此后，在开口中形成多个导电端子1400，以提供与导电结构1000的电连接。随后，执行单体化工艺以得到多个封装结构P1。在一些实施例中，单体化工艺通常涉及利用旋转刀片或激光束进行切割。换句话说，单体化工艺例如是激光切削工艺、机械切削工艺或其他合适的工艺。如上所述，封装结构P1可被称为“InFO封装”。在一些实施例中，通过在集成电路D1中引入芯片200且通过在封装结构P1中利用集成电路D1，可有效地减少封装结构P1中的翘曲及重布线层(redistribution layer，RDL)应力。同时，可充分增强封装结构P1的电性能(electricalperformance)及散热。
在一些实施例中，封装结构P1可进一步与其他封装结构进行组装以形成封装。例如，参照图1P，将封装结构P2堆叠在封装结构P1上以形成封装10。在一些实施例中，封装结构P2通过导电端子1400与封装结构P1电连接。在一些实施例中，封装10可进一步包括位于封装结构P1与封装结构P2之间的底部填充胶UF。在一些实施例中，底部填充胶UF能够保护对封装结构P1与P2进行电连接的导电端子1400。在一些实施例中，封装10可被称为“叠层封装(package-on-package，PoP)”。
图2A至图2L是根据本公开一些替代性实施例的封装20的制造工艺的示意性剖视图。参照图2A，提供半导体晶片W3。图2A中的半导体晶片W3相似于图1F中的半导体晶片W3，因此其相似的组件由相同的附图标号表示，且本文中不再对其予以赘述。在一些实施例中，半导体晶片W3具有有源表面A300及与有源表面A300相对的后表面R300。
如图2A中所示，将芯片100及芯片400拾取并放置在半导体晶片W3上。图2A中的芯片100及芯片400分别相似于图1F中的芯片100及芯片400，因此其相似的组件由相同的附图标号表示，且本文中不再对其予以赘述。在一些实施例中，芯片100与芯片400被放置成在所述两者之间具有间隙G。在一些实施例中，从俯视图来看，芯片400的侧壁不与芯片100的侧壁对齐。在一些实施例中，芯片100具有有源表面A100及与有源表面A100相对的后表面R100。相似地，芯片400具有有源表面A400及与有源表面A400相对的后表面R400。如图2A中所示，芯片100及芯片400以面朝下的方式设置在半导体晶片W3上。在一些实施例中，芯片100及芯片400混合接合到半导体晶片W3。例如，芯片100及芯片400被放置成使得芯片100的有源表面A100及芯片400的有源表面A400与半导体晶片W3的有源表面A300直接接触。图2A中的混合接合工艺可相似于图1F中所示的混合接合工艺，因此本文中不再对其予以赘述。在一些实施例中，芯片100的介电层106及芯片400的介电层406与半导体晶片W3的介电层306直接接触。同时，芯片100的导体108及芯片400的导体408与半导体晶片W3的导体308实质上对齐且与半导体晶片W3的导体308直接接触。
如图2A中所示，在芯片100的后表面R100上形成接合膜BF3，且在芯片400的后表面R400上形成接合膜BF4。接合膜BF3及接合膜BF4相似于图1C中的接合膜BF2，因此本文中不再对其予以赘述。
参照图2B，形成绝缘包封体500以填充芯片100与芯片400之间的间隙G。在一些实施例中，可选地形成TIV 600以穿透绝缘包封体500。图2B中的绝缘包封体500及TIV 600分别相似于图1G中的绝缘包封体500及TIV 600，因此本文中不再对其予以赘述。在一些实施例中，绝缘包封体500横向包封芯片100、400及接合膜BF3、BF4。
参照图2C，在芯片100、芯片400及绝缘包封体500上形成半导体晶片W2。在一些实施例中，图2C中的半导体晶片W2相似于图1C中的半导体晶片W2，因此本文中不再对其予以赘述。在一些实施例中，半导体晶片W2可可选地包括嵌入其中的多个TSV(未示出)。在一些实施例中，半导体晶片W2接合到芯片100与芯片400两者。例如，半导体晶片W2通过接合膜BF3接合到芯片100，且通过接合膜BF4接合到芯片400。在一些实施例中，半导体晶片W2与芯片100、400之间的接合可通过熔融接合来实现，且为同时进行的。图2C中的熔融接合工艺可相似于图1D中所示的熔融接合工艺，因此本文中不再对其予以赘述。在一些实施例中，在将半导体晶片W2接合到芯片100及芯片400之后，可对半导体晶片W2进行薄化。
参照图2D，将图2C中所示的结构上下颠倒翻面且贴合到载体C2。图2D中的载体C2相似于图1H中的载体C2，因此本文中不再对其予以赘述。此后，在半导体晶片W3的后表面R300上执行平坦化工艺。在一些实施例中，平坦化工艺包括机械研磨工艺及/或CMP工艺。在一些实施例中，对半导体晶片W3的半导体衬底302a进行研磨，直到显露出TSV 310为止，以便形成半导体衬底302。例如，在平坦化工艺之后，TSV 310穿透半导体衬底302。TSV 310使得能够在半导体晶片W3的前侧与背侧之间实现电通信。在一些实施例中，在显露出TSV 310之后，可进一步研磨半导体晶片W3，以减小半导体晶片W3的总体厚度。
参照图2E，在半导体晶片W3的后表面R300上形成内连线结构700、钝化层800及多个导通孔900。图2E中的内连线结构700、钝化层800及导通孔900分别相似于图1I中的内连线结构700、钝化层800及导通孔900，因此本文中不再对其予以赘述。
参照图2E及图2F，移除载体C2，且在图2E中所示的结构上执行单体化工艺，以获得多个集成电路D2。图2F中的单体化工艺相似于图1J中的单体化工艺，因此本文中不再对其予以赘述。在一些实施例中，单体化工艺将半导体晶片W2分割成多个芯片200，且将半导体晶片W3分割成多个芯片300。图2F中的芯片200及芯片300分别相似于图1J中的芯片200及芯片300，因此其相似的组件由相同的附图标号表示，且本文中不再对其予以赘述。在一些实施例中，芯片200堆叠在芯片100及芯片400两者上且熔融接合到芯片100与芯片400两者。如图2F中所示，芯片100的厚度H100实质上等于芯片400的厚度H400。例如，芯片100的厚度H100及芯片400的厚度H400的范围可介于约20μm到约60μm。另一方面，芯片200的厚度H200的范围介于约50μm到约90μm之间，而芯片300的厚度H300的范围介于约10μm到约60μm之间。由于芯片200具有实质上均匀的厚度H200且芯片100、400的厚度H100，H400实质上相等，芯片100的厚度H100与芯片200的厚度H200的和实质上等于芯片400的厚度H400与芯片200的厚度H200的和。
在一些实施例中，由于多个芯片(芯片100、200、300及400)被集成到单个集成电路D2中，因此集成电路D2可被称为“SOIC”。如图2F中所示，芯片100与芯片400并排设置在芯片300上。同时，芯片100与芯片400也并排设置在芯片200上。例如，芯片100及芯片400夹置在芯片200与芯片300之间。芯片100及芯片400混合接合到芯片300。另一方面，芯片100及芯片400熔融接合到芯片200。在一些实施例中，芯片200可由与芯片100、300及400相同的材料制成。因此，可减少集成电路D2或随后形成的封装的不同组件之间的CTE的失配。因此，由集成电路D2或随后形成的封装的制造工艺产生的翘曲可被最小化，从而提高良率。此外，在一些实施例中，芯片200还可用作散热机构，以在随后形成的封装的操作期间增加散热速率。在一些实施例中，集成电路D2进一步包括绝缘包封体500、TIV 600、内连线结构700、钝化层800及导通孔900。绝缘包封体500横向包封芯片100及400。TIV 600穿透包封体500且与芯片300电连接。内连线结构700、钝化层800及导通孔900与芯片100及400相对地设置在芯片300上。在一些实施例中，集成电路D2可用于各种应用。例如，集成电路D2可用作InFO封装中的管芯。以下将阐述InFO封装的制造工艺。
参照图2G至图2K，除图1K至图1O中的集成电路D1被图2F中的集成电路D2所取代以外，图2G至图2K中的步骤相似于图1K至图1O中所示的步骤，因此本文中不再对其予以赘述。参照图2K，获得多个封装结构P3。如上所述，封装结构P3可被称为“InFO封装”。如图2K中所示，包封体1100与芯片200及芯片300的侧壁直接接触，以横向包封芯片200及芯片300。在一些实施例中，通过在集成电路D2中引入芯片200且通过在封装结构P3中利用集成电路D2，可有效地减少封装结构P3中的翘曲及RDL应力。同时，可充分增强封装结构P3的电性能及散热。
在一些实施例中，封装结构P3可进一步与其他封装结构进行组装以形成封装。例如，参照图2L，将封装结构P2堆叠在封装结构P3上以形成封装20。在一些实施例中，封装结构P3通过导电端子1400与封装结构P2电连接。在一些实施例中，封装20可进一步包括位于封装结构P3与封装结构P2之间的底部填充胶UF。在一些实施例中，底部填充胶UF能够保护对封装结构P3与P2进行电连接的导电端子1400。在一些实施例中，封装20可被称为“PoP”。
图3A至图3Q是根据本公开一些替代性实施例的封装30的制造工艺的示意性剖视图。参照图3A，提供半导体衬底302a。在一些实施例中，半导体衬底302a具有嵌入其中的多个TSV 310。图3A中的半导体衬底302a及TSV 310分别相似于图1F中的半导体衬底302a及TSV 310，因此本文中不再对其予以赘述。如图3A中所示，在半导体衬底302a上形成接合膜BF5。例如，形成接合膜BF5以覆盖半导体衬底302a及TSV 310。在一些实施例中，接合膜BF5相似于图1A中的接合膜BF1，因此本文中不再对其予以赘述。
参照图3B，将图3A中所示的结构上下颠倒翻面且贴合到载体C4。例如，通过接合膜BF5将半导体衬底302a接合到载体C4。在一些实施例中，载体C4相似于图1B中的载体C1，因此本文中不再对其予以赘述。在将半导体衬底302a接合到载体C4之后，在半导体衬底302a上执行平坦化工艺。在一些实施例中，平坦化工艺包括机械研磨工艺及/或CMP工艺。在一些实施例中，对半导体衬底302a进行研磨，直到显露出TSV 310为止，以便形成半导体衬底302。例如，在平坦化工艺之后，TSV 310穿透半导体衬底302。在一些实施例中，在显露出TSV310之后，可进一步研磨半导体衬底302。
参照图3C，在半导体衬底302上形成内连线结构304、介电层306及多个导体308。在一些实施例中，图3C中的内连线结构304、介电层306及导体308分别相似于图1F中的内连线结构304、介电层306及导体308，因此本文中不再对其予以赘述。如图3C中所示，导体308被形成为通过内连线结构304的导电图案与TSV 310电连接。在一些实施例中，半导体衬底302、内连线结构304、介电层306、导体308及TSV 310可被统称为半导体晶片W3。
参照图3D，提供半导体晶片W2，且将半导体晶片W2混合接合到半导体晶片W3。半导体晶片W2包括半导体衬底202a、内连线结构204、介电层206、多个导体208及多个TSV 210。在一些实施例中，半导体衬底202a可为不具有有源组件及无源组件的块状半导体衬底。例如，半导体衬底202a可为其中未形成任何有源或无源组件的本征硅衬底。然而，本公开不限于此。在一些替代性实施例中，半导体衬底202a可包括形成在其中的有源组件及/或无源组件。另一方面，图3D中的内连线结构204、介电层206、导体208及TSV 210分别相似于图1F中的内连线结构304、介电层306、导体308及TSV 310，因此本文中不再对其予以赘述。如图3D中所示，内连线结构204设置在半导体衬底202a上，且介电层206覆盖内连线结构204。在一些实施例中，导体208嵌入在介电层206中。在一些实施例中，TSV 210嵌入在半导体衬底202a中。
如图3D中所示，半导体晶片W3具有由导体308的顶表面及介电层306的顶表面形成的表面S300a。导体308的顶表面与介电层306的顶表面实质上位于相同的水平高度处，以提供适宜用于混合接合的表面S300a。另一方面，半导体晶片W2具有由导体208的底表面及介电层206的底表面形成的表面S200a。导体208的底表面与介电层206的底表面实质上位于相同的水平高度处，以提供适宜用于混合接合的表面S200a。在一些实施例中，半导体晶片W2的表面S200a与半导体晶片W3的表面S300a直接接触。图3D中的混合接合工艺可相似于图1F中所示的混合接合工艺，因此本文中不再对其予以赘述。在一些实施例中，半导体晶片W2的介电层206与半导体晶片W3的介电层306直接接触。同时，半导体晶片W2的导体208与半导体晶片W3的导体308实质上对齐且与半导体晶片W3的导体308直接接触。在一些实施例中，由于半导体晶片W2及半导体晶片W3均呈晶片形式，因此半导体晶片W2与半导体晶片W3的接合被称为“晶片到晶片接合”。
参照图3E，在半导体晶片W2上执行平坦化工艺。在一些实施例中，平坦化工艺包括机械研磨工艺及/或CMP工艺。在一些实施例中，研磨半导体晶片W2的半导体衬底202a，直到显露出TSV 210为止，以便形成半导体衬底202。例如，在平坦化工艺之后，TSV 210穿透半导体衬底202。TSV 210使得能够在半导体晶片W2的前侧与背侧之间实现电通信。在一些实施例中，在显露出TSV 210之后，可进一步研磨半导体晶片W2，以减小半导体晶片W2的总体厚度。
参照图3E及图3F，移除载体C4及接合膜BF5以暴露出半导体晶片W3的TSV 310。随后，将图3E中所示的结构上下颠倒翻面且贴合到载体C5。载体C5可相似于图1H中的载体C2，因此本文中不再对其予以赘述。此后，在半导体衬底302及暴露出的TSV 310上形成内连线结构312、介电层314及多个导体316。在一些实施例中，内连线结构312、介电层314及导体316分别相似于内连线结构304、介电层306及导体308，因此本文中不再对其予以赘述。如图3F中所示，内连线结构312设置在半导体衬底302及TSV 310上。另一方面，介电层314覆盖内连线结构312。在一些实施例中，导体316嵌入在介电层314中。在一些实施例中，内连线结构312、介电层314及导体316也被视为半导体晶片W3的一部分。
如图3F中所示，半导体晶片W3具有由导体316的顶表面及介电层314的顶表面形成的表面S300b。即，表面S300b与表面S300a相对。导体316的顶表面与介电层314的顶表面实质上位于相同的水平高度处，以提供适宜用于混合接合的表面S300b。
参照图3G，将芯片100及芯片400拾取并放置在半导体晶片W3上。图3G中的芯片100及芯片400分别相似于图1F中的芯片100及芯片400，因此其相似的组件由相同的附图标号表示，且本文中不再对其予以赘述。在一些实施例中，芯片100及芯片400被放置成在所述两者之间具有间隙G。在一些实施例中，从俯视图来看，芯片400的侧壁不与芯片100的侧壁对齐。在一些实施例中，芯片100具有有源表面A100及与有源表面A100相对的后表面R100。相似地，芯片400具有有源表面A400及与有源表面A400相对的后表面R400。如图3G中所示，芯片100及芯片400以面朝下的方式设置在半导体晶片W3上。在一些实施例中，芯片100及芯片400混合接合到半导体晶片W3。例如，芯片100及芯片400被放置成使得芯片100的有源表面A100及芯片400的有源表面A400与半导体晶片W3的表面S300b直接接触。图3G中的混合接合工艺可相似于图1F中所示的混合接合工艺，因此本文中不再对其予以赘述。在一些实施例中，芯片100的介电层106及芯片400的介电层406与半导体晶片W3的介电层314直接接触。同时，芯片100的导体108及芯片400的导体408与半导体晶片W3的导体316实质上对齐且与半导体晶片W3的导体316直接接触。
参照图3H，形成绝缘包封体500以填充芯片100与芯片400之间的间隙G。绝缘包封体500相似于图1G中的绝缘包封体500，因此本文中不再对其予以赘述。在一些实施例中，绝缘包封体500横向包封芯片100及芯片400。
参照图3H及图3I，移除载体C5以暴露出半导体晶片W2的TSV 210。随后，将图3H中所示的结构上下颠倒翻面且贴合到载体C2。图3I中的载体C2相似于图1H中的载体C2，因此本文中不再对其予以赘述。如图3I中所示，芯片100、芯片400及绝缘包封体500贴合到载体C2。
参照图3J，在半导体晶片W2的半导体衬底202及TSV 210上形成内连线结构700、钝化层800及多个导通孔900。图3J中的内连线结构700、钝化层800及导通孔900分别相似于图1I中的内连线结构700、钝化层800及导通孔900，因此本文中不再对其予以赘述。在一些实施例中，内连线结构700与半导体晶片W2的TSV 210电连接。例如，内连线结构700的导电图案可与半导体晶片W2的TSV 210直接接触。在一些实施例中，导通孔900形成在内连线结构700的导电图案上且与内连线结构700的导电图案直接接触。即，导通孔900依序通过内连线结构700、TSV 210、内连线结构204、导体208、导体308、内连线结构304、TSV 310、内连线结构312及导体316与芯片100及400电连接。
参照图3J及图3K，移除载体C2，且在图3J中所示的结构上执行单体化工艺，以获得多个集成电路D3。图3K中的单体化工艺相似于图1J中的单体化工艺，因此本文中不再对其予以赘述。在一些实施例中，单体化工艺将半导体晶片W2分割成多个芯片200，且将半导体晶片W3分割成多个芯片300。在一些实施例中，每一芯片200包括半导体衬底202、内连线结构204、介电层206、导体208及TSV 210。在一些实施例中，芯片200是不具有有源组件及无源组件的虚设芯片。即，在随后形成的电子装置的操作期间，芯片200被去能/不起作用。然而，本公开不限于此。在一些替代性实施例中，芯片200可包括形成在其中的有源组件和/或无源组件。即，依据设计要求，芯片200可对随后形成的电子装置的操作具有贡献。在一些实施例中，芯片200可被称为“机电热(MET)芯片”。在一些实施例中，每一芯片300包括半导体衬底302、内连线结构304、312、介电层306、314、导体308、316及TSV 310。在一些实施例中，芯片300能够执行逻辑功能。例如，芯片300可为中央处理器(CPU)芯片、图形处理单元(GPU)芯片、现场可编程门阵列(FPGA)等。
如图3K中所示，芯片100的厚度H100实质上等于芯片400的厚度H400。例如，芯片100的厚度H100及芯片400的厚度H400的范围可介于约10μm到约60μm。另一方面，芯片300的厚度H300的范围介于约20μm到约60μm之间，而芯片200的厚度H200的范围介于约10μm到约50μm之间。
在一些实施例中，由于多个芯片(芯片100、200、300及400)被集成到单个集成电路D3中，因此集成电路D3可被称为“SOIC”。如图3K中所示，芯片300堆叠在芯片100与芯片400两者上且混合接合到芯片100与芯片400两者。即，芯片100与芯片400并排设置在芯片300的表面S300b上。另一方面，芯片200堆叠在芯片300的与表面S300b相对的表面S300a上。例如，芯片300夹置在芯片100与芯片200之间，且夹置在芯片400与芯片200之间。在一些实施例中，芯片200混合接合到芯片300。在一些实施例中，芯片200的侧壁与芯片300的侧壁对齐。在一些实施例中，芯片300与芯片100及芯片400两者电连接。另一方面，芯片200与芯片300电连接。例如，芯片200的TSV 210与芯片300的TSV 310电连接。如图3K中所示，TSV 210与TSV 310对齐。然而，本公开不限于此。在一些替代性实施例中，TSV 210及TSV 310可具有偏移(offset)。在一些实施例中，芯片200可由与芯片100、300及400相同的材料制成。因此，可减少集成电路D3或随后形成的封装的不同组件之间的CTE失配。因此，由集成电路D3或随后形成的封装的制造工艺产生的翘曲可被最小化，从而提高良率。此外，在一些实施例中，芯片200还可用作散热机构，以在随后形成的封装的操作期间增加散热速率。在一些实施例中，集成电路D3进一步包括绝缘包封体500、内连线结构700、钝化层800及导通孔900。绝缘包封体500横向包封芯片100及400。内连线结构700、钝化层800及导通孔900与芯片300相对地设置在芯片200上。在一些实施例中，集成电路D3可用于各种应用。例如，集成电路D3可用作InFO封装中的管芯。以下将阐述InFO封装的制造工艺。
参照图3L至图3P，除图1K至图1O中的集成电路D1被图3K中的集成电路D3所取代以外，图3L至图3P中的步骤相似于图1K至图1O中所示的步骤，因此本文中不再对其予以赘述。参照图3P，获得多个封装结构P4。如上所述，封装结构P4可被称为“InFO封装”。如图3P中所示，包封体1100与芯片200及芯片300的侧壁直接接触，以横向包封芯片200及芯片300。另一方面，重布线结构1200与芯片100、200、300及400电连接。在一些实施例中，通过在集成电路D3中引入芯片200且通过在封装结构P4中利用集成电路D3，可有效地减少封装结构P4中的翘曲及RDL应力。同时，可充分增强封装结构P4的电性能及散热。
在一些实施例中，封装结构P4可进一步与其他封装结构进行组装以形成封装。例如，参照图3Q，将封装结构P2堆叠在封装结构P4上以形成封装30。在一些实施例中，封装结构P4通过导电端子1400与封装结构P2电连接。在一些实施例中，封装30可进一步包括位于封装结构P4与封装结构P2之间的底部填充胶UF。在一些实施例中，底部填充胶UF能够保护对封装结构P4与P2进行电连接的导电端子1400。在一些实施例中，封装30可被称为“PoP”。
图4A至图4Q是根据本公开一些替代性实施例的封装40的制造工艺的示意性剖视图。参照图4A，提供半导体晶片W3。图4A中的半导体晶片W3相似于图1F中的半导体晶片W3，因此其相似的组件由相同的附图标号表示，且本文中不再对其予以赘述。在一些实施例中，半导体晶片W3具有有源表面A300及与有源表面A300相对的后表面R300。
如图4A中所示，将多个芯片400拾取并放置在半导体晶片W3上。图4A中的芯片400相似于图1F中的芯片400，因此其相似的组件由相同的附图标号表示，且本文中不再对其予以赘述。在一些实施例中，芯片400被放置成阵列，以在两个相邻的芯片400之间具有间隙G。在一些实施例中，每一芯片400具有有源表面A400及与有源表面A400相对的后表面R400。如图4A中所示，芯片400以面朝下的方式设置在半导体晶片W3上。在一些实施例中，芯片400混合接合到半导体晶片W3。例如，芯片400被放置成使得芯片400的有源表面A400与半导体晶片W3的有源表面A300直接接触。图4A中的混合接合工艺可相似于图1F中所示的混合接合工艺，因此本文中不再对其予以赘述。在一些实施例中，芯片400的介电层406与半导体晶片W3的介电层306直接接触。同时，芯片400的导体408与半导体晶片W3的导体308实质上对齐且与半导体晶片W3的导体308直接接触。
参照图4B，形成绝缘包封体500a以填充两个相邻的芯片400之间的间隙G。图4B中的绝缘包封体500a相似于图1G中的绝缘包封体500，因此本文中不再对其予以赘述。在一些实施例中，绝缘包封体500a横向包封芯片400。
参照图4B及图4C，将图4B中所示的结构上下颠倒翻面且贴合到载体C2。图4B中的载体C2可相似于图1H中的载体C2，因此本文中不再对其予以赘述。此后，在半导体晶片W3的后表面R300上执行平坦化工艺。在一些实施例中，平坦化工艺包括机械研磨工艺及/或CMP工艺。在一些实施例中，研磨半导体晶片W3的半导体衬底302a，直到显露出TSV 310为止，以便形成半导体衬底302。例如，在平坦化工艺之后，TSV 310穿透半导体衬底302。TSV 310使得能够在半导体晶片W3的前侧与背侧之间实现电通信。在一些实施例中，在显露出TSV 310之后，可进一步研磨半导体晶片W3，以减小半导体晶片W3的总体厚度。
参照图4D，在半导体晶片W3的后表面R300上形成内连线结构700a、钝化层800a及多个导通孔900a。在一些实施例中，图4D中的内连线结构700a、钝化层800a及导通孔900a分别相似于图1I中的内连线结构700、钝化层800及导通孔900，因此本文中不再对其予以赘述。在一些实施例中，内连线结构700a与半导体晶片W3的TSV 310电连接。例如，内连线结构700a的导电图案可与半导体晶片W3的TSV 310直接接触。在一些实施例中，导通孔900a形成在内连线结构700a的导电图案上且与内连线结构700a的导电图案直接接触。即，导通孔900a依序通过内连线结构700a、TSV 310、内连线结构304及导体308与芯片400电连接。
参照图4D及图4E，移除载体C2，且在图4D中所示的结构上执行单体化工艺，以获得多个集成电路D4。图4E中的单体化工艺相似于图1J中的单体化工艺，因此本文中不再对其予以赘述。在一些实施例中，单体化工艺将半导体晶片W3分割成多个芯片300。图4E中的芯片300相似于图1J中的芯片300，因此其相似的组件由相同的附图标号表示，且本文中不再对其予以赘述。在一些实施例中，芯片300堆叠在芯片400上且混合接合到芯片400。在一些实施例中，芯片300的厚度H300的范围介于约10μm到约50μm之间，而芯片400的厚度H400的范围介于约10μm到约120μm之间。在一些实施例中，由于多个芯片(芯片300及400)被集成到单个集成电路D4中，因此集成电路D4可被称为“SOIC”。
参照图4F至图4I，图4F至图4I中的步骤相似于图1A至图1D中所示的步骤，因此本文中不再对其予以赘述。
参照图4I及图4J，移除载体C1。随后，将图4I中所示的结构上下颠倒翻面且贴合到载体C6。换句话说，将半导体晶片W2贴合到载体C6。载体C6相似于图1H中的载体C2，因此本文中不再对其予以赘述。此后，在半导体晶片W1上形成内连线结构700b、钝化层800b及多个导通孔900b。图4J中的内连线结构700b、钝化层800b及导通孔900b分别相似于图1I中的内连线结构700、钝化层800及导通孔900，因此本文中不再对其予以赘述。在一些实施例中，内连线结构700b与半导体晶片W1的导体108电连接。例如，内连线结构700b的导电图案可与半导体晶片W1的导体108直接接触。在一些实施例中，导通孔900b形成在内连线结构700b的导电图案上且与内连线结构700b的导电图案直接接触。
参照图4J及图4K，移除载体C6，且在图4J中所示的结构上执行单体化工艺，以获得多个集成电路D5。图4K中的单体化工艺相似于图1J中的单体化工艺，因此本文中不再对其予以赘述。在一些实施例中，单体化工艺将半导体晶片W1分割成多个芯片100，且将半导体晶片W2分割成多个芯片200。图4K中的芯片100及芯片200分别相似于图1J中的芯片100及芯片200，因此其相似的组件由相同的附图标号表示，且本文中不再对其予以赘述。在一些实施例中，芯片100通过接合膜BF2熔融接合到芯片200。在一些实施例中，芯片100的侧壁与芯片200的侧壁对齐。在一些实施例中，芯片100的厚度H100的范围介于约10μm到约50μm之间，而芯片400的厚度H400的范围介于约10μm到约120μm之间。在一些实施例中，由于多个芯片(芯片100及200)被集成到单个集成电路D5中，因此集成电路D5可被称为“SOIC”。
同时参照图4E及图4K，集成电路D4包括芯片300、400，而集成电路D5包括芯片100、200。在一些实施例中，芯片200可由与芯片100、300及400相同的材料制成。因此，可减少集成电路D5或随后形成的封装的不同组件之间的CTE失配。因此，由集成电路D5或随后形成的封装的制造工艺产生的翘曲可被最小化，从而提高良率。此外，在一些实施例中，芯片200还可用作散热机构，以在随后形成的封装的操作期间增加散热速率。在一些实施例中，集成电路D4及集成电路D5可用于各种应用。例如，集成电路D4及集成电路D5可用作InFO封装中的管芯。以下将阐述InFO封装的制造工艺。
参照图4L至图4P，除图1K至图1O中的集成电路D1被图4E中的集成电路D4及图4K中的集成电路D5所取代以外，图4L至图4P中的步骤相似于图1K至图1O中所示的步骤，因此本文中不再对其予以赘述。参照图4M及图4N，将集成电路D4及集成电路D5放置成在所述两者之间具有间隙G1。例如，集成电路D4与集成电路D5间隔开。即，芯片100及芯片200与芯片300及芯片400间隔开。如图4N中所示，将包封体1100填充到间隙G1中。例如，包封体1100的至少一部分位于集成电路D4与集成电路D5之间。换句话说，包封体1100的至少一部分位于芯片100与芯片300之间，且位于芯片200与芯片400之间。在一些实施例中，从俯视图来看，芯片300的侧壁不与芯片100的侧壁及芯片200的侧壁对齐。
参照图4P，获得多个封装结构P5。如上所述，封装结构P5可被称为“InFO封装”。如图4P中所示，包封体1100与芯片100、200及300的侧壁直接接触，以横向包封芯片100、200及300。另一方面，重布线结构1200与芯片100、300及400电连接。在一些实施例中，通过在集成电路D5中引入芯片200且通过在封装结构P5中利用集成电路D5，可有效地减少封装结构P5中的翘曲及RDL应力。同时，可充分增强封装结构P5的电性能及散热。
在一些实施例中，封装结构P5可进一步与其他封装结构进行组装以形成封装。例如，参照图4Q，将封装结构P2堆叠在封装结构P5上以形成封装40。在一些实施例中，封装结构P5通过导电端子1400与封装结构P2电连接。在一些实施例中，封装40可进一步包括位于封装结构P5与封装结构P2之间的底部填充胶UF。在一些实施例中，底部填充胶UF能够保护对封装结构P5与P2进行电连接的导电端子1400。在一些实施例中，封装40可被称为“PoP”。
图5A至图5B是根据本公开一些替代性实施例的封装60的制造工艺的示意性剖视图。参照图5A，提供集成电路D6。在一些实施例中，图5A中的集成电路D6相似于图2F中的集成电路D2，因此其相似的组件由相同的附图标号表示，且本文中不再对其予以赘述。然而，在图5A所示的集成电路D6中省略了图2F中的钝化层800。此外，集成电路D6进一步包括形成在导通孔900上的焊料900’。
在一些实施例中，由于多个芯片(芯片100、200、300及400)被集成到单个集成电路D6中，因此集成电路D6可被称为“SOIC”。如图5A中所示，芯片100与芯片400并排设置在芯片300上。同时，芯片100与芯片400也并排设置在芯片200上。例如，芯片100及芯片400夹置在芯片200与芯片300之间。芯片100及芯片400混合接合到芯片300。另一方面，芯片100及芯片400熔融接合到芯片200。在一些实施例中，芯片200可由与芯片100、300及400相同的材料制成。因此，可减少集成电路D6或随后形成的封装的不同组件之间的CTE失配。因此，由集成电路D6或随后形成的封装的制造工艺产生的翘曲可被最小化，从而提高良率。此外，在一些实施例中，芯片200还可用作散热机构，以在随后形成的封装的操作期间增加散热速率。在一些实施例中，集成电路D6可用于各种应用。例如，集成电路D6可用作倒装芯片封装(flip-chip package)中的管芯。
参照图5B，提供电路衬底SUB。在一些实施例中，电路衬底SUB具有嵌入其中的多个导电图案。电路衬底SUB的导电图案彼此内连。如图5B中所示，集成电路D6堆叠在电路衬底SUB的一侧上以形成封装60。在一些实施例中，集成电路D6与电路衬底SUB电连接。例如，集成电路D6的导通孔900及焊料900’与电路衬底SUB的导电图案电连接。在一些实施例中，封装60可进一步包括底部填充胶UF。在一些实施例中，底部填充胶UF的至少一部分位于集成电路D6与电路衬底SUB之间。在一些实施例中，底部填充胶UF能够保护对集成电路D6与电路衬底SUB进行电连接的导通孔900及焊料900’。在一些实施例中，封装60可进一步包括与集成电路D6相对地位于电路衬底SUB上的多个导电端子1500。在一些实施例中，导电端子1500相似于图1N中的导电端子1300，因此本文中不再对其予以赘述。在一些实施例中，导电端子1500与电路衬底SUB的导电图案直接接触且与电路衬底SUB的导电图案电连接。如上所述，在一些实施例中，封装60可被称为“倒装芯片封装”。
根据本公开的一些实施例，一种封装包括集成电路。所述集成电路包括第一芯片、第二芯片、第三芯片及第四芯片。所述第二芯片及所述第三芯片并排设置在所述第一芯片上。所述第二芯片及所述第三芯片混合接合到所述第一芯片。所述第四芯片熔融接合到所述第二芯片及所述第三芯片中的至少一者。
根据本公开的一些实施例，所述第四芯片堆叠在所述第三芯片上且熔融接合到所述第三芯片，且所述第三芯片的厚度与所述第四芯片的厚度的和实质上等于所述第二芯片的厚度。
根据本公开的一些实施例，所述第四芯片堆叠在所述第二芯片及所述第三芯片两者上且熔融接合到所述第二芯片及所述第三芯片两者，且所述第二芯片的厚度与所述第四芯片的厚度的和实质上等于所述第三芯片的厚度与所述第四芯片的所述厚度的和。
根据本公开的一些实施例，所述第四芯片是虚设芯片(dummy chip)。
根据本公开的一些实施例，所述第一芯片进一步包括嵌入其中的多个半导体穿孔(through semiconductor via，TSV)。
根据本公开的一些实施例，所述集成电路进一步包括横向包封所述第二芯片及所述第三芯片的绝缘包封体。
根据本公开的一些实施例，所述绝缘包封体进一步横向包封所述第四芯片。
根据本公开的一些实施例，所述集成电路进一步包括穿透所述绝缘包封体的多个绝缘穿孔(through insulating via，TIV)。
根据本公开的一些实施例，所述封装进一步包括多个导电结构、包封体、重布线结构以及多个导电端子。所述导电结构环绕所述集成电路。所述包封体横向包封所述集成电路及所述导电结构。所述重布线结构设置在所述集成电路、所述包封体及所述导电结构上。所述重布线结构与所述集成电路及所述导电结构电连接。所述导电端子设置在所述重布线结构上。
根据本公开的一些实施例，所述封装进一步包括电路衬底以及底部填充胶。所述集成电路设置在所述电路衬底上且与所述电路衬底电连接。所述底部填充胶的至少一部分位于所述集成电路与所述电路衬底之间。
根据本公开的一些实施例，一种封装包括第一芯片、第二芯片、第三芯片、第四芯片、多个导电结构、包封体及重布线结构。所述第一芯片具有嵌入其中的多个半导体穿孔(through semiconductor via，TSV)。所述第二芯片堆叠在所述第一芯片上且混合接合到所述第一芯片。所述第三芯片与所述第一芯片电连接。所述第四芯片是虚设芯片。所述导电结构环绕所述第一芯片、所述第二芯片、所述第三芯片及所述第四芯片。所述包封体横向包封所述第一芯片及所述第四芯片。所述重布线结构设置在所述导电结构及所述包封体上。所述重布线结构与所述第一芯片电连接。
根据本公开的一些实施例，所述第一芯片具有第一表面及与所述第一表面相对的第二表面，所述第二芯片及所述第三芯片并排设置在所述第一芯片的所述第一表面上，所述第四芯片设置在所述第一芯片的所述第二表面上，且所述第二芯片、所述第三芯片及所述第四芯片混合接合到所述第一芯片。
根据本公开的一些实施例，所述第四芯片包括嵌入其中的多个半导体穿孔，且所述第一芯片的所述半导体穿孔连接到所述第四芯片的所述半导体穿孔。
根据本公开的一些实施例，所述第一芯片及所述第二芯片与所述第三芯片及所述第四芯片间隔开，且所述第四芯片熔融接合到所述第三芯片。
根据本公开的一些实施例，所述包封体的至少一部分位于所述第一芯片与所述第三芯片之间。
根据本公开的一些实施例，所述第四芯片的侧壁与所述第三芯片的侧壁对齐。
根据本公开的一些实施例，一种封装的制造方法包括至少以下步骤。提供其中形成有多个半导体穿孔(through semiconductor via，TSV)的半导体晶片(semiconductorwafer)。所述半导体晶片具有第一表面及与所述第一表面相对的第二表面。将第一芯片及第二芯片混合接合到所述半导体晶片的所述第一表面。所述第一芯片与所述第二芯片并排设置。通过绝缘包封体来横向包封所述第一芯片及所述第二芯片。通过熔融接合将虚设芯片贴合到所述第二芯片。对所述半导体晶片的所述第二表面进行薄化，直到暴露出所述半导体穿孔为止。在所述半导体晶片的所述第二表面上形成内连线结构。所述内连线结构与所述半导体穿孔电连接。对所述半导体晶片进行单体化。
根据本公开的一些实施例，在将所述第一芯片及所述第二芯片混合接合到所述半导体晶片的所述步骤之前，将所述虚设芯片贴合到所述第二芯片。
根据本公开的一些实施例，所述封装的制造方法进一步包括通过熔融接合将所述虚设芯片贴合到所述第一芯片，其中在将所述第一芯片及所述第二芯片混合接合到所述半导体晶片之后，将所述虚设芯片贴合到所述第一芯片及所述第二芯片。
根据本公开的一些实施例，通过熔融接合将所述虚设芯片贴合到所述第一芯片的所述步骤与通过熔融接合将所述虚设芯片贴合到所述第二芯片的所述步骤同时执行。
前述内容概述了若干个实施例的特征，以使所属领域中的技术人员可更好地理解本发明的方面。所属领域中的技术人员应理解，其可容易地使用本发明作为设计或修改其他工艺及结构的基础以施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优势。所属领域中的技术人员还应意识到此种等效构造并不背离本发明的精神及范围，且其可在不背离本发明的精神及范围的情况下在本文中做出各种变化、替代性及更改。

Claims (1)

1.一种封装，包括：
集成电路，包括：
第一芯片；
第二芯片及第三芯片，并排设置在所述第一芯片上，其中所述第二芯片及所述第三芯片混合接合到所述第一芯片；以及
第四芯片，熔融接合到所述第二芯片及所述第三芯片中的至少一者。
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Application publication date: 20201229

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