TWI701778B - 多層封裝總成及具有多層封裝總成之系統 - Google Patents
多層封裝總成及具有多層封裝總成之系統 Download PDFInfo
- Publication number
- TWI701778B TWI701778B TW105117038A TW105117038A TWI701778B TW I701778 B TWI701778 B TW I701778B TW 105117038 A TW105117038 A TW 105117038A TW 105117038 A TW105117038 A TW 105117038A TW I701778 B TWI701778 B TW I701778B
- Authority
- TW
- Taiwan
- Prior art keywords
- components
- active
- layer
- mold
- hole
- Prior art date
Links
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 18
- 239000010703 silicon Substances 0.000 claims abstract description 18
- 229910000679 solder Inorganic materials 0.000 claims description 33
- 239000012778 molding material Substances 0.000 claims description 17
- 239000004020 conductor Substances 0.000 claims description 11
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 238000005259 measurement Methods 0.000 claims description 5
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 239000012811 non-conductive material Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 90
- 238000000034 method Methods 0.000 description 20
- 238000004891 communication Methods 0.000 description 18
- 239000003989 dielectric material Substances 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 12
- 238000000465 moulding Methods 0.000 description 12
- 238000007789 sealing Methods 0.000 description 12
- 150000001875 compounds Chemical class 0.000 description 10
- 230000008569 process Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 230000009471 action Effects 0.000 description 6
- 230000000712 assembly Effects 0.000 description 6
- 238000000429 assembly Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005457 optimization Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229920000089 Cyclic olefin copolymer Polymers 0.000 description 1
- 239000004713 Cyclic olefin copolymer Substances 0.000 description 1
- 241000289427 Didelphidae Species 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000001311 chemical methods and process Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000013035 low temperature curing Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 229920006305 unsaturated polyester Polymers 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
- H01L2224/1132—Screen printing, i.e. using a stencil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73259—Bump and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81009—Pre-treatment of the bump connector or the bonding area
- H01L2224/81024—Applying flux to the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/8184—Sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
- H01L2224/92224—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1436—Dynamic random-access memory [DRAM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本文中之實施例係關於一種系統級封裝(SiP)。該SiP可具有具一或多個第一功能組件之一第一層,該一或多個第一功能組件具有各自第一作用側及與該等第一作用側相對之第一非作用側。該SiP可進一步包括具一或多個第二功能組件之一第二層,該一或多個第二功能組件具有各自第二作用側及與該等第二作用側相對之第二非作用側。在實施例中,該等第一作用側中之一或多者與該等第二作用側中之一或多者相面對且經由一穿模通孔或一穿矽通孔電耦接。
Description
本發明之實施例大體上係關於具有高密度互連封裝及小型外觀尺寸之封裝總成的領域。
諸如智慧型電話及超級本之行動電子裝置之最終產品大小的持續減小係開發具有小型外觀尺寸(SFF)之封裝技術的驅動力。已開發將多個組件併入至單個封裝中以減小系統大小的系統級封裝(SiP)技術。
依據本發明之一實施例,係特地提出一種封裝,其包含:經模封成一晶圓之具有一或多個第一組件之一第一層,該第一層具有一第一作用層側及與該第一作用層側相對之一第一非作用層側,其中該一或多個第一組件之個別組件具有一各自之第一作用組件側及與該第一作用組件側相對之一第一非作用組件側,該第一作用組件側與該第一非作用組件側在一第一方向及垂直於該第一方向之一第二方向上彼此平行,且該一或多個第一組件之各組件在垂
直於該第一方向及該第二方向之一第三方向上具有一各自z高度量測值,且該一或多個第一組件中之一第一者的一z高度係不同於該一或多個第一組件中之一第二者的一z高度;以及在一模封材料中之具有一或多個第二組件之一第二層,該第二層具有一第二作用層側及與該第二作用層側相對之一第二非作用層側,且其中該一或多個第二組件具有一第二作用組件側及與該第二作用組件側相對之一第二非作用組件側,該第二作用組件側與該第二非作用組件側沿著該第一方向及該第二方向彼此平行,且其中該第二作用層側係面向、電耦接及實體地耦接至該第一作用層側,且該第二作用層側經由一穿模通孔或一穿矽通孔被電耦接至該第二非作用層側。
100‧‧‧封裝總成
102、104‧‧‧被動組件
102a、102b、104a、104b、106a、106b‧‧‧組件之區段
106‧‧‧主動組件
108‧‧‧模封化合物/模封材料
110‧‧‧導電層/金屬化層
112‧‧‧介電材料/介電質/焊料凸塊/介電層
114、118‧‧‧通孔
116‧‧‧焊料遮罩
120‧‧‧預成形焊料凸塊
122、124、322、324‧‧‧晶粒
122a‧‧‧穿矽通孔
126‧‧‧模封材料
128、130‧‧‧穿模通孔
132‧‧‧模封材料
134‧‧‧球腳柵格陣列
200、300‧‧‧替代性封裝總成
210‧‧‧導電組件/導電材料
232‧‧‧非導電組件
302‧‧‧焊料凸塊/球腳柵格陣列(BGA)球凸部
310‧‧‧導電材料
326‧‧‧薄模封層
400‧‧‧用於製造造封裝總成之方法
402至440‧‧‧方塊
500‧‧‧計算裝置
502‧‧‧主機板
504‧‧‧處理器
506‧‧‧通訊晶片
520‧‧‧依電性記憶體
522‧‧‧快閃記憶體
524‧‧‧非依電性記憶體
526‧‧‧晶片組
528‧‧‧天線
530‧‧‧圖形處理器
532‧‧‧觸控螢幕顯示器
536‧‧‧電池
540‧‧‧全球定位系統裝置
541‧‧‧功率放大器
542‧‧‧羅盤
546‧‧‧觸控式螢幕控制器
550‧‧‧揚聲器
551‧‧‧罩殼
552‧‧‧攝影機
555‧‧‧封裝總成組件
圖1-A至圖1-K說明根據實施例之處於製造製程之各個階段之封裝總成的實例。
圖2說明根據實施例之處於製造製程之結束階段之封裝總成的另一實例。
圖3說明根據實施例之處於製造製程之結束階段之封裝總成的另一實例。
圖4說明根據實施例之用於製造封裝總成之製程的實例。
圖5示意性地說明根據實施例之計算裝置。
本發明之實施例大體上係關於高密度互連封裝及極小外觀尺寸之領域。特定而言,高度整合之系統級封裝(SiP)能夠藉由以下操作來製造:在建置之前且之後將具有數個功能組件之兩個層整合於模封化合物(molding compound)中,且接著將該兩個模封層焊接結合或以黏合方式結合。在以下詳細描述中,參考形成詳細描述之一部分的隨附圖式,其中通篇類似數字指定類似部件,且其中藉助於圖示展示可實踐本發明之標的之實施例。應理解,在不背離本發明之範疇之情況下,可利用其他實施例,且可進行結構或邏輯改變。因此,以下詳細描述不應以限制性意義來理解,且實施例之範疇係由所附申請專利範圍及其等效物來界定。
出於本發明之目的,片語「A及/或B」意謂(A)、(B)或(A及B)。出於本發明之目的,片語「A、B及/或C」意謂(A)、(B)、(C)、(A及B)、(A及C)、(B及C)或(A、B及C)。
描述可使用基於視角之描述,諸如頂部/底部、內/外、上方/下方及類似者。此等描述僅用以促進論述且不欲將本文中所描述之實施例之應用限於任何特定定向。
描述可使用片語「在一實施例中」或「在實施例中」,該等片語可各自係指一或多個相同或不同實施例。此外,如關於本發明之實施例而使用,術語「包含」、「包括」、「具有」及其類似者為同義的。
可在本文中使用術語「與……耦接(coupled with)」連同其衍生詞。「耦接」可意謂以下一或多者。「耦接」可
意謂兩個或兩個以上元件直接實體或電接觸。然而,「耦接」亦可意謂兩個或兩個以上元件彼此間接接觸,但又仍彼此協作或相互作用,且可意謂一或多個其他元件在據稱為彼此耦接的元件之間耦接或連接。術語「直接耦接」可意謂兩個或元件處於直接接觸。
各種操作以最有助於理解所主張之標的之方式可依次描述為多個離散操作。然而,描述之次序不應解釋為暗示此等操作為必須依賴於次序的。
如本文所使用,術語「模組」可指以下各項、係以下各項之一部分或包括以下各項:ASIC、電子電路、執行一或多個軟體或韌體程式之處理器(共享、專用或群組)及/或記憶體(共享、專用或群組)、組合邏輯電路及/或提供所描述功能性之其他適合組件。
本文中之各種圖可描繪一或多個封裝總成之一或多個層。本文中所描繪之層被描繪為不同封裝總成之層之相對位置的實例。該等層出於解釋目的而描繪,且未按比例繪製。因而,不應依據諸圖假定比較性層大小,且僅可針對所具體指示或論述之某些實施例假定大小、厚度或尺寸。
如上文所提及,封裝大小按比例調整對於總成製造而言至關重要。在一些實施例中,所揭示封裝可實現:具有變化之x高度、y高度及z高度之多個主動及被動組件之整合;如負鼠(Opossum)組態之矽晶粒至矽晶粒組態;面板級處理;兩個或兩個以上模封化合物以使低密度及高密度
I/0裝置嵌入之整合最佳化;扇入及扇出之實施;以及在不研磨模封體的情況下對準且暴露金屬***支柱,在無額外鍍覆製程情況下使通孔互連。詳言之,高度整合之系統級封裝(SiP)能夠藉由在建置之前且之後將具有多個功能組件之兩個層整合於模封化合物中,且接著將該兩個模封層焊接結合或以黏合方式結合來製造。此情形亦可具有組件之間的較短佈線距離之優點。另外,此情形亦可具有將被動裝置附接至模封體中(其中被動裝置可為厚組件)且稍後可將可為極薄的主動組件附接於不同層中的優點。因此,經模封層可為厚的,且所附接之矽晶粒可為薄的。
圖1-A至圖1-K描繪處於製造製程之各個階段之此類封裝總成的實例。在實施例中,一或多個元件可在較早圖(例如圖1-A)中被引入,且接著假定在諸如圖1-B之稍後圖中繼續存在。因而,為清楚且易於理解起見,可能不會在圖1-A至圖1-K之每個階段中標註封裝總成100之每個元件。
具體言之,圖1-A描繪包括被動組件102、104及主動組件106之封裝總成100。在實施例中,組件之區段102a、104a及106a可表示可電耦接組件之區域,且組件之區段102b、104b及106b可表示不能夠電耦接組件之區域。在實施例中,可使用任何數目個被動或主動組件。在非限制性實例中,被動組件可包括或涉及電阻器或電容器,且主動組件可包括或涉及電晶體或積體電路。
在實施例中,此等組件可至少部分地被模封化合
物108包圍。模封化合物108可為某其他電及/或熱中性層,該電及/或熱中性層可增加組件102、104、106之側表面面積,及/或以電或熱方式隔離組件102、104、106。在一些實施例中,模封化合物108可為環氧樹脂,儘管在其他實施例中,模封化合物可為或可包括酚、不飽和聚酯、熱固性聚醯亞胺等。
組件102、104、106中之每一者可具有在第一方向及垂直於組件之第一方向之第二方向上平行於彼此之不同的作用側及非作用側。垂直於第一方向及第二方向之第三方向可被稱為z高度。在實施例中,組件之z高度可小於模封體108之z高度。
接著,如圖1-B中所展示,在實施例中,可塗覆導電層110而以各種方式連接組件102、104、106。舉例而言,在一些實施例中,導電層110可經由濺鍍及電鍍或無電鍍敷及電鍍來塗覆。在實施例中,可首先塗覆晶種層且可稍後增加其厚度。導電層110可為銅或諸如金(Au)之某一其他導電材料。
隨後,在實施例中,可在導電層110上方塗覆介電材料112。在實施例中,此介電材料可為旋塗塗層,諸如WPR感光性介電材料(購自JSR Corporation®)或其他介電材料。在實施例中,可經由層壓來施加介電質。
接著,如圖1-C中所展示,可在介電材料112中開出通孔114。在實施例中,可在介電質係感光性的情況下藉由光學方法開出通孔114。在其他實施例中,可藉由雷射鑽
孔、化學蝕刻或某一其他物理、光學及/或化學製程開出通孔114。
接著,如圖1-D中所展示,可添加用於佈線之金屬化層110。在實施例中,該層可為具有鍍層之半相加式層,且可被稱為第二導電層。第二導電層可允許佈線之交叉,且可以與第一導電層相同或類似之方式被塗覆。
接著,如圖1-E中所展示,可沈積焊料遮罩116,且可在遮罩內開出通孔118。在實施例中,可被稱為焊料阻擋層之焊料遮罩116可為可保護表面層金屬化且提供與其他裝置連接之通路的光定義之介電材料。焊料遮罩116可為與介電材料112相同之材料,且可經旋塗、狹縫式塗佈或層壓。在實施例中,焊料遮罩116之厚度可大於介電質112之厚度。
接著,如圖1-F中所展示,可添加焊料凸塊120。在實施例中,可在印刷製程中在通孔118上塗覆助熔劑,以形成用於焊料凸塊120之區域。在實施例中,接著可(例如)在類似印刷之製程中經由模板施加預成形焊料凸塊120。在實施例中,該封裝接著可經歷回焊製程,其中助熔劑可移除襯墊及焊料凸塊112上之氧化層,且一或多個焊接凸塊112可熔融且與襯墊接觸。
接著,如圖1-G中所展示,一或多個晶粒122、124可附接至焊料凸塊120及電耦接至該焊料凸塊。晶粒122、124可為(例如)矽或某一其他導電或導熱或半導電材料。儘管未示出,但在一些實施例中,晶粒122、124可包括形成
於晶粒122、124之作用側上之一或多個電晶體裝置及/或各個互連結構層以將電信號及/或電力導引至一或多個電晶體裝置。在實施例中,晶粒或組件之作用側可為晶粒或組件可電耦接至的側。可為相對側之非作用側係組件可能無法電耦接至之側。具體言之,在一些實施例中,晶粒122、124可包括一或多個層或材料,諸如介電材料、基體、半導體材料、鈍化層,或此項技術中可已知之某一其他材料或層。在實施例中,通孔122a可併入至晶粒122中。
接著,如圖1-H中所展示,可底填充且模封126晶粒122、124。在實施例中,轉移成型製程可在晶圓級進行及/或可在面板級進行。在實施例中,用於模封體之材料可具有兩個組份,其可包括較軟相,諸如樹脂或聚合物,且可包括較硬相,諸如二氧化矽(SiO2)或碳化矽(SiC)。較軟相可為材料提供可移動性以在特定條件下流動,且一旦流動結束且完全固化,較硬相可提供所要之機械強度。
接著,如圖1-I中所展示,可穿過模封體126切割出穿模通孔128、130。在實施例中,可僅切割出穿過模封體126之通孔128。在其他實施例中,可切割出穿過模封體126及焊料遮罩116之通孔130。在實施例中,此可藉由雷射或化學、物理或其他光學製程完成,或可與具有穿矽通孔122a之矽晶粒中之一者一起完成。
接著,如圖1-J中所展示,可鍍覆110通孔128、130。在實施例中,此情形可涉及濺鍍、電鍍或無電鍍敷,及/或其他方法,諸如膏劑印刷、焊料燒結,或焊料回焊。
在實施例中,可添加額外模封材料132。
接著,如圖1-K中所展示,可翻轉封裝100,且可應用呈區域陣列定向之焊料球以達成可被附接之球腳柵格陣列(BGA)134。在實施例中,此時,晶粒122、124與組件102、104、106相面對,處於分離模封體中,以面對面對準方式接合且電耦接。此結構可具有晶粒122、124與組件102、104、106之間較短連接之優點。其亦可具有支援額外扇入(邏輯閘之輸入之數目)或扇出(該結構之邏輯輸出能夠驅動之邏輯輸入的數目)之優點。
圖2描繪可實施平面柵格陣列(LGA)之替代性封裝總成200。在實施例中,LGA實施可產生較小總體外觀尺寸,具體言之,在總體封裝之z高度上的較小總體外觀尺寸。在實施例中,可翻轉圖1-J中展示之封裝,且可附接用於平面柵格陣列(LGA)之著陸墊。在實施例中,LGA可藉由將焊料遮罩116開孔且接著在通孔區域(例如,在通孔122a處或附近)鍍覆或沈積導電層而形成。因而,LGA可包括導電組件210及非導電組件232。封裝總成200藉由以下情形不同於圖1-K中之封裝總成100:允許較低輪廓LGA連接而非可能需要焊接之較高輪廓BGA連接。在實施例中,封裝之較低豎直(stand-off)高度可提供增加的可靠性。
圖3描繪可實施球腳柵格陣列(BGA)球凸部302之替代性封裝總成300,該球凸部302可填充更大型穿模通孔。在實施例中,可以可使晶粒322、324(如圖1-H之122、124)之上部部分暴露之方式替代地應用薄之模封層326(如
圖1-H之126)。此情形(例如)在可能不需要形成額外扇入、扇出及/或佈線建置時可為有用的。在不藉由模封材料包圍晶粒322、324之上部部分的情況下,可存在額外熱耗散之優點。
圖4描繪根據各種實施例之展示用於製造諸如封裝總成100之封裝總成之方法400的流程圖。方法400可在方塊402處開始。
在方塊404處,可將諸如組件102、104、106之裝置嵌入於模封體中。在實施例中,可將裝置嵌入於晶圓(未示出)上之模封體中,可釋放且翻轉經模封之晶圓。在其他實施例中,裝置可包括諸如被動組件102、104之被動組件及/或諸如主動組件106之主動組件,如圖1-A中所展示(在可能已翻轉晶圓之後)。在實施例中,諸如模封化合物108之模封化合物可部分或完全包圍該等組件。
在方塊408處,可塗覆諸如介電層112之介電質。在實施例中,此操作亦可包括塗覆諸如導電層110之導電層以用各種方式連接諸如組件102、104、106之一或多個組件。導電層110可具有某一導電金屬。在實施例中,諸如介電質112之介電質可塗覆於諸如導電層110之導電層上方,且塗覆至諸如模封材料108之模封材料的邊緣,如圖1-B中所展示。諸如介電質112之介電質可包括旋塗塗層WPR,或其他適合介電材料。在實施例中,可使用低溫固化聚醯亞胺。在其他實施例中,可(例如)在基體係矩形的情況下使用層壓層。
在方塊410處,可在諸如介電質112之介電質中開出諸如通孔114之通孔。在實施例中,諸如在圖1-C上展示之通孔114的介電質通孔(例如)在介電質係感光性的情況下可藉由光學方法開出,或可藉由雷射鑽孔開出。
在方塊412處,可應用諸如金屬化層110之金屬化層以用於佈線。在實施例中,金屬化層110可具有導電金屬,如圖1-D中所展示。
在方塊414處,可沈積諸如圖1-E上之焊料遮罩116的焊料遮罩,且可在焊料遮罩中開出諸如通孔118之通孔。
在方塊416處,可附接諸如焊料凸塊120之焊料凸塊。
在方塊418處,可附接諸如矽晶粒122、124之晶粒。經附接矽晶粒之實施例在圖1-G上展示,且可包括附接至焊料凸塊120之晶粒。
在方塊420處,可執行檢查以判定諸如晶粒122、124之晶粒之部分是否將暴露。若判定結果展示晶粒將暴露,則在方塊422處,可底填充該等晶粒。在實施例中,諸如如在圖1-H中所展示之模封材料126的模封材料可在晶粒122、124下方流動,從而使晶粒122、124之表面及/或上部部分暴露(未示出)。在方塊424處,可附接諸如圖3中之焊料凸塊302的焊料凸塊。此後,方法400可在方塊440處結束。
在方塊420處,若晶粒之一部分將不暴露,則在方塊426處,可底填充諸如晶粒122、124之晶粒,且可在晶
粒上方使用諸如模封體126之模封體。在實施例中,諸如模封體126之模封體可裝封晶粒122、124。
在方塊428處,可開出諸如通孔128、130之穿模通孔。在實施例中,可穿過諸如模封體126之模封體切割出穿模通孔128、130,如圖1-I中所展示。在實施例中,可僅穿過諸如模封體126之模封體切割出諸如通孔128之通孔。在其他實施例中,可穿過諸如模封體126之模封體及焊料遮罩116切割出諸如通孔130之通孔。在實施例中,此操作可藉由雷射完成,或可與具有穿矽通孔122a之矽晶粒中之一者一起完成。
在方塊430處,可填充諸如通孔128、130之通孔。在實施例中,可用諸如在圖1-J中發現之材料110的導電材料鍍覆諸如通孔128、130之通孔。在其他實施例中,可藉由諸如電鍍、無電鍍敷、膏劑印刷、焊料燒結或焊料回焊之方法鍍覆通孔。在另其他實施例中,在鍍覆之後,可添加諸如模封材料132之額外模封材料,且額外模封材料可含有通孔(未示出)以允許接入導電材料110。
在方塊432處,可執行檢查以判定諸如BGA 134之BGA是否將用於連接。若判定結果展示BGA將用於連接,則在方塊434處,可翻轉封裝,且諸如BGA 302之BGA可連接至諸如導電材料310(如圖2之210;及/或如圖1B、圖1D、圖1J及圖1K之110)之導電材料,BGA可為諸如模封材料132中之通孔(未示出)的穿孔。此後,方法400可在方塊440處結束。
在方塊432處,若BGA將不用於連接,則在方塊436處,可執行檢查以判定LGA是否將用於連接。在實施例中,LGA層可由被諸如頂部模封層212之頂部模封層隔開的諸如導電材料210(如圖1B、圖1D、圖1J及圖1K之110)之導電材料構成。若判定結果展示將使用LGA,則在方塊438處,可翻轉封裝且可產生LGA連接。在實施例中,LGA連接可具有如在圖2中所展示之佈局。此後,方法400可在方塊440處結束。
本發明之實施例可使用任何合適硬體及/或軟體視需要進行組配而實施至系統中。圖5示意性地說明根據本發明之一個實施的計算裝置500。計算裝置500可容納諸如主機板502之板(亦即,罩殼551)。主機板502可包括數個組件,該等組件包括(但不限於)處理器504及至少一個通訊晶片506。處理器504可實體地且電耦接至主機板502。在一些實施中,至少一個通訊晶片506亦可實體地且電耦接至主機板502。在進一步實施中,通訊晶片506可為處理器504之部分。
取決於應用,計算裝置500可包括可以或可不實體地且電耦接至主機板502之其他組件。此等其他組件可包括(但不限於)以下各者:依電性記憶體(例如,DRAM)520、非依電性記憶體(例如,ROM)524、快閃記憶體522、圖形處理器530、數位信號處理器(未示出)、密碼處理器(未示出)、晶片組526、天線528、顯示器(未示出)、觸控式螢幕顯示器532、觸控式螢幕控制器546、電池536、音訊編解碼器(未
示出)、視訊編解碼器(未示出)、功率放大器541、全球定位系統(GPS)裝置540、羅盤542、加速度計(未示出)、回轉儀(未示出)、揚聲器550、攝影機552及大容量儲存裝置(諸如硬碟機、光碟(CD)、數位化通用光碟(DVD)等)(未示出)。圖5中未展示之其他組件可包括麥克風、濾波器、振盪器、壓力感測器或RFID晶片。在實施例中,封裝總成組件555中之一或多者可為諸如圖1-K中展示之封裝總成100、圖2中展示之封裝總成200或圖3中展示之封裝總成300的封裝總成。
通訊晶片506可實現將資料傳送至計算裝置500及將資料自計算裝置500傳送出的無線通訊。術語「無線」及其衍生詞可用以描述可經由使用經調變電磁輻射經由非實體媒體傳達資料的電路、裝置、系統、方法、技術、通訊頻道等。該術語並不暗示相關聯裝置不含有任何導線,儘管在一些實施例中該等裝置可能不含有導線。通訊晶片506可實施數個無線標準或協定中之任一者,該等無線標準或協定包括(但不限於)電氣電子工程師學會(IEEE)標準,包括Wi-Fi(IEEE 802.11族)、IEEE 802.16標準(例如,IEEE 802.16-2005修正案)、長期演進(LTE)計劃連同任何修正案、更新及/或修訂(例如,高階LTE計劃、超級行動寬頻(UMB)計劃(亦被稱作「3GPP2」)等)。與IEEE 802.16相容之BWA網路通常被稱為WiMAX網路,WiMAX係表示微波存取全球互通(Worldwide Interoperability for Microwave Access)之首字母縮寫,係通過IEEE 802.16標準之一致性及互通測試之產品的認證標示。通訊晶片506可根據全球行動通訊系統
(GSM)、通用封包無線電服務(GPRS)、通用行動電信系統(UMTS)、高速封包存取(HSPA)、演進型HSPA(E-HSPA)或LTE網路來操作。通訊晶片506可根據增強型GSM演進資料(EDGE)、GSM EDGE無線電存取網路(GERAN)、通用陸地無線電存取網路(UTRAN)或演進型UTRAN(E-UTRAN)來操作。通訊晶片706可根據分碼多重存取(CDMA)、分時多重存取(TDMA)、數位增強型無線電信(DECT)、演進資料最佳化(EV-DO)、其衍生物以及指定為3G、4G、5G及更高之任何其他無線協定來操作。在其他實施例中,通訊晶片506可根據其他無線協定操作。
計算裝置500可包括多個通訊晶片506。舉例而言,第一通訊晶片506可專用於較短距離無線通訊(諸如,Wi-Fi及藍芽),且第二通訊晶片506可專用於較長距離無線通訊(諸如,GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他)。在一些實施例中,通訊晶片中之一或多者可包括封裝總成(諸如,本文中描述之封裝總成100、200、300中之一者)中之晶粒。
計算裝置500之處理器504可包括封裝總成(諸如,本文中描述之封裝總成100、200、300中之一者)中之晶粒。術語「處理器」可指處理來自暫存器及/或記憶體之電子資料以將彼電子資料變換成可儲存於暫存器及/或記憶體中之其他電子資料的任何裝置或裝置之部分。
在各種實施中,計算裝置500可為膝上型電腦、上網本、筆記型電腦、超級本、智慧型電話、平板電腦、
個人數位助理(PDA)、超級行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描儀、監視器、機上盒、娛樂控制單元、數位攝影機、攜帶型音樂播放器或數位視訊錄製器。在進一步實施中,計算裝置500可為處理資料之任何其他電子裝置,例如一體式裝置,諸如一體式傳真或印刷裝置。
實例
實例1係一種封裝,其包含:經模封成一晶圓之具有一或多個第一組件的一第一層,該第一層具有一第一作用層側及與該第一作用層側相對之一第一非作用層側,其中該一或多個第一組件中之各別組件具有在一第一方向及垂直於該第一方向之一第二方向上平行於彼此的一各別第一作用組件側及與該第一作用組件側相對之一第一非作用組件側,且該一或多個第一組件中之各別者具有在垂直於該第一方向及該第二方向之一第三方向上的一各別z高度量測值,且該一或多個第一組件中之一第一者的一z高度不同於該一或多個第一組件中之一第二者的一z高度;以及在一模封材料中之具有一或多個第二組件的一第二層,該第二層具有一第二作用層側及與該第二作用層側相對之一第二非作用層側,且其中該一或多個第二組件具有沿著該第一方向及該第二方向平行於彼此的一第二作用組件側及與該第二作用組件側相對之一第二非作用組件側,且其中該第二作用層側與該第一作用層側相面對、電耦接及實體地耦接,且該第二作用層側經由一穿模通孔或一穿矽通孔
電耦接至該第二非作用層側。
實例2可包括實例1之標的物,其進一步包含附接至該第二非作用側且電耦接至該第二作用側之一平面柵格陣列或一球腳柵格陣列。
實例3可包括實例1至2中之任一者之標的物,其中該第二作用層側經由焊料或黏著劑與該第一作用層側實體地耦接。
實例4可包括實例1至3中之任一者之標的物,其中該一或多個第一組件中之一者在該第一方向上之一長度比該一或多個第二組件中之一者在該第一方向上之一長度長。
實例5係一種封裝,其包含:具有一或多個第一功能組件之一第一層,該一或多個第一功能組件具有各別第一作用側及與該等第一作用側相對之第一非作用側;具有一或多個第二功能組件之一第二層,該一或多個第二功能組件具有各別第二作用側及與該等第二作用側相對之第二非作用側;且其中該等第一作用側中之一或多者與該等第二作用側中之一或多者相面對且經由一穿模通孔或一穿矽通孔電耦接。
實例6可包括實例5之標的物,其中該第一層之一或多個第一功能組件之經模封成一晶圓。
實例7可包括實例5至6中之任一者之標的物,其中該第二層之一或多個第二功能組件係在一模封材料中。
實例8可包括實例7之標的物,其中該模封材料包
括環烯烴共聚物。
實例9可包括實例5至8中之任一者之標的物,其中該一或多個第一功能組件之各別者之該第一作用側與該一或多個第一功能組件之該等各別者之該第一非作用側在一第一方向及垂直於該第一方向之一第二方向上平行於彼此,該一或多個第一組件之各別者具有在垂直於該第一方向及該第二方向之一第三方向上的一各別z高度量測值,且該一或多個第一組件中之一第一者的一z高度不同於該一或多個第一組件中之一第二者的一z高度。
實例10可包括實例5至9中之任一者之標的物,其中一功能組件係一被動組件或一主動組件。
實例11可包括實例10之標的物,其中一被動組件係一電阻器或一電容器。
實例12可包括實例10之標的物,其中一主動組件係一電晶體或一積體電路。
實例13可包括實例5至12中之任一者之標的物,其中該封裝係一系統級封裝(SiP)。
實例14係一種具有一封裝總成之系統,該系統包含:一電路板;一封裝總成,其與該電路板耦接,該封裝總成包含:具有一或多個第一功能組件之一第一層,該一或多個第一功能組件具有各別第一作用側及與該等第一作用側相對之第一非作用側;具有一或多個第二功能組件之一第二層,該一或多個第二功能組件具有各別第二作用側及與該等第二作用側相對之第二非作用側,其中該等第一
作用側中之一或多者與該等第二作用側中之一或多者相面對且經由一穿模通孔或一穿矽通孔電耦接。
實例15可包括實例14之標的物,其中該第一作用側藉由一穿模通孔或一穿矽通孔與該第二非作用側電耦接。
實例16可包括實例14至15中之任一者之標的物,其進一步包含附接至該第二非作用側且電耦接至該第一作用側之一平面柵格陣列或一球腳柵格陣列。
實例17可包括實例14至16中之任一者之標的物,其中該第一層及該第二層係經模封。
實例18可包括實例17之標的物,其中該第一層模封體與該第二層模封體為不同化合物者。
實例19可包括實例18之標的物,其中該第一功能組件或該第二功能組件係一扇出組件。
實例20可包括實例14至19中之任一者之標的物,其中該一或多個第一功能組件之各別者之該第一作用側與該一或多個第一功能組件之該等各別者之該第一非作用側在一第一方向及垂直於該第一方向之一第二方向上平行於彼此,該一或多個第一組件之各別者具有在垂直於該第一方向及該第二方向之一第三方向上的一各別z高度量測值,且該一或多個第一組件中之一第一者的一z高度不同於該一或多個第一組件中之一第二者的一z高度。
各種實施例可包括上述實施例之任何合適組合,包括以聯合形式(及)在上文描述的實施例之替代(或)實施
例(例如,「及」可為「及/或」)。此外,一些實施例可包括一或多個製品(例如,非暫時性電腦可讀媒體),該一或多個製品上儲存有在執行時產生上述實施例中之任一者之動作的指令。此外,一些實施例可包括具有用於進行上述實施例之各種操作之任何合適構件的設備或系統。
本發明之所說明實施的以上描述(包括發明摘要中所描述之內容)並不意欲為詳盡的或將本發明限於所揭示之精確形式。雖然本文中出於例示性目的描述本發明之特定實施及實例,但如熟習相關技術者將認識到,在本發明之範疇內各種等效修改為可能的。
根據以上詳細描述,可對本發明作出此等修改。以下申請專利範圍中所用之術語不應理解為將本發明限於本說明書及申請專利範圍中所揭示之特定實施。確切而言,本發明之範疇應完全由以下申請專利範圍來判定,申請專利範圍將根據申請專利範圍解釋之已確立原則來解釋。
100:封裝總成
102、104:被動組件
106:主動組件
110:導電層/金屬化層
122、124:晶粒
132:模封材料
134:球腳柵格陣列
Claims (6)
- 一種封裝總成,其包含:經模封成一晶圓之具有二或多個第一組件之一第一層,該第一層具有一第一作用層側及與該第一作用層側相對之一第一非作用層側,其中該等二或多個第一組件之個別組件具有一各自之第一作用組件側及與該第一作用組件側相對之一第一非作用組件側,該第一作用組件側與該第一非作用組件側在一第一方向及垂直於該第一方向之一第二方向上彼此平行,且該等二或多個第一組件之各組件在垂直於該第一方向及該第二方向之一第三方向上具有一各自z高度量測值,且該等二或多個第一組件中之一第一者的一z高度係不同於該等二或多個第一組件中之一第二者的一z高度;以及在一模封材料中之具有二或多個第二組件之一第二層,該第二層具有一第二作用層側及與該第二作用層側相對之一第二非作用層側,且其中該等二或多個第二組件具有一第二作用組件側及與該第二作用組件側相對之一第二非作用組件側,該第二作用組件側與該第二非作用組件側沿著該第一方向及該第二方向彼此平行,且其中該第二作用層側係面向、電耦接及實體地耦接至該第一作用層側,且在該第二作用層側處之該第二層包括一第一穿模通孔及一第二穿模通孔,其中該第一穿模通孔係在一穿矽通孔上,該穿矽通孔從第二作用側延伸 至該等第二組件中之至少一者內的第二非作用側;其中該第二穿模通孔係位在該等第二組件中之二者之間,並延伸至該第一作用層側;且其中該第一穿模通孔及該第二穿模通孔中之至少一中心部分係用一非導電材料所填充。
- 如請求項1之封裝總成,其進一步包含附接至該第二非作用側且附接以電耦接至該第二作用側之一平面柵格陣列或一球腳柵格陣列。
- 如請求項1之封裝總成,其中該第二作用層側係經由焊料或黏著劑與該第一作用層側實體地耦接。
- 如請求項1之封裝總成,其中該等二或多個第一組件中之一者在該第一方向上之長度係大於該等二或多個第二組件中之一者在該第一方向上之長度。
- 如請求項1之封裝總成,其進一步包含在該穿矽通孔中之一導體,用以電耦接至該第二非作用層側。
- 一種具有一封裝總成之系統,該系統包含:一電路板;如請求項1~5項中任一項之一封裝總成,其中該封裝總成係與該電路板耦接。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/US2015/041618 WO2017014777A1 (en) | 2015-07-22 | 2015-07-22 | Multi-layer package |
WOPCT/US15/41618 | 2015-07-22 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201705401A TW201705401A (zh) | 2017-02-01 |
TWI701778B true TWI701778B (zh) | 2020-08-11 |
Family
ID=57834333
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105117038A TWI701778B (zh) | 2015-07-22 | 2016-05-31 | 多層封裝總成及具有多層封裝總成之系統 |
Country Status (7)
Country | Link |
---|---|
US (1) | US10535634B2 (zh) |
EP (1) | EP3326201A4 (zh) |
JP (1) | JP2018525807A (zh) |
KR (1) | KR102505189B1 (zh) |
CN (1) | CN107743652A (zh) |
TW (1) | TWI701778B (zh) |
WO (1) | WO2017014777A1 (zh) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI649856B (zh) * | 2016-05-13 | 2019-02-01 | 精材科技股份有限公司 | 晶片封裝體與其製造方法 |
WO2018155195A1 (ja) * | 2017-02-22 | 2018-08-30 | ソニーセミコンダクタソリューションズ株式会社 | 撮像装置、電子機器、及び、撮像装置の製造方法 |
CN108322863B (zh) * | 2018-02-01 | 2020-05-22 | 南京信息工程大学 | 一种喇叭底盘材料、散热式车用喇叭 |
US11735570B2 (en) * | 2018-04-04 | 2023-08-22 | Intel Corporation | Fan out packaging pop mechanical attach method |
US11023247B2 (en) * | 2018-06-29 | 2021-06-01 | Intel Corporation | Processor package with optimization based on package connection type |
CN109345963B (zh) * | 2018-10-12 | 2020-12-18 | 芯光科技新加坡有限公司 | 一种显示装置及其封装方法 |
CN111627941B (zh) * | 2019-02-27 | 2023-04-18 | 中芯集成电路(宁波)有限公司 | Cmos图像传感器封装模块及其形成方法、摄像装置 |
US11309246B2 (en) * | 2020-02-05 | 2022-04-19 | Apple Inc. | High density 3D interconnect configuration |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201005063A (en) * | 2008-06-02 | 2010-02-01 | 3M Innovative Properties Co | Adhesive encapsulating composition and electronic devices made therewith |
US20110278733A1 (en) * | 2010-05-17 | 2011-11-17 | Stmicroelectronics (Grenoble 2) Sas | Process for fabricating semiconductor devices and a semiconductor device comprising a chip with through-vias |
US8247269B1 (en) * | 2011-06-29 | 2012-08-21 | Fairchild Semiconductor Corporation | Wafer level embedded and stacked die power system-in-package packages |
US20140015131A1 (en) * | 2012-07-13 | 2014-01-16 | Intel Mobile Communications GmbH | Stacked fan-out semiconductor chip |
TWM499645U (zh) * | 2014-11-25 | 2015-04-21 | Xerogel Technology | 整合式被動模組及半導體裝置 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003243604A (ja) | 2002-02-13 | 2003-08-29 | Sony Corp | 電子部品及び電子部品の製造方法 |
US20050275750A1 (en) * | 2004-06-09 | 2005-12-15 | Salman Akram | Wafer-level packaged microelectronic imagers and processes for wafer-level packaging |
US7807505B2 (en) * | 2005-08-30 | 2010-10-05 | Micron Technology, Inc. | Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods |
US20080136004A1 (en) * | 2006-12-08 | 2008-06-12 | Advanced Chip Engineering Technology Inc. | Multi-chip package structure and method of forming the same |
US20080157316A1 (en) * | 2007-01-03 | 2008-07-03 | Advanced Chip Engineering Technology Inc. | Multi-chips package and method of forming the same |
US7858441B2 (en) * | 2008-12-08 | 2010-12-28 | Stats Chippac, Ltd. | Semiconductor package with semiconductor core structure and method of forming same |
US8604603B2 (en) * | 2009-02-20 | 2013-12-10 | The Hong Kong University Of Science And Technology | Apparatus having thermal-enhanced and cost-effective 3D IC integration structure with through silicon via interposers |
US8115260B2 (en) * | 2010-01-06 | 2012-02-14 | Fairchild Semiconductor Corporation | Wafer level stack die package |
US9245773B2 (en) | 2011-09-02 | 2016-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device packaging methods and structures thereof |
US9281292B2 (en) * | 2012-06-25 | 2016-03-08 | Intel Corporation | Single layer low cost wafer level packaging for SFF SiP |
US8970023B2 (en) * | 2013-02-04 | 2015-03-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and methods of forming same |
US9659907B2 (en) * | 2015-04-07 | 2017-05-23 | Apple Inc. | Double side mounting memory integration in thin low warpage fanout package |
-
2015
- 2015-07-22 KR KR1020187004770A patent/KR102505189B1/ko active IP Right Grant
- 2015-07-22 WO PCT/US2015/041618 patent/WO2017014777A1/en active Application Filing
- 2015-07-22 JP JP2017553208A patent/JP2018525807A/ja active Pending
- 2015-07-22 CN CN201580081135.8A patent/CN107743652A/zh active Pending
- 2015-07-22 EP EP15899090.3A patent/EP3326201A4/en active Pending
- 2015-07-22 US US15/106,761 patent/US10535634B2/en active Active
-
2016
- 2016-05-31 TW TW105117038A patent/TWI701778B/zh active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201005063A (en) * | 2008-06-02 | 2010-02-01 | 3M Innovative Properties Co | Adhesive encapsulating composition and electronic devices made therewith |
US20110278733A1 (en) * | 2010-05-17 | 2011-11-17 | Stmicroelectronics (Grenoble 2) Sas | Process for fabricating semiconductor devices and a semiconductor device comprising a chip with through-vias |
US8247269B1 (en) * | 2011-06-29 | 2012-08-21 | Fairchild Semiconductor Corporation | Wafer level embedded and stacked die power system-in-package packages |
US20140015131A1 (en) * | 2012-07-13 | 2014-01-16 | Intel Mobile Communications GmbH | Stacked fan-out semiconductor chip |
TWM499645U (zh) * | 2014-11-25 | 2015-04-21 | Xerogel Technology | 整合式被動模組及半導體裝置 |
Also Published As
Publication number | Publication date |
---|---|
EP3326201A4 (en) | 2019-03-20 |
CN107743652A (zh) | 2018-02-27 |
KR20180034498A (ko) | 2018-04-04 |
EP3326201A1 (en) | 2018-05-30 |
JP2018525807A (ja) | 2018-09-06 |
US10535634B2 (en) | 2020-01-14 |
TW201705401A (zh) | 2017-02-01 |
US20170207170A1 (en) | 2017-07-20 |
KR102505189B1 (ko) | 2023-03-02 |
WO2017014777A1 (en) | 2017-01-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI701778B (zh) | 多層封裝總成及具有多層封裝總成之系統 | |
US10522483B2 (en) | Package assembly for embedded die and associated techniques and configurations | |
US20230023328A1 (en) | Integrated circuit package having wirebonded multi-die stack | |
US10068852B2 (en) | Integrated circuit package with embedded bridge | |
KR101862496B1 (ko) | 패키지 몸체 내에 배치된 수동 마이크로 전자 디바이스를 갖는 마이크로 전자 패키지, 그 제조 방법 및 그를 포함하는 컴퓨팅 디바이스 | |
US10037976B2 (en) | Scalable package architecture and associated techniques and configurations | |
JP2017535054A (ja) | 裏面受動構成要素を有する集積回路ダイ、およびそれに関連する方法 | |
US9412625B2 (en) | Molded insulator in package assembly | |
TWI636515B (zh) | 扇出型半導體封裝以及製造扇出型半導體封裝的方法 | |
JP6092271B2 (ja) | 集積回路パッケージ | |
US10643983B2 (en) | Extended stiffener for platform miniaturization | |
US20230197547A1 (en) | Edge-aligned template structure for integrated circuit packages | |
US20230197546A1 (en) | Edge-aligned template structure for integrated circuit packages |