TWI692226B - Transmitter circuit, semiconductor apparatus and data transmission method - Google Patents

Transmitter circuit, semiconductor apparatus and data transmission method Download PDF

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TWI692226B
TWI692226B TW105105641A TW105105641A TWI692226B TW I692226 B TWI692226 B TW I692226B TW 105105641 A TW105105641 A TW 105105641A TW 105105641 A TW105105641 A TW 105105641A TW I692226 B TWI692226 B TW I692226B
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output
circuit
signal
pulse
stop
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TW105105641A
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TW201705730A (en
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武田晃一
長瀬寛和
渡部真平
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日商瑞薩電子股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/19—Monitoring patterns of pulse trains
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Dc Digital Transmission (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Logic Circuits (AREA)

Abstract

The transmitter circuit according to one embodiment includes a pulse generating circuit generating a pulse signal based on edges of input data, a first output driver outputting, based on the pulse signal, a first output pulse signal according to one of the edges to a first end of an external insulating coupling element, a second output driver outputting, based on the pulse signal, a second output pulse signal according to other one of the edges to a second end of the insulating coupling element, and an output stop circuit stopping the first and second output pulse signals from being output for a prescribed period from when a power supply voltage is turned on.

Description

發射器電路、半導體裝置及資料傳輸方法 Transmitter circuit, semiconductor device and data transmission method

本發明係有關發射器電路、半導體裝置及資料傳輸方法。 The invention relates to a transmitter circuit, a semiconductor device and a data transmission method.

在彼此之電源電壓不同的多個半導體晶片之間做訊號交換的情況中，該等半導體晶片必須與絕緣耦合元件在交換訊號上互相電絕緣。已知的絕緣耦合元件包含使用電容器、線圈等等的AC耦合元件和光耦合元件(光耦合器)。日本未經審查的專利申請公開案第2013-229812號揭示一種半導體裝置，其使用線圈做為絕緣耦合元件(亦即，所謂的微隔離器)來交換訊號的半導體裝置。 In the case of signal exchange between a plurality of semiconductor chips having different power supply voltages, the semiconductor chips and the insulating coupling element must be electrically insulated from each other on the exchange signal. Known insulating coupling elements include AC coupling elements and optical coupling elements (optical couplers) using capacitors, coils, and the like. Japanese Unexamined Patent Application Publication No. 2013-229812 discloses a semiconductor device that uses a coil as an insulating coupling element (that is, a so-called micro-isolator) to exchange signals.

在日本未經審查的專利申請公開案第2013-229812號之揭示中，由資料訊號的邊緣所觸發的脈波訊號係發射自發射器電路。在此，從該發射器電路能夠區別於資料訊號的上升邊緣與下降邊緣之間的脈波訊號被發射出。因此，該資料訊號能夠被重建於接收器電路處。 In the disclosure of Japanese Unexamined Patent Application Publication No. 2013-229812, the pulse wave signal triggered by the edge of the data signal is transmitted from the transmitter circuit. Here, the pulse signal that can be distinguished from the rising edge and the falling edge of the data signal from the transmitter circuit is transmitted. Therefore, the data signal can be reconstructed at the receiver circuit.

同時，日本未經審查的專利申請公開案第2005-045100和2012-253241號以及日本專利案第4750746號各自揭示設置於電源與接地之間的靜電放電保護電路，該靜電放電保護電路被安裝用來保護半導體裝置的內部電路免於由靜電放電所產生的高電壓脈波。在日本未經審查的專利申請公開案第2005-045100和2012-253241號中所揭示之靜電放電保護電路當感測到電源上的急遽增加時，就開啟NMOS電晶體。在日本專利案第4750746號中所揭示之靜電放電保護電路(GGNMOS：閘極接地的NMOS)當到達某位準的電源電位時，才開啟NMOS電晶體的寄生雙載子。藉由前述的操作，各個靜電放電保護電路在電源電位到達內部電路的擊穿電壓之前操作。因而，電源電壓的增加被抑制，並且內部電路受到保護。 Meanwhile, Japanese Unexamined Patent Application Publication Nos. 2005-045100 and 2012-253241 and Japanese Patent No. 4750746 each disclose an electrostatic discharge protection circuit provided between the power supply and the ground, the electrostatic discharge protection circuit being installed for To protect the internal circuit of the semiconductor device from the high voltage pulse generated by electrostatic discharge. The electrostatic discharge protection circuits disclosed in Japanese Unexamined Patent Application Publication Nos. 2005-045100 and 2012-253241 turn on NMOS transistors when they sense a sudden increase in the power supply. The electrostatic discharge protection circuit (GGNMOS: gate-grounded NMOS) disclosed in Japanese Patent No. 4750746 only turns on the parasitic double carriers of the NMOS transistor when it reaches a certain level of power supply potential. Through the aforementioned operation, each ESD protection circuit operates before the power supply potential reaches the breakdown voltage of the internal circuit. Thus, the increase in the power supply voltage is suppressed, and the internal circuit is protected.

本案發明人已經發現下面的問題。 The inventor of the present case has discovered the following problems.

舉例來說，已經發現到，當用諸如在日本未經審查的專利申請公開案第2013-229812號中所揭示之微隔離器來實施為靜電放電損壞測試的其中一種之人體放電模式(HBM)時，諸如發射器電路的擊穿或絕緣耦合元件的毀壞之失效可能會發生。已經發現到，浪湧電流的施加致使電源電壓超過規定電壓，而且發射器電路輸出錯誤的脈波，其最終招致前述的失效。 For example, it has been found that when a micro-isolator such as disclosed in Japanese Unexamined Patent Application Publication No. 2013-229812 is used to implement one of the human body discharge modes (HBM) for electrostatic discharge damage testing At times, failures such as breakdown of the transmitter circuit or destruction of the insulating coupling element may occur. It has been found that the application of inrush current causes the power supply voltage to exceed the specified voltage, and the transmitter circuit outputs an erroneous pulse wave, which eventually leads to the aforementioned failure.

高速可操作性、低功率耗損、小面積占用率、及雜訊 免疫力為微隔離器的性能指標，其中一種改善它們的方案為致使大電流在短時間期間內從發射器電路流到為絕緣耦合元件的變壓器。舉例來說，在日本未經審查的專利申請公開案第2013-229812號中所揭示之微隔離器中的發射器電路係由輸出短脈波的脈波產生單元和具有高驅動性能的輸出驅動器單元所建構成。另一方面，脈波產生單元係與一問題相關聯，該問題為立即在電源被開啟之後，建構該脈波產生單元之延遲元件中的內部端子的狀態就不穩定，且藉此，該脈波產生單元易於輸出錯誤的脈波。此外，輸出驅動器單元被設計成在正常下以規定電壓(例如，5V)，舉例來說，100mA的電流流過變壓器。在此，該輸出驅動器單元係與一問題相關聯，該問題為當大大地高於規定電壓的電源電壓被施加時，大於可允許值的電流當操時流過該驅動器或變壓器。 High-speed operability, low power consumption, small area occupancy, and noise Immunity is a performance index of micro-isolators, and one of the solutions to improve them is to cause a large current to flow from the transmitter circuit to the transformer which is an insulating coupling element within a short period of time. For example, the transmitter circuit in the micro-isolator disclosed in Japanese Unexamined Patent Application Publication No. 2013-229812 is composed of a pulse wave generating unit that outputs a short pulse wave and an output driver with high driving performance Built by the unit. On the other hand, the pulse wave generating unit is associated with a problem that immediately after the power is turned on, the state of the internal terminal in the delay element constructing the pulse wave generating unit is unstable, and by this, the pulse The wave generating unit is prone to output erroneous pulse waves. In addition, the output driver unit is designed to normally flow a transformer with a prescribed voltage (for example, 5V), for example, a current of 100 mA. Here, the output driver unit is associated with a problem that when a power supply voltage much higher than a prescribed voltage is applied, a current larger than an allowable value flows through the driver or transformer when it is operated.

儘管組成元件係分別與問題相關聯，但是通常兩個問題不會同時發生，因而不致造成挑戰。然而，當HBM測試被實施於電源與接地之間時，進入電源被開啟於大大地高於規定電壓(例如，十幾(ten-odd)V)的電壓之狀態。然後，在脈波產生單元產生錯誤的脈波期間，大於可允許值(例如，幾百mA)的電流流過該驅動器或變壓器，其導致諸如發射器電路的擊穿或絕緣耦合元件的毀壞之失效。 Although the component elements are individually associated with the problem, usually the two problems do not occur at the same time, so they do not pose challenges. However, when the HBM test is performed between the power supply and the ground, the state where the power supply is turned on at a voltage much higher than a prescribed voltage (for example, ten-odd V) is entered. Then, during the generation of an erroneous pulse wave by the pulse wave generating unit, a current larger than the allowable value (for example, several hundred mA) flows through the driver or transformer, which causes breakdown of the transmitter circuit or destruction of the insulating coupling element Failure.

有了日本未經審查的專利申請公開案第2005-045100和2012-253241號以及日本專利案第4750746號中所揭示 之靜電放電保護電路，儘管歸因於浪湧電流的施加之電源電壓的增加可以被抑制而低於擊穿電壓(例如，十幾(ten-odd)V)，但是難以抑制浪湧電流到約為規定電壓(例如，5V)。此外，無法防止建構發射器電路的該脈波產生單元輸出錯誤的脈波。因此，結果是，高於規定電壓的供應電壓藉由該等錯誤的脈波而被傳送至驅動器和變壓器，其導致如上所述之失效。 There are Japanese Unexamined Patent Application Publication Nos. 2005-045100 and 2012-253241 and Japanese Patent No. 4750746 The electrostatic discharge protection circuit, although the increase of the power supply voltage due to the application of the surge current can be suppressed to be lower than the breakdown voltage (for example, ten-odd V), it is difficult to suppress the surge current to about It is a specified voltage (for example, 5V). In addition, it cannot be prevented that the pulse wave generating unit constructing the transmitter circuit outputs an erroneous pulse wave. Therefore, as a result, the supply voltage higher than the prescribed voltage is transmitted to the driver and the transformer by these erroneous pulse waves, which causes the failure as described above.

如上所述，習知的靜電放電保護電路無法有效地抑制靜電放電損壞測試時的失效。 As described above, the conventional electrostatic discharge protection circuit cannot effectively suppress the failure during the electrostatic discharge damage test.

其他的問題及新穎的特徵將從說明書的敘述及附圖而變得顯而易知。 Other problems and novel features will become apparent from the description of the specification and the drawings.

依據一個實施例之發射器電路包含輸出停止電路，其使第一及第二輸出脈波訊號的輸出從當電源電壓被開啟時開始持續一段預定期間。 The transmitter circuit according to one embodiment includes an output stop circuit that enables the output of the first and second output pulse signals to continue for a predetermined period from when the power supply voltage is turned on.

依據一個實施例，靜電放電損壞測試的失效能夠被抑制。 According to one embodiment, the failure of the electrostatic discharge damage test can be suppressed.

TX1、TX2‧‧‧發射器電路 TX1, TX2 ‧‧‧ transmitter circuit

L11、L21‧‧‧主要線圈 L11, L21‧‧‧Main coil

L12、L22‧‧‧次要線圈 L12, L22 ‧‧‧ secondary coil

RX1、RX2‧‧‧接收器電路 RX1, RX2 ‧‧‧ receiver circuit

CHP1、CHP2‧‧‧半導體晶片 CHP1, CHP2 ‧‧‧ semiconductor chip

VDD1、VDD2‧‧‧電源電壓 VDD1, VDD2 ‧‧‧ power supply voltage

GND、GND1、GND2‧‧‧接地電壓 GND, GND1, GND2‧‧‧Ground voltage

PKG‧‧‧半導體封裝組件 PKG‧‧‧Semiconductor package

Pd‧‧‧墊塊 Pd‧‧‧Cushion block

BW‧‧‧接合線 BW‧‧‧bond wire

T‧‧‧引線端子(外部端子) T‧‧‧Lead terminal (external terminal)

1‧‧‧半導體裝置 1‧‧‧Semiconductor device

PGC‧‧‧脈波產生電路 PGC‧‧‧Pulse Wave Generation Circuit

OD1、OD2‧‧‧輸出驅動器 OD1, OD2‧‧‧ output driver

10‧‧‧輸出停止電路 10‧‧‧Output stop circuit

P10‧‧‧脈波訊號 P10‧‧‧Pulse signal

P11、P12‧‧‧輸出脈波訊號 P11, P12‧‧‧Output pulse signal

Din1‧‧‧輸入資料訊號 Din1‧‧‧Input data signal

VR‧‧‧接收訊號 VR‧‧‧Receive signal

IN10、IN11、IN12、IN21、IN22‧‧‧反相器 IN10, IN11, IN12, IN21, IN22 ‧‧‧ inverter

RED1、RED2‧‧‧上升邊緣偵測電路 RED1, RED2 ‧‧‧ rising edge detection circuit

OR1、OR2‧‧‧或閘 OR1, OR2‧‧‧or gate

DC1、DC2‧‧‧延遲電路 DC1, DC2‧‧‧ Delay circuit

AN1、AN2、AN11、AN12、AN21、AN22‧‧‧及閘 AN1, AN2, AN11, AN12, AN21, AN22‧‧‧ and gate

B1、B2‧‧‧緩衝器電路 B1, B2 ‧‧‧ buffer circuit

EP1、EP2‧‧‧邊緣脈波訊號 EP1, EP2‧‧‧Edge pulse signal

DB‧‧‧經反相的資料訊號 DB‧‧‧Inverted data signal

DD‧‧‧正常之經延遲的資料訊號 DD‧‧‧Normal delayed data signal

STP‧‧‧停止訊號 STP‧‧‧Stop signal

DDB‧‧‧經反相之經延遲的資料訊號 DDB‧‧‧Inverted delayed data signal

PDC‧‧‧脈波偵測電路 PDC‧‧‧Pulse wave detection circuit

PWC1、PWC2‧‧‧脈波加寬電路 PWC1, PWC2 ‧‧‧ Pulse broadening circuit

SLC‧‧‧序向邏輯電路 SLC‧‧‧Sequential logic circuit

PPD1、PPD2‧‧‧正脈波偵測電路 PPD1, PPD2 ‧‧‧ positive pulse wave detection circuit

NPD1、NPD2‧‧‧負脈波偵測電路 NPD1, NPD2 ‧‧‧ Negative pulse wave detection circuit

Dout1‧‧‧輸出資料訊號 Dout1‧‧‧Output data signal

TX10‧‧‧發射器電路 TX10‧‧‧Transmitter circuit

R1‧‧‧電阻器元件 R1‧‧‧resistor element

C1、C2、C11、C12、C21、C22‧‧‧電容器元件 C1, C2, C11, C12, C21, C22

N1、N2‧‧‧輸入 N1, N2‧‧‧ input

20‧‧‧輸出停止電路 20‧‧‧Output stop circuit

NM1‧‧‧NMOS電晶體 NM1‧‧‧NMOS transistor

PM1‧‧‧PMOS電晶體 PM1‧‧‧PMOS transistor

N2‧‧‧閘極 N2‧‧‧Gate

30‧‧‧輸出停止電路 30‧‧‧Output stop circuit

ND‧‧‧非及閘 ND‧‧‧Not the gate

CTR1、CTR2‧‧‧計數器 CTR1, CTR2 ‧‧‧ counter

N1、N2‧‧‧儲存節點 N1, N2‧‧‧ storage node

RT12、RT22‧‧‧規律的請求訊號 RT12, RT22 ‧‧‧ regular request signal

2‧‧‧半導體裝置系統 2‧‧‧Semiconductor device system

OSC1、OSC2‧‧‧振盪器電路 OSC1, OSC2 ‧‧‧ oscillator circuit

TM1、TM2‧‧‧計時器 TM1, TM2 ‧‧‧ timer

UVLO1、UVLO2‧‧‧欠電壓鎖定(UVLO)電路 UVLO1, UVLO2‧‧‧ Undervoltage lockout (UVLO) circuit

A1、A2‧‧‧及閘 A1, A2‧‧‧ and gate

O1 to O6‧‧‧或閘 O1 to O6‧‧‧or gate

TO1、TO2‧‧‧逾時訊號 TO1, TO2‧‧‧ Overtime signal

PTD‧‧‧功率電晶體驅動器 PTD‧‧‧Power Transistor Driver

EDC‧‧‧錯誤偵測電路 EDC‧‧‧Error detection circuit

RT11、RT21‧‧‧非規律的請求訊號 RT11, RT21 ‧‧‧ Irregular request signal

RST1、RST2、RST3‧‧‧重設訊號 RST1, RST2, RST3 ‧‧‧ reset signal

上述以及其他的態樣、優點及特徵將從下面配合附圖所提出之某些實施例的說明而變得更加顯而易知，在附圖中：圖1係顯示依據第一實施例之半導體裝置結構的方塊圖；圖2係顯示依據第一實施例之半導體裝置的安裝實例 的圖形；圖3係顯示依據第一實施例之發射器電路TX1之特定電路結構實例的電路圖；圖4係顯示依據第一實施例之發射器電路TX1操作的一個實例之時序圖表；圖5係顯示依據第一實施例之接收器電路RX1之特定電路結構實例的電路圖；圖6係顯示依據第一實施例之接收器電路RX1操作的一個實例之時序圖表；圖7係顯示依據第一實施例之比較實例之發射器電路TX10之特定電路結構的一個實例的電路圖；圖8係用以說明依據比較實例在用發射器電路TX10之HBM測試時失效發生之機制的時序圖表；圖9係用以說明在用發射器電路TX1之HBM測試抑制失效之機制的時序圖表；圖10係顯示依據第一實施例之輸出停止電路10之特定電路結構的一個實例的電路圖；圖11係用以說明當電源電壓被開啟時，依據第一實施例之輸出停止電路10之操作的時序圖表；圖12係顯示依據第一實施例之發射器電路TX1之變型的電路圖；圖13係顯示依據第一實施例之發射器電路TX1之變型的電路圖；圖14係顯示依據第一實施例之脈波產生電路PGC之 變型的電路圖；圖15係顯示依據第二實施例之輸出停止電路20之特定電路結構的一個實例的電路圖；圖16係用以說明當電源電壓被開啟時，依據第二實施例之輸出停止電路20之操作的時序圖表；圖17係顯示依據第三實施例之輸出停止電路30之特定電路結構的一個實例的電路圖；圖18係用以說明當電源電壓被開啟時，依據第三實施例之輸出停止電路30之操作的時序圖表；圖19係顯示依據第三實施例之半導體裝置系統2之結構的方塊圖；圖20係顯示應用有半導體裝置系統2之反相器裝置的圖形；圖21係顯示應用有半導體裝置系統2之反相器裝置之操作的時序圖表；圖22係在電容器被用作為絕緣耦合元件的情況中之半導體裝置的安裝實例；以及圖23係在GMR元件被用作為絕緣耦合元件的情況中之半導體裝置的安裝實例。 The above and other aspects, advantages and features will become more obvious and easy to understand from the following description of some embodiments proposed in conjunction with the drawings. In the drawings: FIG. 1 shows a semiconductor according to the first embodiment Block diagram of the device structure; FIG. 2 shows an installation example of the semiconductor device according to the first embodiment 3 is a circuit diagram showing an example of a specific circuit structure of the transmitter circuit TX1 according to the first embodiment; FIG. 4 is a timing chart showing an example of the operation of the transmitter circuit TX1 according to the first embodiment; FIG. 5 is A circuit diagram showing a specific circuit configuration example of the receiver circuit RX1 according to the first embodiment; FIG. 6 is a timing chart showing an example of the operation of the receiver circuit RX1 according to the first embodiment; FIG. 7 is a display according to the first embodiment A circuit diagram of an example of a specific circuit structure of the transmitter circuit TX10 of the comparative example; FIG. 8 is a timing chart illustrating a mechanism of failure occurrence when the HBM test of the transmitter circuit TX10 is used according to the comparative example; FIG. 9 is used to Timing chart illustrating the mechanism of suppressing failure of the HBM test of the transmitter circuit TX1 in use; FIG. 10 is a circuit diagram showing an example of a specific circuit structure of the output stop circuit 10 according to the first embodiment; FIG. 11 is used to illustrate the power supply When the voltage is turned on, a timing chart of the operation of the output stop circuit 10 according to the first embodiment; FIG. 12 is a circuit diagram showing a modification of the transmitter circuit TX1 according to the first embodiment; FIG. 13 is a circuit diagram according to the first embodiment A circuit diagram of a modification of the transmitter circuit TX1; FIG. 14 shows a pulse wave generating circuit PGC according to the first embodiment. A modified circuit diagram; FIG. 15 is a circuit diagram showing an example of a specific circuit structure of the output stop circuit 20 according to the second embodiment; FIG. 16 is used to explain the output stop circuit according to the second embodiment when the power supply voltage is turned on 20 is a timing chart of the operation; FIG. 17 is a circuit diagram showing an example of a specific circuit structure of the output stop circuit 30 according to the third embodiment; FIG. 18 is used to explain when the power supply voltage is turned on, according to the third embodiment. A timing chart of the operation of the output stop circuit 30; FIG. 19 is a block diagram showing the structure of the semiconductor device system 2 according to the third embodiment; FIG. 20 is a diagram showing an inverter device to which the semiconductor device system 2 is applied; FIG. 21 Is a timing chart showing the operation of the inverter device to which the semiconductor device system 2 is applied; FIG. 22 is a mounting example of a semiconductor device in the case where a capacitor is used as an insulating coupling element; and FIG. 23 is used as a GMR element An installation example of a semiconductor device in the case of an insulating coupling element.

下面將參照附圖來詳細說明特定的實施例。注意，為了清楚地說明起見，下面所提及的說明及附圖被適當地省略或簡化。此外，在附圖中被顯示為實施各種製程之功能 方塊的元件能夠藉由中央處理單元(CPU)、記憶體、其他電路而被實施為硬體，並且可以藉由載入於記憶體等等中之程式而被實現為軟體。因此，習於此技藝者瞭解到這些功能方塊能夠以各種方式來予以實現，諸如單獨由硬體、單獨由軟體、或者藉由其組合，而且本發明並不限於它們的其中一者。注意，在附圖中，相同的參考符號被分配給相同的元件，並且重複的說明視需要而予以省略。 The specific embodiments will be described in detail below with reference to the drawings. Note that, for clarity of explanation, the description and drawings mentioned below are appropriately omitted or simplified. In addition, it is shown in the drawings as a function of implementing various processes The elements of the block can be implemented as hardware by a central processing unit (CPU), memory, and other circuits, and can be implemented as software by a program loaded in memory or the like. Therefore, those skilled in the art understand that these functional blocks can be implemented in various ways, such as hardware alone, software alone, or combinations thereof, and the present invention is not limited to one of them. Note that in the drawings, the same reference symbols are assigned to the same elements, and repeated descriptions are omitted as necessary.

(第一實施例) (First embodiment) <半導體裝置1的結構> <Structure of Semiconductor Device 1>

首先，參照圖1，將說明依據第一實施例的半導體裝置。圖1為顯示依據第一實施例之半導體裝置1結構的方塊圖，依據第一實施例的半導體裝置包含發射器電路TX1、主要線圈L11、次要線圈L12、及接收器電路RX1，以及微隔離器的結構。 First, referring to FIG. 1, a semiconductor device according to the first embodiment will be explained. 1 is a block diagram showing the structure of a semiconductor device 1 according to a first embodiment. The semiconductor device according to the first embodiment includes a transmitter circuit TX1, a primary coil L11, a secondary coil L12, and a receiver circuit RX1, and micro isolation The structure of the device.

發射器電路TX1係形成於半導體晶片CHP1處。注意，半導體晶片CHP1係由屬於第一電源系統的第一電源(電源電壓VDD1、接地電壓GND1、電位差VDD1-GND1為，舉例來說，5V)來予以驅動。 The transmitter circuit TX1 is formed at the semiconductor wafer CHP1. Note that the semiconductor chip CHP1 is driven by a first power supply (power supply voltage VDD1, ground voltage GND1, potential difference VDD1-GND1, for example, 5V) belonging to the first power supply system.

主要線圈L11、次要線圈L12、及接收器電路RX1係形成於半導體晶片CHP2處。注意，半導體晶片CHP2係由屬於與該第一電源系統不同之第二電源系統的第二電源(電源電壓VDD2、接地電壓GND2、電位差VDD2-GND2為，舉例來說，5V)來予以驅動。 The primary coil L11, the secondary coil L12, and the receiver circuit RX1 are formed at the semiconductor chip CHP2. Note that the semiconductor chip CHP2 is driven by a second power supply (power supply voltage VDD2, ground voltage GND2, potential difference VDD2-GND2, for example, 5V) belonging to a second power supply system different from the first power supply system.

主要線圈L11和次要線圈L12建構絕緣耦合元件，該等絕緣耦合元件經由磁場或電場而使其電源電壓彼此不同的兩個半導體晶片CHP1,CHP2耦合，且同時使該等半導體晶片CHP1,CHP2互相電絕緣。藉由該等絕緣耦合元件，資料訊號能夠從半導體晶片CHP1上的發射器電路TX1發送至具有不同電源電壓(電位差VDD1-VDD2為，舉例來說，負幾百V至幾百V)之半導體晶片CHP2上的接收器電路RX1。 The primary coil L11 and the secondary coil L12 constitute an insulating coupling element that couples two semiconductor chips CHP1, CHP2 whose power supply voltages are different from each other through a magnetic field or an electric field, and simultaneously makes the semiconductor chips CHP1, CHP2 mutually Electrical insulation. With these insulating coupling elements, data signals can be sent from the transmitter circuit TX1 on the semiconductor chip CHP1 to semiconductor chips with different power supply voltages (potential difference VDD1-VDD2 is, for example, negative hundreds to hundreds of V) The receiver circuit RX1 on CHP2.

在此，參照圖2，將說明半導體裝置1的安裝實例。圖2為顯示半導體裝置1的安裝實例之圖形。注意，圖2主要用來解釋發射器電路TX1、接收器電路RX1、設置在發射器電路TX1與接收器電路RX1之間的主要線圈L11和次要線圈L12的安裝實例。 Here, referring to FIG. 2, a mounting example of the semiconductor device 1 will be explained. FIG. 2 is a diagram showing an installation example of the semiconductor device 1. Note that FIG. 2 is mainly used to explain an installation example of the transmitter circuit TX1, the receiver circuit RX1, and the primary coil L11 and the secondary coil L12 provided between the transmitter circuit TX1 and the receiver circuit RX1.

在圖2所示的安裝實例中，兩個半導體晶片CHP1,CHP2被安裝在半導體封裝組件PKG上，該等半導體晶片CHP1,CHP2各自具有墊塊Pd。然後，該等半導體晶片CHP1,CHP2的該等墊塊Pd經由未顯示出之接合導線而被連接至設置在該半導體封裝組件PKG上的多個引線端子(外部端子)T。 In the mounting example shown in FIG. 2, two semiconductor wafers CHP1, CHP2 are mounted on a semiconductor package PKG, and the semiconductor wafers CHP1, CHP2 each have a pad Pd. Then, the pads Pd of the semiconductor chips CHP1, CHP2 are connected to a plurality of lead terminals (external terminals) T provided on the semiconductor package PKG via bonding wires not shown.

如圖2所示，發射器電路TX1係形成在該半導體晶片CHP1處，在該半導體晶片CHP2處，接收器電路RX1、主要線圈L11、及次要線圈L12被形成。此外，在該半導體晶片CHP1處，連接至發射器電路TX1之輸出的墊塊Pd被形成。在該半導體晶片CHP2處，分別連接至 主要線圈L11之相對端的墊塊Pd被形成。然後，該發射器電路TX1經由該等墊塊和接合導線BW而被連接至形成在該半導體晶片CHP2處的該主要線圈L11。 As shown in FIG. 2, the transmitter circuit TX1 is formed at the semiconductor wafer CHP1, and at the semiconductor wafer CHP2, the receiver circuit RX1, the primary coil L11, and the secondary coil L12 are formed. In addition, at the semiconductor wafer CHP1, a pad Pd connected to the output of the transmitter circuit TX1 is formed. At this semiconductor wafer CHP2, they are connected to The pad Pd at the opposite end of the main coil L11 is formed. Then, the transmitter circuit TX1 is connected to the main coil L11 formed at the semiconductor wafer CHP2 via the pads and the bonding wires BW.

注意，在圖2所示的實例中，主要線圈L11及次要線圈L12分別被形成在堆疊於其中一個半導體晶片CHP2中之頂部到底部(top-bottom)方向上的第一互連層及第二互連層。此外，主要線圈L11及次要線圈L12可以被形成在具有該發射器電路TX1的該半導體晶片CHP1處。或者，主要線圈L11及次要線圈L12可以被形成在形成於其中形成有該發射器電路TX1的該半導體晶片CHP1與其中形成有該接收器電路RX1的該半導體晶片CHP2之間的第三半導體晶片處。 Note that in the example shown in FIG. 2, the primary coil L11 and the secondary coil L12 are respectively formed in the top-bottom direction and the first interconnect layer stacked in one of the semiconductor wafers CHP2. Second interconnection layer. In addition, the primary coil L11 and the secondary coil L12 may be formed at the semiconductor wafer CHP1 having the transmitter circuit TX1. Alternatively, the primary coil L11 and the secondary coil L12 may be formed on a third semiconductor wafer formed between the semiconductor wafer CHP1 in which the transmitter circuit TX1 is formed and the semiconductor wafer CHP2 in which the receiver circuit RX1 is formed Office.

此外，主要線圈L11及發射器電路TX1可以被形成在該半導體晶片CHP1處，並且次要線圈L12及接收器電路RX1可以被形成在該半導體晶片CHP2處。然後，該半導體晶片CHP1和該半導體晶片CHP2可以互相接合。 In addition, the primary coil L11 and the transmitter circuit TX1 may be formed at the semiconductor wafer CHP1, and the secondary coil L12 and the receiver circuit RX1 may be formed at the semiconductor wafer CHP2. Then, the semiconductor wafer CHP1 and the semiconductor wafer CHP2 may be bonded to each other.

或者，發射器電路TX1、接收器電路RX1、主要線圈L11、及次要線圈L12可以被形成在一個半導體晶片上。在此情況中，配置有該發射器電路TX1的區域和配置有該接收器電路RX1的區域係配置成藉由形成於該半導體晶片中的絕緣層而互相絕緣。 Alternatively, the transmitter circuit TX1, the receiver circuit RX1, the primary coil L11, and the secondary coil L12 may be formed on one semiconductor wafer. In this case, the region where the transmitter circuit TX1 is arranged and the region where the receiver circuit RX1 is arranged are configured to be insulated from each other by an insulating layer formed in the semiconductor wafer.

回到參照圖1，將說明半導體裝置1的代表性結構。發射器電路TX1基於屬於第一電源系統的第一電源而操作，另一方面，接收器電路RX1基於屬於第二電源系統 的第二電源而操作。 Referring back to FIG. 1, a representative structure of the semiconductor device 1 will be explained. The transmitter circuit TX1 operates based on the first power source belonging to the first power supply system, on the other hand, the receiver circuit RX1 is based on the second power supply system The second power supply.

該發射器電路TX1包含脈波產生電路PGC、輸出驅動器OD1,OD2、及輸出停止電路10。 The transmitter circuit TX1 includes a pulse wave generation circuit PGC, output drivers OD1, OD2, and an output stop circuit 10.

脈波產生電路PGC依據輸入資料訊號Din1的邊緣而產生脈波訊號P10。 The pulse wave generating circuit PGC generates the pulse wave signal P10 according to the edge of the input data signal Din1.

輸出驅動器OD1基於該脈波訊號P10而將輸出脈波訊號P11輸出到主要線圈L11的第一端，該輸出脈波訊號P11為用來發送該輸入資料訊號Din1的上升邊緣之脈波訊號。 The output driver OD1 outputs the output pulse signal P11 to the first end of the main coil L11 based on the pulse signal P10. The output pulse signal P11 is a pulse signal used to transmit the rising edge of the input data signal Din1.

輸出驅動器OD2基於該脈波訊號P10而將輸出脈波訊號P12輸出到主要線圈L11的第二端，該輸出脈波訊號P12為用來發送該輸入資料訊號Din1的下降邊緣之脈波訊號。 The output driver OD2 outputs the output pulse signal P12 to the second end of the main coil L11 based on the pulse signal P10. The output pulse signal P12 is a pulse signal for transmitting the falling edge of the input data signal Din1.

輸出停止電路10使該等輸出脈波訊號P11,P12的輸出停止一段從當電源電壓被開啟時開始的預定期間。在圖1的實例中，自輸出停止電路10輸出的停止訊號STP被輸入至輸出驅動器OD1,OD2。也就是說，藉由自輸出停止電路10輸出的停止訊號STP，來自輸出驅動器OD1,OD2之輸出脈波訊號P11,P12的輸出被停止。 The output stop circuit 10 stops the output of the output pulse signals P11, P12 for a predetermined period starting when the power supply voltage is turned on. In the example of FIG. 1, the stop signal STP output from the output stop circuit 10 is input to the output drivers OD1, OD2. That is, with the stop signal STP output from the output stop circuit 10, the output of the output pulse signals P11, P12 from the output drivers OD1, OD2 is stopped.

主要線圈L11及次要線圈L12使自該發射器電路TX1輸出的輸出脈波訊號P11,P12轉換成接收訊號VR，並且將該接收訊號VR發送至接收器電路RX1。明確地說，藉由輸出脈波訊號P11,P12的轉變(transition)，流經主要線圈L11的電流改變。據此，為跨於次要線圈L12之相 對端上的電壓之接收訊號VR改變。 The primary coil L11 and the secondary coil L12 convert the output pulse signals P11, P12 output from the transmitter circuit TX1 into a received signal VR, and send the received signal VR to the receiver circuit RX1. Specifically, by the transition of the output pulse signals P11, P12, the current flowing through the main coil L11 changes. Accordingly, the phase spanning the secondary coil L12 The received signal VR of the voltage on the opposite end changes.

接收器電路RX1基於次要線圈L12之接收訊號VR而重新建構該輸入資料訊號Din1，並且輸出該重新建構的訊號作為輸出資料訊號Dout1。 The receiver circuit RX1 reconstructs the input data signal Din1 based on the received signal VR of the secondary coil L12, and outputs the reconstructed signal as the output data signal Dout1.

依據第一實施例之該發射器電路TX1包含該輸出停止電路10，其使該輸出脈波訊號P11和該輸出脈波訊號P12的輸出停止一段從當電源電壓VDD1被開啟時開始的預定期間。因此，其使抑制與該電源電壓VDD1的開啟相關聯之錯誤脈波的輸出變成可能，在靜電放電損壞測試時該電源電壓VDD1上的增加為類似於該電源電壓VDD1的開啟之物理現象。因此，有了依據第一實施例之該發射器電路TX1，也在靜電放電損壞測試時，該輸出停止電路10啟動，並且歸因於與該電源電壓VDD1上的增加相關聯之錯誤脈波的任何失效能夠被抑制。 The transmitter circuit TX1 according to the first embodiment includes the output stop circuit 10, which stops the output of the output pulse signal P11 and the output pulse signal P12 for a predetermined period starting when the power supply voltage VDD1 is turned on. Therefore, it becomes possible to suppress the output of an erroneous pulse wave associated with the turning on of the power supply voltage VDD1, and the increase in the power supply voltage VDD1 during the electrostatic discharge damage test is a physical phenomenon similar to the turning on of the power supply voltage VDD1. Therefore, with the transmitter circuit TX1 according to the first embodiment, also during the electrostatic discharge damage test, the output stop circuit 10 is activated and is attributed to the error pulse associated with the increase in the power supply voltage VDD1 Any failure can be suppressed.

<發射器電路TX1的特定電路結構> <Specific circuit structure of transmitter circuit TX1>

接著，參照圖3，將說明發射器電路TX1的特定電路結構。下面所示的電路結構僅為例子。圖3為顯示依據第一實施例之發射器電路TX1的特定電路結構之實例的電路圖。如圖1及圖3所示，發射器電路TX1包含脈波產生電路PGC、輸出驅動器OD1,OD2、及輸出停止電路10。 Next, referring to FIG. 3, a specific circuit structure of the transmitter circuit TX1 will be explained. The circuit structure shown below is just an example. FIG. 3 is a circuit diagram showing an example of a specific circuit structure of the transmitter circuit TX1 according to the first embodiment. As shown in FIGS. 1 and 3, the transmitter circuit TX1 includes a pulse wave generation circuit PGC, output drivers OD1 and OD2, and an output stop circuit 10.

如圖3所示，脈波產生電路PGC包含一個反相器IN10、兩個上升邊緣偵測電路RED1,RED2、和一個或 (OR)閘OR1。在此，上升邊緣偵測電路RED1,RED2在電路結構上互相類似，上升邊緣偵測電路RED1包含延遲電路DC1、反相器IN11、和一個及(AND)閘AN11，上升邊緣偵測電路RED2包含延遲電路DC2、反相器IN12、、和一個及(AND)閘AN12。 As shown in FIG. 3, the pulse wave generation circuit PGC includes an inverter IN10, two rising edge detection circuits RED1, RED2, and one or (OR) gate OR1. Here, the rising edge detection circuits RED1 and RED2 are similar to each other in circuit structure. The rising edge detection circuit RED1 includes a delay circuit DC1, an inverter IN11, and an AND gate AN11, and the rising edge detection circuit RED2 includes The delay circuit DC2, the inverter IN12, and an AND gate AN12.

如圖3所示，輸出驅動器OD1,OD2實質上在電路結構方面係互相類似的。輸出驅動器OD1包含及(AND)閘AN1、緩衝器電路B1、和反相器IN1，輸出驅動器OD2包含及(AND)閘AN2、緩衝器電路B2、和反相器IN2。 As shown in FIG. 3, the output drivers OD1 and OD2 are substantially similar to each other in terms of circuit structure. The output driver OD1 includes an AND gate AN1, a buffer circuit B1, and an inverter IN1, and the output driver OD2 includes an AND gate AN2, a buffer circuit B2, and an inverter IN2.

注意，如圖3所示，介於輸出驅動器OD1,OD2之間的差異在於，在輸入資料訊號Din1被輸入至輸出驅動器OD1的同時，該輸入資料訊號Din1的反相訊號被輸入至輸出驅動器OD2。也就是說，及(AND)閘AN2包含在用於輸入資料訊號Din1之輸入端子處的反相器。 Note that as shown in FIG. 3, the difference between the output drivers OD1 and OD2 is that while the input data signal Din1 is input to the output driver OD1, the inverted signal of the input data signal Din1 is input to the output driver OD2 . That is, the AND gate AN2 includes an inverter at the input terminal for inputting the data signal Din1.

在下面，將說明連接關係。 In the following, the connection relationship will be explained.

輸入資料訊號Din1被輸入至上升邊緣偵測電路RED1，該上升邊緣偵測電路RED1在輸入資料訊號Din1的上升邊緣處輸出邊緣脈波訊號EP1。明確地說，輸入資料訊號Din1被延遲電路DC1所延遲，並且被反相器IN11所反相，自反相器IN11所輸出的經反相之經延遲的資料訊號DDB連同該輸入資料訊號Din1一起被輸入至及(AND)閘AN11。然後，及(AND)閘AN11將該邊緣脈波訊號EP1輸出。 The input data signal Din1 is input to the rising edge detection circuit RED1, which outputs the edge pulse signal EP1 at the rising edge of the input data signal Din1. Specifically, the input data signal Din1 is delayed by the delay circuit DC1 and inverted by the inverter IN11, and the inverted delayed data signal DDB output from the inverter IN11 together with the input data signal Din1 It is input to AND gate AN11. Then, the AND gate AN11 outputs the edge pulse signal EP1.

另一方面，該輸入資料訊號Din1的反相訊號經由反相器IN10(在下文中被稱為經反相的資料訊號DB)而被輸入至上升邊緣偵測電路RED2，該上升邊緣偵測電路RED2在該經反相的資料訊號DB的上升邊緣處(也就是說，在輸入資料訊號Din1的下降邊緣處)輸出邊緣脈波訊號EP2。明確地說，該經反相的資料訊號DB被延遲電路DC2所延遲，並且被反相器IN12所反相，而為正常之經延遲的資料訊號DD，來自該反相器IN12之該正常之經延遲的資料訊號DD和該經反相的資料訊號DB一起被輸入至及(AND)閘AN12。然後，及(AND)閘AN12將該邊緣脈波訊號EP2輸出。 On the other hand, the inverted signal of the input data signal Din1 is input to the rising edge detection circuit RED2 through the inverter IN10 (hereinafter referred to as the inverted data signal DB), and the rising edge detection circuit RED2 The edge pulse signal EP2 is output at the rising edge of the inverted data signal DB (that is, at the falling edge of the input data signal Din1). Specifically, the inverted data signal DB is delayed by the delay circuit DC2 and inverted by the inverter IN12, and is the normal delayed data signal DD, the normal signal from the inverter IN12 The delayed data signal DD is input to the AND gate AN12 together with the inverted data signal DB. Then, the AND gate AN12 outputs the edge pulse signal EP2.

自兩個上升邊緣偵測電路RED1,RED2輸出的該等邊緣脈波訊號EP1,EP2兩者皆被輸入至或(OR)閘OR1，該或(OR)閘OR1將發送該輸入資料訊號Din1之上升邊緣和下降邊緣的輸出脈波P10輸出作為脈波產生電路PGC的輸出訊號。 The edge pulse signals EP1, EP2 output from the two rising edge detection circuits RED1, RED2 are both input to the OR gate OR1, which will send the input data signal Din1 The output pulse wave P10 of the rising edge and the falling edge is output as the output signal of the pulse wave generating circuit PGC.

該輸出脈波P10被輸入至分別建構輸出驅動器OD1,OD2的及(AND)閘AN1,AN2。此外，該輸入資料訊號Din1被輸入至及(AND)閘AN1，另一方面，該輸入資料訊號Din1的反相訊號被輸入至及(AND)閘AN2。 The output pulse wave P10 is input to AND gates AN1 and AN2 that construct the output drivers OD1 and OD2, respectively. In addition, the input data signal Din1 is input to the AND gate AN1. On the other hand, the inverted signal of the input data signal Din1 is input to the AND gate AN2.

結果是，及(AND)閘AN1輸出用以發送輸入資料訊號Din1的上升邊緣的H(高)-有效脈波訊號，此脈波訊號經由緩衝器電路B1而被輸入至反相器IN1。然後，反相器IN1輸出用以發送輸入資料訊號Din1的上升邊緣 的L(低)-有效輸出脈波訊號P11作為輸出驅動器OD1的輸出訊號。 As a result, the AND gate AN1 outputs an H (high)-effective pulse signal for transmitting the rising edge of the input data signal Din1, and this pulse signal is input to the inverter IN1 through the buffer circuit B1. Then, the output of the inverter IN1 is used to send the rising edge of the input data signal Din1 L (low)-effective output pulse signal P11 as the output signal of the output driver OD1.

另一方面，及(AND)閘AN2輸出用以發送輸入資料訊號Din1的下降邊緣的H(高)-有效脈波訊號，此脈波訊號經由緩衝器電路B2而被輸入至反相器IN2。然後，反相器IN2輸出用以發送輸入資料訊號Din1的下降邊緣的L(低)-有效輸出脈波訊號P12作為輸出驅動器OD2的輸出訊號。 On the other hand, the AND gate AN2 outputs an H (high)-effective pulse signal for transmitting the falling edge of the input data signal Din1, and this pulse signal is input to the inverter IN2 through the buffer circuit B2. Then, the inverter IN2 outputs the L (low)-effective output pulse signal P12 for transmitting the falling edge of the input data signal Din1 as the output signal of the output driver OD2.

在此，自輸出停止電路10所輸出的停止訊號STP被輸入至分別建構該等輸出驅動器OD1,OD2的及(AND)閘AN1,AN2。在停止訊號STP為L位準的周期期間，分別輸出自該等輸出驅動器OD1,OD2之輸出脈波訊號P11,P12的輸出總是到達H位準。也就是說，在該停止訊號STP為L位準的周期期間，雖然脈波訊號P10係輸出自脈波產生電路PGC，但是輸出脈波訊號P11,P12並非輸出自輸出驅動器OD1,OD2。 Here, the stop signal STP output from the output stop circuit 10 is input to the AND gates AN1, AN2 that construct the output drivers OD1, OD2, respectively. During the period when the stop signal STP is at the L level, the outputs of the output pulse signals P11 and P12 respectively output from the output drivers OD1 and OD2 always reach the H level. In other words, during the period when the stop signal STP is at the L level, although the pulse signal P10 is output from the pulse wave generating circuit PGC, the output pulse signals P11 and P12 are not output from the output drivers OD1 and OD2.

注意，脈波產生電路PGC可以不包含或(OR)閘OR1。在此情況中，邊緣脈波訊號EP1,EP2分別被直接輸入至及(AND)閘AN1,AN2。衹有邊緣脈波訊號EP1和停止訊號STP應該被輸入至及(AND)閘AN1，並且輸入資料訊號Din1不需要被輸入。此外，衹有邊緣脈波訊號EP2和停止訊號STP應該被輸入至及(AND)閘AN2，並且輸入資料訊號Din1的反相訊號不需要被輸入。 Note that the pulse wave generating circuit PGC may not include OR gate OR1. In this case, the edge pulse signals EP1, EP2 are directly input to AND gates AN1, AN2, respectively. Only the edge pulse signal EP1 and the stop signal STP should be input to the AND gate AN1, and the input data signal Din1 need not be input. In addition, only the edge pulse signal EP2 and the stop signal STP should be input to the AND gate AN2, and the inverted signal of the input data signal Din1 need not be input.

<發射器電路TX1的操作> <Operation of Transmitter Circuit TX1>

接著，參照圖4，將說明發射器電路TX1的正常操作。圖4為顯示依據第一實施例之發射器電路TX1的正常操作之一個實例的時序圖。注意，在圖4所示的正常操作模式中，輸出停止電路10並未啟動。 Next, referring to FIG. 4, the normal operation of the transmitter circuit TX1 will be explained. 4 is a timing chart showing an example of normal operation of the transmitter circuit TX1 according to the first embodiment. Note that in the normal operation mode shown in FIG. 4, the output stop circuit 10 is not activated.

圖4顯示，按照從上面開始的順序，輸入資料訊號Din1、經反相之經延遲的資料訊號DDB、邊緣脈波訊號EP1、經反相的資料訊號DB、正常之經延遲的資料訊號DD、邊緣脈波訊號EP2、脈波訊號P10、輸出脈波訊號P11、和輸出脈波訊號P12。 Figure 4 shows that, in order from the top, the input data signal Din1, the inverted delayed data signal DDB, the edge pulse signal EP1, the inverted data signal DB, the normal delayed data signal DD, The edge pulse signal EP2, the pulse signal P10, the output pulse signal P11, and the output pulse signal P12.

在第二層處所示之經反相之經延遲的資料訊號DDB為藉由使在頂層處所示之輸入資料訊號Din1反相並且延遲一段延遲時間Td所取得的訊號。 The inverted delayed data signal DDB shown at the second layer is a signal obtained by inverting the input data signal Din1 shown at the top layer and delaying it for a delay time Td.

在第三層處所示之邊緣脈波訊號EP1為具有寬度Td並且表示在頂層處所示之輸入資料訊號Din1的上升邊緣的脈波訊號，該邊緣脈波訊號EP1係藉由在頂層處所示之該輸入資料訊號Din1和在第二層處所示之該經反相之經延遲的資料訊號DDB之及(AND)邏輯所取得的。 The edge pulse signal EP1 shown at the third layer is a pulse signal having a width Td and representing the rising edge of the input data signal Din1 shown at the top layer. The edge pulse signal EP1 is obtained by AND logic of the input data signal Din1 shown and the inverted and delayed data signal DDB shown at the second layer.

在第四層處所示之經反相的資料訊號DB為在頂層處所示之該輸入資料訊號Din1的反相訊號。 The inverted data signal DB shown at the fourth layer is the inverted signal of the input data signal Din1 shown at the top layer.

在第五層處所示之正常之經延遲的資料訊號DD為藉由使在頂層處所示之該輸入資料訊號Din1延遲一段延遲時間Td所取得的訊號。 The normal delayed data signal DD shown at the fifth layer is a signal obtained by delaying the input data signal Din1 shown at the top layer for a delay time Td.

在第六層處所示之邊緣脈波訊號EP2為具有寬度Td並且表示在頂層處所示之該輸入資料訊號Din1的下降邊緣的脈波訊號，該邊緣脈波訊號EP2係藉由在第四層處所示之該經反相的資料訊號DB和在第五層處所示之正常之經延遲的資料訊號DD之及(AND)邏輯所取得的。 The edge pulse signal EP2 shown at the sixth layer is a pulse signal having a width Td and representing the falling edge of the input data signal Din1 shown at the top layer. The edge pulse signal EP2 is obtained by AND logic of the inverted data signal DB shown at the layer and the normal delayed data signal DD shown at the fifth layer.

在第七層處所示之脈波訊號P10為表示在頂層處所示之該輸入資料訊號Din1的上升邊緣和下降邊緣的脈波訊號，該脈波訊號P10係藉由在第三層處所示之該邊緣脈波訊號EP1和在第六層處所示之該邊緣脈波訊號EP2的或(OR)邏輯所取得的。 The pulse signal P10 shown at the seventh layer is a pulse signal representing the rising edge and the falling edge of the input data signal Din1 shown at the top layer. The pulse signal P10 is obtained by It is obtained by OR logic of the edge pulse signal EP1 shown and the edge pulse signal EP2 shown at the sixth layer.

在第八層處所示之輸出脈波訊號P11為表示在頂層處所示之該輸入資料訊號Din1的上升邊緣之L-有效脈波訊號，該輸出脈波訊號P11為藉由使經由在頂層處所示之該輸入資料訊號Din1和在第七層處所示之該脈波訊號P10之及(AND)邏輯所取得的訊號反相所取得之訊號。 The output pulse signal P11 shown at the eighth layer is an L-effective pulse signal representing the rising edge of the input data signal Din1 shown at the top layer. The output pulse signal P11 is passed through the top layer The signal obtained by the AND logic of the input data signal Din1 shown at the position and the pulse signal P10 shown at the seventh layer is inverted.

在底層處所示之輸出脈波訊號P12為表示在頂層處所示之該輸入資料訊號Din1的下降邊緣之L-有效脈波訊號，該輸出脈波訊號P12為藉由使在第四層處所示之該經反相的資料訊號DB和在第七層處所示之該脈波訊號P10之及(AND)邏輯所取得的訊號反相所取得之訊號。 The output pulse signal P12 shown at the bottom layer is an L-effective pulse signal representing the falling edge of the input data signal Din1 shown at the top layer. The output pulse signal P12 is obtained by using the fourth layer The inverted data signal DB shown and the signal obtained by the AND logic of the pulse signal P10 shown at the seventh layer are inverted to obtain the signal.

接著，將說明時間序列。 Next, the time series will be explained.

在時間點t1，在頂層處所示之該輸入資料訊號Din1從L位準切換至H位準(亦即，上升邊緣)。因此，在第三層處所示之該邊緣脈波訊號EP1和在第七層處所示之 該脈波訊號P10從L位準切換至H位準，並且在第八層處所示之該輸出脈波訊號P11從H位準切換至L位準。 At the time point t1, the input data signal Din1 shown at the top layer is switched from the L level to the H level (that is, the rising edge). Therefore, the edge pulse signal EP1 shown at the third layer and the one shown at the seventh layer The pulse signal P10 is switched from the L level to the H level, and the output pulse signal P11 shown at the eighth layer is switched from the H level to the L level.

在時間點t2，在第二層處所示之該經反相之經延遲的資料訊號DDB從H位準切換至L位準。因此，在第三層處所示之該邊緣脈波訊號EP1和在第七層處所示之該脈波訊號P10從H位準切換至L位準，並且在第八層處所示之該輸出脈波訊號P11從L位準切換至H位準。 At the time point t2, the inverted and delayed data signal DDB shown at the second layer is switched from the H level to the L level. Therefore, the edge pulse signal EP1 shown at the third layer and the pulse signal P10 shown at the seventh layer are switched from the H level to the L level, and the edge shown at the eighth layer The output pulse signal P11 switches from L level to H level.

在時間點t3，在頂層處所示之該輸入資料訊號Din1從從H位準切換至L位準(亦即，下降邊緣)，並且在第四層處所示之該經反相的資料訊號DB從L位準切換至H位準。因此，在第六層處所示之該邊緣脈波訊號EP2和在第七層處所示之該脈波訊號P10從L位準切換至H位準，並且在底層處所示之該輸出脈波訊號P12從H位準切換至L位準。 At time t3, the input data signal Din1 shown at the top layer is switched from the H level to the L level (that is, the falling edge), and the inverted data signal shown at the fourth layer DB switches from L level to H level. Therefore, the edge pulse signal EP2 shown at the sixth layer and the pulse signal P10 shown at the seventh layer are switched from the L level to the H level, and the output pulse shown at the bottom layer The wave signal P12 switches from the H level to the L level.

在時間點t4，在第五層處所示之該正常之經延遲的資料訊號DD從H位準切換至L位準。因此，在第六層處所示之該邊緣脈波訊號EP2和在第七層處所示之該脈波訊號P10從H位準切換至L位準，並且在底層處所示之該輸出脈波訊號P12從L位準切換至H位準。 At time t4, the normal delayed data signal DD shown at the fifth layer is switched from the H level to the L level. Therefore, the edge pulse signal EP2 shown at the sixth layer and the pulse signal P10 shown at the seventh layer are switched from the H level to the L level, and the output pulse shown at the bottom layer The wave signal P12 switches from L level to H level.

<接收器電路RX1的特定電路結構> <Specific circuit structure of receiver circuit RX1>

接著，參照圖5，將說明接收器電路RX1的特定電路結構，下面所示的電路結構僅僅是例子。圖5為顯示依據第一實施例之接收器電路RX1的特定電路結構之實例的 電路圖。如圖5所示，接收器電路RX1包含脈波偵測電路PDC、兩個脈波加寬電路PWC1,PWC2、序向邏輯電路SLC、和或(OR)閘OR2。 Next, referring to FIG. 5, a specific circuit structure of the receiver circuit RX1 will be described, and the circuit structure shown below is merely an example. FIG. 5 is an example showing a specific circuit structure of the receiver circuit RX1 according to the first embodiment Circuit diagram. As shown in FIG. 5, the receiver circuit RX1 includes a pulse wave detection circuit PDC, two pulse wave widening circuits PWC1, PWC2, a sequence logic circuit SLC, and an OR gate OR2.

下面，將說明連接關係。 Next, the connection relationship will be explained.

回應自發射器電路TX1所輸出之輸出脈波訊號P11,P12，跨於次要線圈L12之相對端上所產生的接收訊號VR被輸入至脈波偵測電路PDC，該脈波偵測電路PDC當偵測到正脈波時即輸出正脈波偵測訊號PPD1，並且當偵測到負脈波時即輸出負脈波偵測訊號NPD1。明確地說，當自該發射器電路TX1輸出該等輸出脈波訊號P11,P12時，不管哪一個訊號被輸出，一對的正脈波偵測訊號PPD1和負脈波偵測訊號NPD1被輸出。然而，在輸出脈波訊號P11與輸出脈波訊號P12之間，正脈波偵測訊號PPD1和負脈波偵測訊號NPD1的輸出順序係相反的。在本實施例中，當輸出脈波訊號P11被輸出時，正脈波偵測訊號PPD1先被輸出；並且當輸出脈波訊號P12被輸出時，負脈波偵測訊號NPD1先被輸出。 In response to the output pulse signals P11, P12 output from the transmitter circuit TX1, the received signal VR generated on the opposite end of the secondary coil L12 is input to the pulse wave detection circuit PDC, which is the pulse wave detection circuit PDC When a positive pulse wave is detected, a positive pulse wave detection signal PPD1 is output, and when a negative pulse wave is detected, a negative pulse wave detection signal NPD1 is output. Specifically, when the output pulse signals P11, P12 are output from the transmitter circuit TX1, no matter which signal is output, a pair of positive pulse wave detection signal PPD1 and negative pulse wave detection signal NPD1 are output . However, between the output pulse signal P11 and the output pulse signal P12, the output sequence of the positive pulse wave detection signal PPD1 and the negative pulse wave detection signal NPD1 is reversed. In this embodiment, when the output pulse signal P11 is output, the positive pulse wave detection signal PPD1 is output first; and when the output pulse signal P12 is output, the negative pulse wave detection signal NPD1 is output first.

該正脈波偵測訊號PPD1被輸入至脈波加寬電路PWC1，並且負脈波偵測訊號NPD1被輸入至脈波加寬電路PWC2。該等脈波加寬電路PWC1,PWC2分別使所接收到之正脈波偵測訊號PPD1和負脈波偵測訊號NPD1被加寬，並且輸出正脈波偵測訊號PPD2和負脈波偵測訊號NPD2。在此，該等脈波加寬電路PWC1,PWC2僅使正脈波偵測訊號PPD1和負脈波偵測訊號NPD1各自的下降邊 緣延遲，而沒有改變上升邊緣。因而，正脈波偵測訊號PPD2的H位準期間和負脈波偵測訊號NPD2的H位準期間彼此部分重疊。 The positive pulse wave detection signal PPD1 is input to the pulse wave widening circuit PWC1, and the negative pulse wave detection signal NPD1 is input to the pulse wave widening circuit PWC2. The pulse wave widening circuits PWC1 and PWC2 respectively widen the received positive pulse wave detection signal PPD1 and negative pulse wave detection signal NPD1, and output positive pulse wave detection signal PPD2 and negative pulse wave detection Signal NPD2. Here, the pulse-width widening circuits PWC1 and PWC2 only make the respective falling edges of the positive pulse wave detection signal PPD1 and the negative pulse wave detection signal NPD1 The edge is delayed without changing the rising edge. Therefore, the H level period of the positive pulse wave detection signal PPD2 and the H level period of the negative pulse wave detection signal NPD2 partially overlap each other.

正脈波偵測訊號PPD2和負脈波偵測訊號NPD2被輸入至序向邏輯電路SLC，該序向邏輯電路SLC認出所接收到之正脈波偵測訊號PPD2和負脈波偵測訊號NPD2的順序，並且輸出該輸出資料訊號Dout1。明確地說，當正脈波偵測訊號PPD2先被接收到時，該序向邏輯電路SLC輸出H位準作為該輸出資料訊號Dout1。另一方面，當負脈波偵測訊號NPD2先被接收到時，該序向邏輯電路SLC輸出L位準作為該輸出資料訊號Dout1。 The positive pulse wave detection signal PPD2 and the negative pulse wave detection signal NPD2 are input to the sequence logic circuit SLC, which recognizes the received positive pulse wave detection signal PPD2 and negative pulse wave detection signal NPD2 sequence, and output the output data signal Dout1. Specifically, when the positive pulse wave detection signal PPD2 is received first, the sequence outputs the H level to the logic circuit SLC as the output data signal Dout1. On the other hand, when the negative pulse detection signal NPD2 is received first, the sequence outputs the L level to the logic circuit SLC as the output data signal Dout1.

再者，正脈波偵測訊號PPD2和負脈波偵測訊號NPD2被輸入至或(OR)閘OR2，該或(OR)閘OR2輸出脈波偵測訊號PD1。如同稍後將被說明於第三實施例中者，該脈波偵測訊號PD1可以被使用，例如，作為用來測量從當該脈波偵測訊號PD1被輸出實開始的時間期間之計時器的重設訊號。注意，如同可從圖5中看出，該或(OR)閘OR2在產生該輸出資料訊號Dout1方面並非必要的。 Furthermore, the positive pulse wave detection signal PPD2 and the negative pulse wave detection signal NPD2 are input to the OR gate OR2, and the OR gate OR2 outputs the pulse wave detection signal PD1. As will be described later in the third embodiment, the pulse wave detection signal PD1 can be used, for example, as a timer for measuring the time period from when the pulse wave detection signal PD1 is outputted Reset signal. Note that, as can be seen from FIG. 5, the OR gate OR2 is not necessary in generating the output data signal Dout1.

<接收器電路RX1的操作> <Operation of Receiver Circuit RX1>

接著，參照圖6，將說明接收器電路RX1的操作。圖6為顯示依據第一實施例之接收器電路RX1之操作的一個實例的時序圖，圖6顯示，按照從上面開始的順序，該發 射器電路TX1之輸入資料訊號Din1、自該發射器電路TX1輸出之輸出脈波訊號P11,P12、次要線圈L12之接收訊號VR、正脈波偵測訊號PPD1、負脈波偵測訊號NPD1、正脈波偵測訊號PPD2、負脈波偵測訊號NPD2、輸出資料訊號Dout1、和脈波偵測訊號PD1。 Next, referring to FIG. 6, the operation of the receiver circuit RX1 will be explained. FIG. 6 is a timing chart showing an example of the operation of the receiver circuit RX1 according to the first embodiment. FIG. 6 shows that in accordance with the order from the top The input data signal Din1 of the transmitter circuit TX1, the output pulse signals P11, P12 output from the transmitter circuit TX1, the received signal VR of the secondary coil L12, the positive pulse wave detection signal PPD1, the negative pulse wave detection signal NPD1 , Positive pulse wave detection signal PPD2, negative pulse wave detection signal NPD2, output data signal Dout1, and pulse wave detection signal PD1.

在第四層處所示之次要線圈L12的接收訊號VR中，依據在第二層處所示之輸出脈波訊號P11和在第三層處所示之輸出脈波訊號P12，在圖表中向上投射的正脈波或在圖表中向下投射的負脈波被產生。明確地說，在輸出脈波訊號P11的下降邊緣和輸出脈波訊號P12的上升邊緣處，正脈波被產生。另一方面，在輸出脈波訊號P11的上升邊緣和輸出脈波訊號P12的下降邊緣處，負脈波被產生。 In the received signal VR of the secondary coil L12 shown at the fourth layer, based on the output pulse signal P11 shown at the second layer and the output pulse signal P12 shown at the third layer, in the graph A positive pulse wave projected upward or a negative pulse wave projected downward in the chart is generated. Specifically, at the falling edge of the output pulse signal P11 and the rising edge of the output pulse signal P12, a positive pulse wave is generated. On the other hand, at the rising edge of the output pulse signal P11 and the falling edge of the output pulse signal P12, a negative pulse wave is generated.

在第五層處所示之正脈波偵測訊號PPD1被輸出於接收訊號VR中之正脈波被產生於其中的時序處。 The positive pulse wave detection signal PPD1 shown at the fifth layer is output to the timing at which the positive pulse wave in the received signal VR is generated.

在第六層處所示之負脈波偵測訊號NPD1被輸出於接收訊號VR中之負脈波被產生於其中的時序處。 The negative pulse wave detection signal NPD1 shown at the sixth layer is output to the timing at which the negative pulse wave in the received signal VR is generated.

在第七層處所示之正脈波偵測訊號PPD2為藉由使在脈波加寬電路PWC1處之正脈波偵測訊號PPD1的下降邊緣延遲所加寬的訊號。 The positive pulse wave detection signal PPD2 shown at the seventh layer is a signal widened by delaying the falling edge of the positive pulse wave detection signal PPD1 at the pulse wave widening circuit PWC1.

在第八層處所示之負脈波偵測訊號NPD2為藉由使在脈波加寬電路PWC2處之負脈波偵測訊號NPD1的下降邊緣延遲所加寬的訊號。 The negative pulse wave detection signal NPD2 shown at the eighth layer is a signal widened by delaying the falling edge of the negative pulse wave detection signal NPD1 at the pulse wave widening circuit PWC2.

在底層處所示之脈波偵測訊號PD1為每一次當該輸出脈波訊號P11和該輸出脈波訊號P12的其中一者被輸出 時所輸出的訊號。如上所述，該脈波偵測訊號PD1係產生自該正脈波偵測訊號PPD2和該負脈波偵測訊號NPD2。 The pulse detection signal PD1 shown at the bottom layer is every time when one of the output pulse signal P11 and the output pulse signal P12 is output The signal output at the time. As described above, the pulse wave detection signal PD1 is generated from the positive pulse wave detection signal PPD2 and the negative pulse wave detection signal NPD2.

接著，將說明時間序列。 Next, the time series will be explained.

在時間點t1，因為該輸出脈波訊號P11從H位準切換至L位準，所以正脈波被產生於接收訊號VR中。因此，在時間點t1，正脈波偵測訊號PPD1,PPD2從L位準切換至H位準。由於該正脈波偵測訊號PPD2從L位準切換至H位準的結果，H位準被輸出作為該輸出資料訊號Dout1。 At time t1, since the output pulse signal P11 is switched from the H level to the L level, a positive pulse wave is generated in the received signal VR. Therefore, at the time point t1, the positive pulse wave detection signals PPD1 and PPD2 are switched from the L level to the H level. As a result of the switching of the positive pulse wave detection signal PPD2 from the L level to the H level, the H level is output as the output data signal Dout1.

在時間點t2，因為該輸出脈波訊號P11從L位準切換至H位準，所以負脈波被產生於該接收訊號VR中。因此，在時間點t2，該等負脈波偵測訊號NPD1,NPD2從L位準切換至H位準。也就是說，在時間點t2，在該負脈波偵測訊號NPD2從L位準切換至H位準的同時，該正脈波偵測訊號PPD2仍然在H位準。因此，L位準並未被輸出作為該輸出資料訊號Dout1，而且H位準被保持著。也就是說，當該負脈波偵測訊號NPD2從L位準轉變至H位準且該正脈波偵測訊號PPD2為H位準時，該輸出資料訊號Dout1並不改變。 At time t2, because the output pulse signal P11 is switched from the L level to the H level, a negative pulse wave is generated in the received signal VR. Therefore, at the time point t2, the negative pulse detection signals NPD1, NPD2 are switched from the L level to the H level. In other words, at time t2, while the negative pulse detection signal NPD2 is switched from the L level to the H level, the positive pulse detection signal PPD2 is still at the H level. Therefore, the L level is not output as the output data signal Dout1, and the H level is maintained. That is, when the negative pulse wave detection signal NPD2 changes from the L level to the H level and the positive pulse wave detection signal PPD2 is the H level, the output data signal Dout1 does not change.

在時間點t3，因為該輸出脈波訊號P12從H位準切換至L位準，所以負脈波被產生於該接收訊號VR中。因此，在時間點t3，該等負脈波偵測訊號NPD1,NPD2從L位準切換至H位準。由於該負脈波偵測訊號NPD2從L位 準轉變至H位準的結果，L位準被輸出作為該輸出資料訊號Dout1。 At time t3, because the output pulse signal P12 is switched from the H level to the L level, a negative pulse wave is generated in the received signal VR. Therefore, at time t3, the negative pulse detection signals NPD1, NPD2 are switched from the L level to the H level. Because the negative pulse detection signal NPD2 starts from the L position As a result of the level transition to the H level, the L level is output as the output data signal Dout1.

在時間點t4，因為該輸出脈波訊號P12從L位準切換至H位準，所以正脈波被產生於該接收訊號VR中。因此，在時間點t4，該等正脈波偵測訊號PPD1,PPD2從L位準切換至H位準。也就是說，在時間點t4，在該正脈波偵測訊號PPD2從L位準切換至H位準的同時，該負脈波偵測訊號NPD2仍然在H位準。因此，H位準並未被輸出作為該輸出資料訊號Dout1，而且L位準被保持著。也就是說，當該正脈波偵測訊號PPD2從L位準轉變至H位準且該負脈波偵測訊號NPD2為H位準時，該輸出資料訊號Dout1並不改變。 At time t4, since the output pulse signal P12 is switched from the L level to the H level, a positive pulse wave is generated in the received signal VR. Therefore, at the time point t4, the positive pulse wave detection signals PPD1, PPD2 are switched from the L level to the H level. That is, at time t4, while the positive pulse wave detection signal PPD2 is switched from the L level to the H level, the negative pulse wave detection signal NPD2 is still at the H level. Therefore, the H level is not output as the output data signal Dout1, and the L level is maintained. In other words, when the positive pulse wave detection signal PPD2 changes from the L level to the H level and the negative pulse wave detection signal NPD2 is the H level, the output data signal Dout1 does not change.

<依據比較實例之發射器電路TX10的電路結構> <The circuit structure of the transmitter circuit TX10 according to the comparative example>

接著，參照圖7，將說明依據第一實施例之比較實例的發射器電路TX10。圖7為顯示依據第一實施例之比較實例之發射器電路TX10的特定電路結構的一個實例的電路圖。如圖7所示，該發射器電路TX10係不同於圖3中所示之依據第一實施例的發射器電路TX1(其中並不包含輸出停止電路10)，其他結構係類似於圖3中所示之依據第一實施例的發射器電路TX1的結構。 Next, referring to FIG. 7, a transmitter circuit TX10 according to a comparative example of the first embodiment will be explained. 7 is a circuit diagram showing an example of a specific circuit structure of a transmitter circuit TX10 according to a comparative example of the first embodiment. As shown in FIG. 7, the transmitter circuit TX10 is different from the transmitter circuit TX1 shown in FIG. 3 according to the first embodiment (which does not include the output stop circuit 10), and the other structure is similar to that shown in FIG. The structure of the transmitter circuit TX1 according to the first embodiment is shown.

<依據比較實例之發射器電路TX10中之失效發生的機制> <The mechanism of failure occurrence in the transmitter circuit TX10 according to the comparative example>

接著，參照圖8，將說明在用依據比較實例的發射器 電路TX10之HBM測試時失效發生的機制。圖8為用來說明在用依據比較實例的發射器電路TX10之HBM測試時失效發生之機制的時序圖表，圖8顯示，按照從上面開始的順序，電源電壓VDD1、輸入資料訊號Din1、脈波訊號P10、輸出脈波訊號P1、和輸出脈波訊號P2。 Next, referring to FIG. 8, a transmitter according to a comparative example in use will be explained The mechanism of failure occurrence during HBM test of circuit TX10. FIG. 8 is a timing chart for explaining the mechanism of failure occurrence in the HBM test of the transmitter circuit TX10 according to the comparative example. FIG. 8 shows that, in order from the top, the power supply voltage VDD1, the input data signal Din1, and the pulse wave Signal P10, output pulse signal P1, and output pulse signal P2.

如同在頂層處所示，藉由施加浪湧電流，電源電壓VDD1持續地增加而超過指定電壓。在圖8所示的實例中，限幅器(未顯示出)被設置而使得電源電壓VDD1並未超過上限電壓。因此，在施加浪湧電流之後，過了一會兒，電源電壓VDD1變成固定在該上限電壓。 As shown at the top layer, by applying a surge current, the power supply voltage VDD1 continuously increases to exceed the specified voltage. In the example shown in FIG. 8, a limiter (not shown) is set so that the power supply voltage VDD1 does not exceed the upper limit voltage. Therefore, after the inrush current is applied, after a while, the power supply voltage VDD1 becomes fixed at the upper limit voltage.

如同在第二層處所示，輸入資料訊號Din1保持在L位準。 As shown at the second level, the input data signal Din1 remains at the L level.

如同在第三層處所示，依據電源電壓VDD1的增加，自脈波產生電路PGC輸出之脈波訊號P10中可能會產生錯誤的脈波。在圖8的實例中，產生兩個錯誤的脈波。類似於電源電壓VDD1的開啟模式，延遲電路DC1,DC2之輸出訊號和脈波產生電路PGC中之內部節點的訊號位準的不穩定狀態造成這樣錯誤的脈波。注意，圖8中所示之錯誤的脈波僅為一例，而且單一個錯誤的脈波會造成失效。 As shown in the third layer, according to the increase of the power supply voltage VDD1, an erroneous pulse wave may be generated in the pulse signal P10 output from the pulse wave generation circuit PGC. In the example of FIG. 8, two false pulses are generated. Similar to the on mode of the power supply voltage VDD1, the unstable state of the output signals of the delay circuits DC1, DC2 and the signal level of the internal nodes in the pulse wave generation circuit PGC causes such an erroneous pulse wave. Note that the wrong pulse shown in Figure 8 is only an example, and a single wrong pulse will cause failure.

結果是，在第五層處所示之輸出脈波訊號P2中產生錯誤的脈波。另一方面，在第四層處所示之輸出脈波訊號P1中沒有產生錯誤的脈波。也就是說，在該等輸出脈波訊號P1,P2之間發生可能的差異，而且大電流流經主要 線圈L11。結果是，諸如輸出驅動器OD1,OD2的擊穿或主要線圈L11的斷裂之失效可能會發生。 As a result, an erroneous pulse wave is generated in the output pulse signal P2 shown at the fifth layer. On the other hand, no false pulse is generated in the output pulse signal P1 shown at the fourth layer. In other words, a possible difference occurs between these output pulse signals P1, P2, and a large current flows through the main Coil L11. As a result, failures such as breakdown of the output drivers OD1, OD2 or breakage of the main coil L11 may occur.

<發射器電路TX1中之失效抑制的機制> <The mechanism of failure suppression in the transmitter circuit TX1>

接著，參照圖9，將說明在圖3中所示之用依據本實施例的發射器電路TX1之HBM測試時抑制失效的機制。圖9為用來說明在用發射器電路TX1之HBM測試時抑制失效之機制的時序圖表。 Next, referring to FIG. 9, a mechanism for suppressing failure during the HBM test using the transmitter circuit TX1 according to the present embodiment shown in FIG. 3 will be explained. FIG. 9 is a timing chart for explaining the mechanism of suppressing failure during HBM testing with the transmitter circuit TX1.

圖9顯示，按照從上面開始的順序，電源電壓VDD1、輸入資料訊號Din1、脈波訊號P10、停止訊號STP、和輸出脈波訊號P11,P12。在頂層處所示之電源電壓VDD1、在第二層處所示之輸入資料訊號Din1、和在第三層處所示之脈波訊號P10與圖8中的那些元件相同。 Figure 9 shows that, in order from the top, the power supply voltage VDD1, the input data signal Din1, the pulse signal P10, the stop signal STP, and the output pulse signal P11, P12. The power supply voltage VDD1 shown at the top layer, the input data signal Din1 shown at the second layer, and the pulse signal P10 shown at the third layer are the same as those in FIG. 8.

如圖3所示，依據本實施例的發射器電路TX1包含輸出停止電路10，其使輸出脈波訊號P11,P12的輸出停止一段從當電源電壓VDD1被開啟時開始的預定周期。自輸出停止電路10輸出的停止訊號STP被輸入至輸出驅動器OD1,OD2的及(AND)閘AN1,AN2。因此，在停止訊號STP為L位準的周期期間，輸出脈波訊號P11,P12兩者被維持在H位準。換言之，在停止訊號STP為L位準的周期期間，輸出脈波訊號P11,P12的輸出被停止。 As shown in FIG. 3, the transmitter circuit TX1 according to the present embodiment includes an output stop circuit 10, which stops the output of the output pulse signals P11, P12 for a predetermined period starting when the power supply voltage VDD1 is turned on. The stop signal STP output from the output stop circuit 10 is input to the AND drivers AN1 and AN2 of the output drivers OD1 and OD2. Therefore, during the period when the stop signal STP is at the L level, both the output pulse signals P11 and P12 are maintained at the H level. In other words, during the period when the stop signal STP is at the L level, the output of the output pulse signals P11, P12 is stopped.

如在圖9中的第四層處所示，類似於電源電壓VDD1的開啟模式，停止訊號STP變成L位準一段從當電源電壓VDD1藉由HBM測試而開始增加時開始的預定周期。 As shown at the fourth layer in FIG. 9, similar to the on mode of the power supply voltage VDD1, the stop signal STP becomes the L level for a predetermined period starting when the power supply voltage VDD1 starts to increase by the HBM test.

因此，如在第五層處所示，輸出脈波訊號P11,P12的波型變成彼此相同，並且在輸出脈波訊號P11,P12中不會產生錯誤的脈波。也就是說，輸出脈波訊號P11,P12到達相同的電位，並且沒有電流流經主要線圈L11。結果是，諸如輸出驅動器OD1,OD2的擊穿或主要線圈L11的斷裂之失效可以被抑制。 Therefore, as shown at the fifth layer, the wave patterns of the output pulse signals P11, P12 become the same as each other, and no erroneous pulse wave is generated in the output pulse signals P11, P12. That is, the output pulse signals P11, P12 reach the same potential, and no current flows through the main coil L11. As a result, failures such as breakdown of the output drivers OD1, OD2 or breakage of the main coil L11 can be suppressed.

如同已敘述於上，依據第一實施例的發射器電路TX1包含輸出停止電路10，其使輸出脈波訊號P11及輸出脈波訊號P12的輸出停止一段從當電源電壓VDD1被開啟時開始的預定周期。因此，與電源電壓VDD1之開啟相關聯的錯誤脈波可以被抑制而被被輸出。在靜電放電損壞測試時電源電壓VDD1的增加為一物理現象，其類似於電源電壓VDD1的開啟。因此，有了依據第一實施例的發射器電路TX1，在靜電放電損壞測試時也使，輸出停止電路10啟動，並且歸因於與電源電壓VDD1之增加相關聯的錯誤脈波之任何失效可以被抑制。 As already described above, the transmitter circuit TX1 according to the first embodiment includes the output stop circuit 10, which stops the output of the output pulse signal P11 and the output pulse signal P12 for a period starting from when the power supply voltage VDD1 is turned on cycle. Therefore, the error pulse associated with the turn-on of the power supply voltage VDD1 can be suppressed and output. The increase of the power supply voltage VDD1 during the electrostatic discharge damage test is a physical phenomenon, which is similar to the turn-on of the power supply voltage VDD1. Therefore, with the transmitter circuit TX1 according to the first embodiment, the output stop circuit 10 is also activated during the electrostatic discharge damage test, and any failure due to an error pulse associated with an increase in the power supply voltage VDD1 can be suppressed.

<輸出停止電路10的特定電路結構> <Specific circuit structure of the output stop circuit 10>

接著，參照圖10，將說明依據第一實施例之輸出停止電路10的特定電路結構，下面所示之電路結構僅為實例。圖10為顯示依據第一實施例之輸出停止電路10之特定電路結構的一個實例之電路圖。如圖10所示，輸出停止電路10包含電阻器元件R1、電容器元件C1、及反相器IN21。 Next, referring to FIG. 10, a specific circuit structure of the output stop circuit 10 according to the first embodiment will be described. The circuit structure shown below is just an example. FIG. 10 is a circuit diagram showing an example of a specific circuit structure of the output stop circuit 10 according to the first embodiment. As shown in FIG. 10, the output stop circuit 10 includes a resistor element R1, a capacitor element C1, and an inverter IN21.

反相器IN21的輸入N1經由電容器元件C1而被連接至電源。此外，反相器IN21的輸入N1經由電阻器元件R1而被接地(連接至地)。也就是說，反相器IN21的輸入N1為介於電容器元件C1與電阻器元件R1之間的連接節點。然後，自反相器IN21輸出停止訊號STP。 The input N1 of the inverter IN21 is connected to the power supply via the capacitor element C1. In addition, the input N1 of the inverter IN21 is grounded (connected to ground) via the resistor element R1. That is, the input N1 of the inverter IN21 is a connection node between the capacitor element C1 and the resistor element R1. Then, the stop signal STP is output from the inverter IN21.

注意，停止訊號STP也可以藉由將電容器元件C1接地並且將電阻器元件R1連接至電源來予以產生。在此情況中，另一反相器IN21應該被添加至反相器IN21的輸出。 Note that the stop signal STP can also be generated by grounding the capacitor element C1 and connecting the resistor element R1 to the power source. In this case, another inverter IN21 should be added to the output of the inverter IN21.

<輸出停止電路10的操作> <Operation of output stop circuit 10>

接著，參照圖11，將說明當電源電壓被開啟時依據第一實施例之輸出停止電路10的操作。圖11為用來說明當電源電壓被開啟時依據第一實施例之輸出停止電路10之操作的時序圖表。圖11顯示，按照從上面開始的順序，電源電壓VDD1、反相器IN21之輸入N1的電壓、及停止訊號STP。 Next, referring to FIG. 11, the operation of the output stop circuit 10 according to the first embodiment when the power supply voltage is turned on will be explained. 11 is a timing chart for explaining the operation of the output stop circuit 10 according to the first embodiment when the power supply voltage is turned on. Fig. 11 shows the power supply voltage VDD1, the voltage of the input N1 of the inverter IN21, and the stop signal STP in the order from the top.

如同在頂層處所示，當電源電壓VDD1藉由被開啟而從地電壓GND增加至指定電壓VDD，如同在第二層處所示，經由電容器元件C1而被連接至電源的反相器IN21之輸入N1的電壓也隨著該指定電壓VDD而增加。因此，如同在第三層處所示，在電源電壓VDD1的開啟之後，為反相器IN21之輸出的停止訊號STP就變成L位準。 As shown at the top layer, when the power supply voltage VDD1 is turned on to increase from the ground voltage GND to the specified voltage VDD, as shown at the second layer, it is connected to the power supply inverter IN21 via the capacitor element C1 The voltage of the input N1 also increases with the specified voltage VDD. Therefore, as shown at the third layer, after the power supply voltage VDD1 is turned on, the stop signal STP output from the inverter IN21 becomes the L level.

如同在第二層處所示，反相器IN21之輸入N1的電 壓藉由經由電阻器元件R1而被放電而逐漸降低。當反相器IN21之輸入N1的電壓到達反相器IN21之邏輯臨界電壓Vth時，反相器IN21的輸出從L位準轉變至H位準。據此，如同在第三層處所示，停止訊號STP從L位準轉變至H位準。在停止訊號STP為L位準的周期期間，輸出脈波訊號P11,P12的輸出被停止。 As shown at the second layer, the power of the input N1 of the inverter IN21 The voltage gradually decreases by being discharged through the resistor element R1. When the voltage of the input N1 of the inverter IN21 reaches the logic threshold voltage Vth of the inverter IN21, the output of the inverter IN21 changes from the L level to the H level. Accordingly, as shown at the third layer, the stop signal STP transitions from the L level to the H level. During the period when the stop signal STP is at the L level, the output of the output pulse signals P11 and P12 is stopped.

藉由電阻器元件R1和電容器元件C1的時間常數來決定停止周期。 The stop period is determined by the time constant of the resistor element R1 and the capacitor element C1.

<發射器電路TX1的變型> <Variation of transmitter circuit TX1>

圖12及13為顯示依據第一實施例之發射器電路TX1的變型之電路圖。 12 and 13 are circuit diagrams showing a modification of the transmitter circuit TX1 according to the first embodiment.

在圖3中所示的發射器電路TX1中，停止訊號STP被輸入至分別建構輸出驅動器OD1,OD2的及(AND)閘AN1,AN2。 In the transmitter circuit TX1 shown in FIG. 3, the stop signal STP is input to the AND gates AN1, AN2 constructing the output drivers OD1, OD2 and (AND) gates, respectively.

另一方面，在圖12中所示的發射器電路TX1中，及(AND)閘AN21,AN22分別建構輸出驅動器OD1,OD2之反相器IN1,IN2的前級，並且停止訊號STP被輸入至及(AND)閘AN21,AN22。 On the other hand, in the transmitter circuit TX1 shown in FIG. 12, and (AND) gates AN21, AN22 construct the output driver OD1, OD2 inverter IN1, IN2 preceding stage, and the stop signal STP is input to And (AND) gate AN21, AN22.

此外，在圖13中所示的發射器電路TX1中，停止訊號STP被輸入至分別建構上升邊緣偵測電路RED1,RED2的及(AND)閘AN11,AN12。 In addition, in the transmitter circuit TX1 shown in FIG. 13, the stop signal STP is input to the AND gates AN11 and AN12 that respectively construct the rising edge detection circuits RED1 and RED2.

有了圖12及13所示的電路結構，類似於圖3所示的電路結構，輸出脈波訊號P11和輸出脈波訊號P12的輸 出也可被停止一段從當電源電壓VDD1被開啟時開始的預定周期。 With the circuit structure shown in FIGS. 12 and 13, similar to the circuit structure shown in FIG. 3, the output of the output pulse signal P11 and the output pulse signal P12 The output can also be stopped for a predetermined period starting when the power supply voltage VDD1 is turned on.

注意，有了圖13所示的電路結構，在從脈波產生電路PGC中所輸出之脈波訊號P10其本身之任何錯誤脈波的產生被抑制。 Note that with the circuit structure shown in FIG. 13, the generation of any erroneous pulse waves in the pulse wave signal P10 output from the pulse wave generation circuit PGC itself is suppressed.

<脈波產生電路PGC的變型> <Variation of pulse wave generation circuit PGC>

圖14為顯示依據第一實施例之脈波產生電路PGC的變型之電路圖。在圖14中所示的脈波產生電路PGC中，延遲電路DC1,DC2經由電容器元件C11,C21而分別被連接至電源。此外，反相器IN11,IN12的輸出分別經由電容器元件C12,C22而被連接至接地。 14 is a circuit diagram showing a modification of the pulse wave generating circuit PGC according to the first embodiment. In the pulse wave generating circuit PGC shown in FIG. 14, the delay circuits DC1 and DC2 are connected to the power supply via the capacitor elements C11 and C21, respectively. In addition, the outputs of the inverters IN11 and IN12 are connected to ground via capacitor elements C12 and C22, respectively.

當在電源電壓被開啟時輸入資料訊號Din1為L位準時，及(AND)閘AN11的輸出變成L位準。 When the input data signal Din1 is at the L level when the power supply voltage is turned on, the output of the AND gate AN11 becomes the L level.

在此情況中，及(AND)閘AN12的其中一個輸入為經反相的資料訊號DB，且因此H位準被取得。然而，延遲電路DC2的輸出經由電容器元件C21而被連接至電源，並且反相器IN12的輸出經由電容器元件C22而被接地。因此，為及(AND)閘AN12的另一個輸入之反相器IN12的輸出變成恆定為L位準。因而，及(AND)閘AN12的輸出也變成L位準。 In this case, one of the inputs of the AND gate AN12 is the inverted data signal DB, and therefore the H level is obtained. However, the output of the delay circuit DC2 is connected to the power supply via the capacitor element C21, and the output of the inverter IN12 is grounded via the capacitor element C22. Therefore, the output of the inverter IN12 for the other input of the AND gate AN12 becomes constant at the L level. Therefore, the output of the AND gate AN12 also becomes the L level.

當在電源電壓被開啟時輸入資料訊號Din1為H位準時，及(AND)閘AN11的其中一個輸入變成H位準。然而，延遲電路DC1的輸出經由電容器元件C11而被連接 至電源，並且反相器IN11的輸出經由電容器元件C12而被接地。因此，為及(AND)閘AN11的另一個輸入之反相器IN11的輸出變成穩定為L位準。因而，及(AND)閘AN11的輸出也變成L位準。 When the input data signal Din1 is at the H level when the power supply voltage is turned on, and one of the inputs of the AND gate AN11 becomes the H level. However, the output of the delay circuit DC1 is connected via the capacitor element C11 To the power supply, and the output of the inverter IN11 is grounded via the capacitor element C12. Therefore, the output of the inverter IN11 which is the other input of the AND gate AN11 becomes stable to the L level. Therefore, the output of the AND gate AN11 also becomes the L level.

在此情況中，及(AND)閘AN12的其中一個輸入為經反相的資料訊號DB，且因此為L位準，並且及(AND)閘AN12的輸出也變成L位準。 In this case, one of the inputs of the AND gate AN12 is the inverted data signal DB, and thus is at the L level, and the output of the AND gate AN12 also becomes the L level.

以此方式，有了圖14所示的脈波產生電路PGC，在脈波訊號P10其本身之任何錯誤脈波的產生被抑制。因此，藉由使用這樣的脈波產生電路PGC結合輸出停止電路10，歸因於在靜電放電損壞測試時所產生之錯誤脈波的失效能夠被更有效地抑制。 In this way, with the pulse wave generating circuit PGC shown in FIG. 14, the generation of any erroneous pulse wave in the pulse wave signal P10 itself is suppressed. Therefore, by using such a pulse wave generation circuit PGC in combination with the output stop circuit 10, the failure due to the erroneous pulse wave generated during the electrostatic discharge damage test can be more effectively suppressed.

注意，在藉由多個反相器來建構延遲電路DC1,DC2的情況中，個別反相器的輸出經由電容器元件而被交替地連接至電源及接地係較佳的。 Note that in the case where the delay circuits DC1, DC2 are constructed by a plurality of inverters, it is preferable that the outputs of the individual inverters are alternately connected to the power source and the ground via the capacitor element.

(第二實施例) (Second embodiment) <輸出停止電路20的結構> <Structure of output stop circuit 20>

接著，參照圖15，將說明依據第二實施例之發射器電路TX1。圖15為顯示依據第二實施例之輸出停止電路20的特定電路結構的一個實例之電路圖。如圖15所示，輸出停止電路20包含NMOS電晶體NM1、PMOS電晶體PM1、電容器元件C1,C2、及反相器IN21。除了輸出停止電路20之外，發射器電路TX1的結構係類似於依據第 一實施例之發射器電路TX1的結構。 Next, referring to FIG. 15, a transmitter circuit TX1 according to the second embodiment will be explained. 15 is a circuit diagram showing an example of a specific circuit structure of the output stop circuit 20 according to the second embodiment. As shown in FIG. 15, the output stop circuit 20 includes an NMOS transistor NM1, a PMOS transistor PM1, capacitor elements C1, C2, and an inverter IN21. Except for the output stop circuit 20, the structure of the transmitter circuit TX1 is similar to The structure of the transmitter circuit TX1 of an embodiment.

在輸出停止電路20中，使用NMOS電晶體NM1的關斷電阻來代替圖10所示之輸出停止電路10中的電阻器元件R1。其源極被接地之NMOS電晶體NM1的汲極經由電容器元件C1而被連接至電源，NMOS電晶體NM1的汲極被連接至反相器IN21的輸入N1。 In the output stop circuit 20, the off resistance of the NMOS transistor NM1 is used instead of the resistor element R1 in the output stop circuit 10 shown in FIG. The drain of the NMOS transistor NM1 whose source is grounded is connected to the power supply via the capacitor element C1, and the drain of the NMOS transistor NM1 is connected to the input N1 of the inverter IN21.

另一方面，其源極被連接至電源之PMOS電晶體PM1的汲極經由電容器元件C2而被接地。也就是說，PMOS電晶體PM1與電容器元件C2之間的連接關係和NMOS電晶體NM1與電容器元件C1之間的連接關係在極性上倒反，NMOS電晶體NM1的閘極N2係連接至PMOS電晶體PM1的汲極。此外，PMOS電晶體PM1的閘極係連接至NMOS電晶體NM1的汲極(亦即，反相器IN21的輸入N1)。 On the other hand, the drain of the PMOS transistor PM1 whose source is connected to the power supply is grounded via the capacitor element C2. That is, the connection relationship between the PMOS transistor PM1 and the capacitor element C2 and the connection relationship between the NMOS transistor NM1 and the capacitor element C1 are reversed in polarity, and the gate N2 of the NMOS transistor NM1 is connected to the PMOS transistor The drain of the crystal PM1. In addition, the gate of the PMOS transistor PM1 is connected to the drain of the NMOS transistor NM1 (that is, the input N1 of the inverter IN21).

然後，從反相器IN21輸出停止訊號STP。 Then, the stop signal STP is output from the inverter IN21.

<輸出停止電路20的操作> <Operation of output stop circuit 20>

接著，參照圖16，將說明當電源電壓被開啟時依據第二實施例之輸出停止電路20的操作。圖16為用來說明當電源電壓被開啟時依據第二實施例之輸出停止電路20之操作的時序圖表。圖16顯示，按照從上面開始的順序，電源電壓VDD1、反相器IN21之輸入N1(亦即，PMOS電晶體PM1的閘極)和NMOS電晶體NM1的閘極N2的電壓、及停止訊號STP。 Next, referring to FIG. 16, the operation of the output stop circuit 20 according to the second embodiment when the power supply voltage is turned on will be explained. 16 is a timing chart for explaining the operation of the output stop circuit 20 according to the second embodiment when the power supply voltage is turned on. Fig. 16 shows the voltage of the power supply voltage VDD1, the input N1 of the inverter IN21 (ie, the gate of the PMOS transistor PM1) and the gate N2 of the NMOS transistor NM1, and the stop signal STP in the order from above .

如同在頂層處所示，當電源電壓VDD1依據被開啟的電源電壓VDD1而從地電壓GND增加至指定電壓VDD時，如同由在第二層處之實線所表示者，經由電容器元件C1而被連接至電源的反相器IN21之輸入N1的電壓也增加至該指定電壓VDD。因此，如同在第三層處所示，在電源電壓VDD1的開啟時，為反相器IN21之輸出的停止訊號STP變成L位準。 As shown at the top layer, when the power supply voltage VDD1 increases from the ground voltage GND to the specified voltage VDD according to the turned-on power supply voltage VDD1, as indicated by the solid line at the second layer, it is passed through the capacitor element C1 The voltage of the input N1 of the inverter IN21 connected to the power supply also increases to the specified voltage VDD. Therefore, as shown at the third layer, when the power supply voltage VDD1 is turned on, the stop signal STP output from the inverter IN21 becomes the L level.

當電源電壓VDD1被開啟時，因為反相器IN21之輸入N1(亦即，PMOS電晶體PM1的閘極)的電壓為H位準，所以PMOS電晶體PM1係處於關斷狀態。此外，因為NMOS電晶體NM1之閘極N2的電壓為L位準，所以NMOS電晶體NM1也處於關斷狀態。 When the power supply voltage VDD1 is turned on, because the voltage of the input N1 of the inverter IN21 (that is, the gate of the PMOS transistor PM1) is at the H level, the PMOS transistor PM1 is in the off state. In addition, because the voltage of the gate N2 of the NMOS transistor NM1 is at the L level, the NMOS transistor NM1 is also in the off state.

如同由在第二層處之實線所表示者，反相器IN21之輸入N1的電壓藉由NMOS電晶體NM1的關斷狀態漏洩電流(off-leakage current)而逐漸降低。另一方面，如同由在第二層處之實虛線(dot-and-dash line)所表示者，NMOS電晶體NM1之閘極N2的電壓藉由PMOS電晶體PM1的關斷狀態漏洩電流而逐漸增加。 As indicated by the solid line at the second layer, the voltage of the input N1 of the inverter IN21 is gradually reduced by the off-leakage current of the NMOS transistor NM1. On the other hand, as indicated by the dot-and-dash line at the second layer, the voltage of the gate N2 of the NMOS transistor NM1 is gradually increased by the off-state leakage current of the PMOS transistor PM1 increase.

當反相器IN21之輸入N1(亦即，PMOS電晶體PM1的閘極)或NMOS電晶體NM1之閘極N2的電壓到達臨界電壓時，NMOS電晶體NM1及PMOS電晶體PM1進入開啟狀態。然後，反相器IN21之輸入N1電壓被鎖存於L位準，並且NMOS電晶體NM1之閘極N2的電壓被鎖存於H位準。 When the voltage of the input N1 of the inverter IN21 (that is, the gate of the PMOS transistor PM1) or the gate N2 of the NMOS transistor NM1 reaches a critical voltage, the NMOS transistor NM1 and the PMOS transistor PM1 enter an on state. Then, the input N1 voltage of the inverter IN21 is latched at the L level, and the voltage of the gate N2 of the NMOS transistor NM1 is latched at the H level.

據此，如同在第三層處所示，停止訊號STP從L位準轉變至H位準。在停止訊號STP為L位準的周期期間，輸出脈波訊號P11,P12的輸出被停止。 Accordingly, as shown at the third layer, the stop signal STP transitions from the L level to the H level. During the period when the stop signal STP is at the L level, the output of the output pulse signals P11 and P12 is stopped.

類似於依據第一實施例之發射器電路TX1，依據第二實施例之發射器電路TX1包含輸出停止電路20，其使輸出脈波訊號P11和輸出脈波訊號P12的輸出停止一段從當電源電壓VDD1被開啟時開始的預定周期。因此，與電源電壓VDD1相關聯之錯誤訊號的輸出可以被抑制。在靜電放電損壞測試時該電源電壓VDD1上的增加為類似於該電源電壓VDD1的開啟之物理現象。因而，在靜電放電損壞測試時也，該輸出停止電路20啟動，並且歸因於與該電源電壓VDD1上的增加相關聯之錯誤脈波的任何失效能夠被抑制。 Similar to the transmitter circuit TX1 according to the first embodiment, the transmitter circuit TX1 according to the second embodiment includes an output stop circuit 20, which stops the output of the output pulse signal P11 and the output pulse signal P12 for a period from the current power supply voltage The predetermined period that starts when VDD1 is turned on. Therefore, the output of the error signal associated with the power supply voltage VDD1 can be suppressed. The increase in the power supply voltage VDD1 during the electrostatic discharge damage test is a physical phenomenon similar to the turn-on of the power supply voltage VDD1. Therefore, also in the electrostatic discharge damage test, the output stop circuit 20 is activated, and any failure due to an erroneous pulse wave associated with the increase in the power supply voltage VDD1 can be suppressed.

在此同時，有了依據第一實施例之輸出停止電路10，藉由電阻器元件R1和電容器元件C1的時間常數來決定停止周期。因此，為了確保幾μs的停止周期，該電阻器元件R1和該電容器元件C1的尺寸必須大，並且要求晶片面積的增加。 At the same time, with the output stop circuit 10 according to the first embodiment, the stop period is determined by the time constants of the resistor element R1 and the capacitor element C1. Therefore, in order to ensure a stop period of several μs, the size of the resistor element R1 and the capacitor element C1 must be large, and an increase in the wafer area is required.

另一方面，有了依據第二實施例之輸出停止電路20，使用NMOS電晶體NM1來代替電阻器元件R1。因此，電阻值能夠隨著NMOS電晶體NM1的尺寸變小而增加，並且該電容器元件C1的尺寸也可被縮減。同樣地，PMOS電晶體PM1和電容器元件C2的尺寸也可被縮減。因而，相較於依據第一實施例之輸出停止電路10，在元 件的數目增加的同時，晶片面積整體上可被縮減。 On the other hand, with the output stop circuit 20 according to the second embodiment, the NMOS transistor NM1 is used instead of the resistor element R1. Therefore, the resistance value can be increased as the size of the NMOS transistor NM1 becomes smaller, and the size of the capacitor element C1 can also be reduced. Similarly, the size of the PMOS transistor PM1 and the capacitor element C2 can also be reduced. Therefore, compared to the output stop circuit 10 according to the first embodiment, the As the number of parts increases, the wafer area can be reduced as a whole.

此外，有了依據第二實施例之輸出停止電路20，在輸出停止被解除之後，可以使停止訊號STP藉由NMOS電晶體NM1和PMOS電晶體PM1的開啟電阻而保持在H位準。因而，正常操作時的抗噪性(noise immunity)改善。 In addition, with the output stop circuit 20 according to the second embodiment, after the output stop is released, the stop signal STP can be maintained at the H level by the on-resistance of the NMOS transistor NM1 and the PMOS transistor PM1. Therefore, noise immunity during normal operation is improved.

(第三實施例) (Third embodiment) <輸出停止電路30的結構> <Structure of output stop circuit 30>

接著，參照圖17，將說明依據第三實施例之發射器電路TX1。圖17為顯示依據第三實施例之輸出停止電路30之特定電路結構的一個實例之電路圖。如圖17所示，輸出停止電路30包含非及(NAND)閘ND、電容器元件C1,C2、反相器IN21,IN22、及計數器CTR1。除了輸出停止電路30之外，發射器電路TX1的結構係類似於依據第一實施例之發射器電路TX1的結構。 Next, referring to FIG. 17, a transmitter circuit TX1 according to the third embodiment will be explained. 17 is a circuit diagram showing an example of a specific circuit structure of the output stop circuit 30 according to the third embodiment. As shown in FIG. 17, the output stop circuit 30 includes a NAND gate ND, capacitor elements C1 and C2, inverters IN21 and IN22, and a counter CTR1. Except for the output stop circuit 30, the structure of the transmitter circuit TX1 is similar to that of the transmitter circuit TX1 according to the first embodiment.

反相器IN22的輸入N2經由電容器元件C2而被接地，反相器IN22的輸出經由電容器元件C1而被連接至電源，反相器IN22的輸出被連接至反相器IN21的輸入N1。 The input N2 of the inverter IN22 is grounded via the capacitor element C2, the output of the inverter IN22 is connected to the power supply via the capacitor element C1, and the output of the inverter IN22 is connected to the input N1 of the inverter IN21.

此外，反相器IN22的輸出(亦即，反相器IN21的輸入N1)被輸入至非及(NAND)閘ND，非及(NAND)閘ND的輸出係連接至反相器IN22的輸入N2。也就是說，藉由反相器IN22和非及(NAND)閘ND，鎖存器電 路被建構。 In addition, the output of the inverter IN22 (that is, the input N1 of the inverter IN21) is input to the NAND gate ND, and the output of the NAND gate ND is connected to the input N2 of the inverter IN22 . In other words, by the inverter IN22 and the NAND gate ND, the latch The road is constructed.

換句話說，鎖存器電路的儲存節點N1經由電容器元件C1而被連接至電源，並且儲存節點N2經由電容器元件C2而被接地，鎖存器電路的儲存節點N1,N2分別保持彼此為倒反的電壓。 In other words, the storage node N1 of the latch circuit is connected to the power supply via the capacitor element C1, and the storage node N2 is grounded via the capacitor element C2, and the storage nodes N1, N2 of the latch circuit are kept inverted from each other, respectively The voltage.

輸出自計數器CTR1之規律的(regular)請求訊號RT12的反相訊號被輸入至非及(NAND)閘ND。 The inverted signal of the regular request signal RT12 output from the counter CTR1 is input to the NAND gate ND.

然後，從反相器IN21輸出停止訊號STP。 Then, the stop signal STP is output from the inverter IN21.

注意，規律的請求訊號RT12，舉例來說，為高位準有效的(H-active)脈波訊號，其不規律地被輸出於電源電壓VDD1被開啟之後。然而，輸出自計數器CTR1之訊號可為H-active脈波訊號，其在當電源電壓VDD1被開啟時開始的預定周期的流逝之後只被輸出一次，或者可以是從L位準轉變至H位準並且維持在H位準的致能(enable)訊號。此外，雖然致能訊號的邏輯係類似於停止訊號STP，但其可非有意地，舉例來說，藉由溫度的改變而改變至L位準。如同稍後所更詳細敘述者，在這樣的情況中也，停止訊號STP的值藉由鎖存器電路而被穩定地保持在H位準。 Note that the regular request signal RT12, for example, is a high-level (H-active) pulse signal, which is output irregularly after the power voltage VDD1 is turned on. However, the signal output from the counter CTR1 may be an H-active pulse signal, which is output only once after the lapse of a predetermined period starting when the power supply voltage VDD1 is turned on, or may be changed from the L level to the H level And maintain the enable signal at the H level. In addition, although the logic of the enable signal is similar to the stop signal STP, it can be changed to the L level unintentionally, for example, by a change in temperature. As described in more detail later, also in such a case, the value of the stop signal STP is stably maintained at the H level by the latch circuit.

<輸出停止電路30的操作> <Operation of output stop circuit 30>

接著，參照圖18，將說明當電源電壓被開啟時依據第三實施例之輸出停止電路30的操作。圖18為用來說明當電源電壓被開啟時依據第三實施例之輸出停止電路30 之操作的時序圖表。圖18顯示，按照從上面開始的順序，電源電壓VDD1、儲存節點N1,N2的電壓、規律的請求訊號RT12、及停止訊號STP。 Next, referring to FIG. 18, the operation of the output stop circuit 30 according to the third embodiment when the power supply voltage is turned on will be explained. 18 is a diagram for explaining the output stop circuit 30 according to the third embodiment when the power supply voltage is turned on The timing chart of the operation. FIG. 18 shows that, in order from the top, the power supply voltage VDD1, the storage node N1, N2 voltage, the regular request signal RT12, and the stop signal STP.

如同在頂層處所示，當電源電壓VDD1依據電源電壓VDD1的開啟而從地電壓GND增加至指定電壓VDD時，如同由在第二層處之實線所表示者，經由電容器元件C1而被連接至電源之儲存節點N1的電壓也增加至該指定電壓VDD。因此，如同在第三層處所示，當電源電壓VDD1的開啟時，為反相器IN21之輸出的停止訊號STP變成L位準。 As shown at the top layer, when the power supply voltage VDD1 increases from the ground voltage GND to the specified voltage VDD according to the turn-on of the power supply voltage VDD1, as indicated by the solid line at the second layer, it is connected via the capacitor element C1 The voltage to the storage node N1 of the power supply also increases to the specified voltage VDD. Therefore, as shown at the third layer, when the power supply voltage VDD1 is turned on, the stop signal STP output from the inverter IN21 becomes the L level.

在電源電壓VDD1被開啟之後，如同由在第二層處之實線所表示者；由反相器IN22和非及(NAND)閘ND所建構之鎖存器電路之儲存節點N1的電壓係保持在H位準。另一方面，如同由在第二層處之實虛線所表示者，鎖存器電路之儲存節點N2的電壓係保持在L位準。 After the power supply voltage VDD1 is turned on, as indicated by the solid line at the second layer; the voltage of the storage node N1 of the latch circuit constructed by the inverter IN22 and the NAND gate ND is maintained At the H level. On the other hand, as indicated by the solid dotted line at the second layer, the voltage of the storage node N2 of the latch circuit is maintained at the L level.

如同在第三層處所示，在當電源電壓VDD1被開啟時開始的預定周期的流逝之後，當規律的請求訊號RT12暫時變成H位準時，儲存節點N2的電壓轉變至H位準。因此，儲存節點N1的電壓轉變至L位準。然後，藉由反相器IN22和非及(NAND)閘ND，儲存節點N1的電壓被鎖存在L位準且儲存節點N2的電壓被鎖存在H位準。不管規律的請求訊號RT12的訊號位準為何，此狀態被維持著。 As shown at the third layer, after the lapse of a predetermined period that starts when the power supply voltage VDD1 is turned on, when the regular request signal RT12 temporarily becomes the H level, the voltage of the storage node N2 transitions to the H level. Therefore, the voltage of the storage node N1 shifts to the L level. Then, by the inverter IN22 and the NAND gate ND, the voltage of the storage node N1 is latched at the L level and the voltage of the storage node N2 is latched at the H level. Regardless of the signal level of the regular request signal RT12, this state is maintained.

據此，如同在第四層處所示，停止訊號STP從L位 準轉變至H位準。在停止訊號STP為L位準的周期期間，輸出脈波訊號P11,P12的輸出被停止。當停止訊號STP切換至H位準時，輸出脈波訊號P11,P12的輸出停止被解除。 According to this, as shown at the fourth layer, the stop signal STP from the L bit To the H level. During the period when the stop signal STP is at the L level, the output of the output pulse signals P11 and P12 is stopped. When the stop signal STP is switched to the H level, the output stop of the output pulse signals P11 and P12 is released.

依此方式，由反相器IN22和非及(NAND)閘ND所建構之鎖存器電路感測電源電壓的啟動，並且使停止訊號STP維持在L位準。然後，鎖存器電路依據輸出自為計時器之計數器CTR1之規律的請求訊號RT12而使停止訊號STP切換至H位準。 In this way, the latch circuit constructed by the inverter IN22 and the NAND gate ND senses the start of the power supply voltage and maintains the stop signal STP at the L level. Then, the latch circuit switches the stop signal STP to the H level according to the regular request signal RT12 output from the counter CTR1 which is a timer.

類似於依據第一實施例之發射器電路TX1，依據第三實施例之發射器電路TX1包含輸出停止電路30，其使輸出脈波訊號P11和輸出脈波訊號P12的輸出停止一段從當電源電壓VDD1被開啟時開始的預定周期。因此，與電源電壓VDD1相關聯之錯誤訊號的輸出可以被抑制。在靜電放電損壞測試時該電源電壓VDD1上的增加為類似於該電源電壓VDD1的開啟之物理現象。因而，在靜電放電損壞測試時也，該輸出停止電路30啟動，並且歸因於與該電源電壓VDD1上的增加相關聯之錯誤脈波的任何失效能夠被抑制。 Similar to the transmitter circuit TX1 according to the first embodiment, the transmitter circuit TX1 according to the third embodiment includes an output stop circuit 30, which stops the output of the output pulse signal P11 and the output pulse signal P12 for a period from the current power supply voltage The predetermined period that starts when VDD1 is turned on. Therefore, the output of the error signal associated with the power supply voltage VDD1 can be suppressed. The increase in the power supply voltage VDD1 during the electrostatic discharge damage test is a physical phenomenon similar to the turn-on of the power supply voltage VDD1. Therefore, also in the electrostatic discharge damage test, the output stop circuit 30 is activated, and any failure due to an erroneous pulse wave associated with the increase in the power supply voltage VDD1 can be suppressed.

有了依據第三實施例之輸出停止電路30，因為停止周期係由為計時器之計數器CTR1來予以決定，所以停止周期上的變動可以被減小。此外，因為電容器元件C1,C2並未有助於停止周期，所以可達成尺寸上的縮減。舉例來說，尺寸可藉由使用電晶體的閘極容量做為電容器元件 C1,C2而被進一步縮減。此外，並不需要重新設置計時器且既有的元件也可被使用。因而，晶片面積整體上可被縮減。 With the output stop circuit 30 according to the third embodiment, since the stop period is determined by the counter CTR1 which is a timer, the variation in the stop period can be reduced. In addition, since the capacitor elements C1 and C2 do not contribute to the stop period, a reduction in size can be achieved. For example, the size can be used as the capacitor element by using the gate capacity of the transistor C1, C2 were further reduced. In addition, there is no need to reset the timer and existing components can also be used. Thus, the wafer area can be reduced as a whole.

此外，因為停止訊號STP在輸出停止解除之後藉由反相器IN22和非及(NAND)閘ND而被鎖存在H位準，所以在正常操作上展現出優異的抗噪性。 In addition, since the stop signal STP is latched at the H level by the inverter IN22 and the NAND gate ND after the output stop is released, it exhibits excellent noise resistance in normal operation.

<半導體裝置系統2的結構> <Structure of Semiconductor Device System 2>

接著，參照圖19，將說明使用依據第三實施例之發射器電路TX1的半導體裝置系統2。圖19為用來顯示依據第三實施例之半導體裝置系統2的方塊圖。依據第三實施例之半導體裝置系統2包含兩個發射器電路TX1,TX2、主要線圈L11,L21、次要線圈L12,L22、兩個接收器電路RX1,RX2、兩個振盪器電路OSC1,OSC2、兩個計數器CTR1,CTR2、兩個計時器TM1,TM2、兩個欠電壓鎖定(UVLO)電路UVLO1,UVLO2、兩個及(AND)閘A1,A2、及六個或(OR)閘O1至O6。 Next, referring to FIG. 19, a semiconductor device system 2 using the transmitter circuit TX1 according to the third embodiment will be described. FIG. 19 is a block diagram showing the semiconductor device system 2 according to the third embodiment. The semiconductor device system 2 according to the third embodiment includes two transmitter circuits TX1, TX2, primary coils L11, L21, secondary coils L12, L22, two receiver circuits RX1, RX2, two oscillator circuits OSC1, OSC2 , Two counters CTR1, CTR2, two timers TM1, TM2, two undervoltage lockout (UVLO) circuits UVLO1, UVLO2, two AND gates A1, A2, and six OR gates O1 to O6.

在此，發射器電路TX1,TX2和已參照圖3予以說明之依據第一實施例的發射器電路TX1被類似地建構。在此，發射器電路TX1,TX2各自包含圖17中所示之依據第三實施例的輸出停止電路30。此外，接收器電路RX1,RX2和已參照圖5予以說明之依據第一實施例的接收器電路RX1被類似地建構。依據第三實施例之半導體裝置系統2為應用於功率電晶體之控制系統之微隔離器的實例。 Here, the transmitter circuits TX1, TX2 and the transmitter circuit TX1 according to the first embodiment, which has been described with reference to FIG. 3, are similarly constructed. Here, the transmitter circuits TX1, TX2 each include the output stop circuit 30 according to the third embodiment shown in FIG. In addition, the receiver circuits RX1, RX2 and the receiver circuit RX1 according to the first embodiment that have been described with reference to FIG. 5 are constructed similarly. The semiconductor device system 2 according to the third embodiment is an example of a micro-isolator applied to a control system of power transistors.

首先，將說明訊號的實質結構和流動。 First, the actual structure and flow of the signal will be explained.

輸出自微電腦MCU的控制訊號CNT1被輸入至發射器電路TX1作為輸入資料訊號Din1。此外，輸出自UVLO電路UVLO1之非規律的(irregular)請求訊號RT11和輸出自計數器CTR1之規律的請求訊號RT12也被輸入至該發射器電路TX1。 The control signal CNT1 output from the microcomputer MCU is input to the transmitter circuit TX1 as the input data signal Din1. In addition, an irregular request signal RT11 output from the UVLO circuit UVLO1 and a regular request signal RT12 output from the counter CTR1 are also input to the transmitter circuit TX1.

輸出自發射器電路TX1之輸出脈波訊號P11,P12經由主要線圈L11和次要線圈L12而被發送至接收器電路RX1，該接收器電路RX1重新建構來自所接收到之訊號中的資料訊號，並且輸出作為輸出資料訊號Dout1，該輸出資料訊號Dout1被輸入至功率電晶體驅動器PTD作為控制訊號CNT2。 The output pulse signals P11, P12 output from the transmitter circuit TX1 are sent to the receiver circuit RX1 through the primary coil L11 and the secondary coil L12, and the receiver circuit RX1 reconstructs the data signal from the received signal, And output as the output data signal Dout1, the output data signal Dout1 is input to the power transistor driver PTD as the control signal CNT2.

也就是說，輸出自微電腦MCU的控制訊號CNT1經由發射器電路TX1和接收器電路RX1而被輸入至功率電晶體驅動器PTD作為控制訊號CNT2。 That is, the control signal CNT1 output from the microcomputer MCU is input to the power transistor driver PTD as the control signal CNT2 through the transmitter circuit TX1 and the receiver circuit RX1.

另一方面，輸出自錯誤偵測電路EDC之錯誤偵測訊號ED1被輸入至發射器電路TX2作為輸入資料訊號Din2。此外，輸出自UVLO電路UVLO2之非規律的請求訊號RT21和輸出自計數器CTR2之規律的請求訊號RT22也被輸入至該發射器電路TX2。 On the other hand, the error detection signal ED1 output from the error detection circuit EDC is input to the transmitter circuit TX2 as the input data signal Din2. In addition, the irregular request signal RT21 output from the UVLO circuit UVLO2 and the regular request signal RT22 output from the counter CTR2 are also input to the transmitter circuit TX2.

輸出自發射器電路TX2之輸出脈波訊號P21,P22經由主要線圈L21和次要線圈L22而被發送至接收器電路RX2，該接收器電路RX2重新建構來自所接收到之訊號中的資料訊號，並且輸出作為輸出資料訊號Dout2，該輸出 資料訊號Dout2被輸入至微電腦MCU作為錯誤偵測訊號ED2。 The output pulse signals P21, P22 output from the transmitter circuit TX2 are sent to the receiver circuit RX2 through the primary coil L21 and the secondary coil L22, and the receiver circuit RX2 reconstructs the data signal from the received signal, And output as the output data signal Dout2, the output The data signal Dout2 is input to the microcomputer MCU as the error detection signal ED2.

也就是說，輸出自錯誤偵測電路EDC的錯誤偵測訊號ED1經由發射器電路TX2和接收器電路RX2而被輸入至微電腦MCU作為錯誤偵測訊號ED2。 That is, the error detection signal ED1 output from the error detection circuit EDC is input to the microcomputer MCU via the transmitter circuit TX2 and the receiver circuit RX2 as the error detection signal ED2.

<半導體裝置系統2的細節> <Details of semiconductor device system 2>

下面，將說明詳細的結構和訊號的流動。 Next, the detailed structure and signal flow will be explained.

輸出自微電腦MCU的控制訊號CNT1經由及(AND)閘A1而被輸入至發射器電路TX1作為輸入資料訊號Din1。在此，輸出自UVLO電路UVLO1之非規律的請求訊號RT11的反相訊號也輸入至及(AND)閘A1。 The control signal CNT1 output from the microcomputer MCU is input to the transmitter circuit TX1 via the AND gate A1 as the input data signal Din1. Here, the inverted signal of the irregular request signal RT11 output from the UVLO circuit UVLO1 is also input to the AND gate A1.

在正常狀態中，非規律的請求訊號RT11為L位準，並且在電源電壓減小的不正常狀態中變成H位準。也就是說，在非規律的請求訊號RT11為L位準之正常狀態中，輸出自微電腦MCU的控制訊號CNT1被輸入至發射器電路TX1作為輸入資料訊號Din1。另一方面，在非規律的請求訊號RT11為H位準之不正常狀態中，藉由及(AND)閘A1，輸出自微電腦MCU之控制訊號CNT1的輸入至發射器電路TX1被阻斷。 In the normal state, the irregular request signal RT11 is at the L level, and becomes the H level in the abnormal state where the power supply voltage is reduced. In other words, in the normal state where the irregular request signal RT11 is at the L level, the control signal CNT1 output from the microcomputer MCU is input to the transmitter circuit TX1 as the input data signal Din1. On the other hand, in the abnormal state where the irregular request signal RT11 is at the H level, the input of the control signal CNT1 output from the microcomputer MCU to the transmitter circuit TX1 is blocked by the AND gate A1.

此外，非規律的請求訊號RT11也被輸入至發射器電路TX1。在其中之非規律的請求訊號RT11從L位準轉變至H位準或從H位準轉變至L位準的時序時，輸入資料訊號Din1(控制訊號CNT1)的值從發射器電路TX1被重 新發送至接收器電路RX1。也就是說，不僅當電源電壓減小時，而且也在其中之電源電壓藉由被開啟而增加並且轉變至正常值的時序時，發送側上之資料訊號的值及接收側上之資料訊號的值被同步化。 In addition, the irregular request signal RT11 is also input to the transmitter circuit TX1. At the timing when the irregular request signal RT11 changes from L level to H level or from H level to L level, the value of the input data signal Din1 (control signal CNT1) is reset from the transmitter circuit TX1 Newly sent to the receiver circuit RX1. That is, not only when the power supply voltage decreases, but also when the power supply voltage increases and turns to the normal timing by being turned on, the value of the data signal on the sending side and the value of the data signal on the receiving side Be synchronized.

輸出自計數器CTR1之規律的請求訊號RT12被輸入至發射器電路TX1，該規律的請求訊號RT12為，舉例來說，在輸出自振盪器電路OSC1之時脈訊號的每10個計數時變成H位準的訊號。例如，當自振盪器電路OSC1輸出10MHz的時脈訊號時，計數器CTR1產生1μs-周期(1MHz)之規律的請求訊號RT12。藉由規律的請求訊號RT12，即使當資料值沒有任何改變時，該資料值被重新發送於每10個計數。因此，即使當由接收器電路RX1所重新建構的資料值藉由雜訊等等而被反轉時，正確的值可以被快速地重新獲得(recover)。 The regular request signal RT12 output from the counter CTR1 is input to the transmitter circuit TX1. The regular request signal RT12 is, for example, changed to the H bit every 10 counts of the clock signal output from the oscillator circuit OSC1 Accurate signal. For example, when a 10 MHz clock signal is output from the oscillator circuit OSC1, the counter CTR1 generates a regular request signal RT12 of 1 μs-cycle (1 MHz). With the regular request signal RT12, even when there is no change in the data value, the data value is retransmitted every 10 counts. Therefore, even when the data value reconstructed by the receiver circuit RX1 is inverted by noise or the like, the correct value can be quickly recovered.

此外，如上所述，輸出自計數器CTR1之規律的請求訊號RT12依據圖17中所示的第三實施例而被輸入至輸出停止電路30的非及(NAND)閘ND。 In addition, as described above, the regular request signal RT12 output from the counter CTR1 is input to the NAND gate ND of the output stop circuit 30 according to the third embodiment shown in FIG. 17.

計數器CTR1藉由脈波訊號P10或輸出自UVLO電路UVLO1之非規律的請求訊號RT11而被重設。也就是說，計數器CTR1藉由輸出自或(OR)閘O1的重設訊號RST1而被重設，而或(OR)閘O1的輸入為脈波訊號P10和非規律的請求訊號RT11。 The counter CTR1 is reset by the pulse signal P10 or the irregular request signal RT11 output from the UVLO circuit UVLO1. That is, the counter CTR1 is reset by the reset signal RST1 output from the OR gate O1, and the input of the OR gate O1 is the pulse signal P10 and the irregular request signal RT11.

發射器電路TX1根據輸入資料訊號Din1而輸出輸出脈波訊號P11,P12，輸出脈波訊號P11,P12經由主要線圈 L11和次要線圈L12而被輸入至接收器電路RX1，接收器電路RX1重新建構該資料訊號，並且輸出作為輸出資料訊號Dout1。注意，細節係如同在第一實施例所述者。 The transmitter circuit TX1 outputs and outputs pulse signals P11 and P12 according to the input data signal Din1, and outputs pulse signals P11 and P12 via the main coil L11 and the secondary coil L12 are input to the receiver circuit RX1, and the receiver circuit RX1 reconstructs the data signal and outputs it as the output data signal Dout1. Note that the details are as described in the first embodiment.

輸出資料訊號Dout1經由及(AND)閘A2而被輸入至功率電晶體驅動器PTD。在此，輸出自UVLO電路UVLO2之非規律的請求訊號RT21的反相訊號被輸入至及(AND)閘A2。此外，輸出自計時器TM1之逾時(timeout)訊號TO1的反相訊號被輸入至及(AND)閘A2。 The output data signal Dout1 is input to the power transistor driver PTD through the AND gate A2. Here, the inverted signal of the irregular request signal RT21 output from the UVLO circuit UVLO2 is input to the AND gate A2. In addition, the inverted signal of the timeout signal TO1 output from the timer TM1 is input to the AND gate A2.

非規律的請求訊號RT21在正常狀態中為L位準，並且當電源電壓減小時變成H位準。此外，逾時訊號TO1在正常狀態中亦為L位準，並且當在預定周期(例如，40個計數)的流逝之後並未偵測到脈波偵測位訊號PD1時變成H位準。也就是說，在非規律的請求訊號RT21和逾時訊號TO1為L位準的正常狀態中，輸出資料訊號Dout1被輸入至功率電晶體驅動器PTD。另一方面，當非規律的請求訊號RT21或逾時訊號TO1切換至H位準時，藉由及(AND)閘A2，輸入至功率電晶體驅動器PTD的輸出資料訊號Dout1的輸入被阻斷。此外，逾時訊號TO1重設該接收器電路RX1。注意，在正常操作模式中，在來自發射器電路TX1之每10個計數時，藉由規律的請求訊號RT12而重新發送該資料值，並且從該接收器電路RX1輸出脈波偵測位訊號PD1。因此，計時器TM1將不會到達40個計數。另一方面，在其中發射器電路TX1停止等的 情況中，逾時訊號TO1被輸出。藉由規律的請求訊號RT12，在該發射器電路TX1的操作中的異常能夠被偵測到。 The irregular request signal RT21 is L level in the normal state, and becomes H level when the power supply voltage is reduced. In addition, the timeout signal TO1 is also at the L level in the normal state, and becomes the H level when the pulse wave detection bit signal PD1 is not detected after the lapse of a predetermined period (for example, 40 counts). That is, in the normal state where the irregular request signal RT21 and the timeout signal TO1 are at the L level, the output data signal Dout1 is input to the power transistor driver PTD. On the other hand, when the irregular request signal RT21 or the timeout signal TO1 is switched to the H level, the input data signal Dout1 input to the power transistor driver PTD is blocked by the AND gate A2. In addition, the timeout signal TO1 resets the receiver circuit RX1. Note that in the normal operation mode, at every 10 counts from the transmitter circuit TX1, the data value is retransmitted by the regular request signal RT12, and the pulse detection bit signal PD1 is output from the receiver circuit RX1 . Therefore, the timer TM1 will not reach 40 counts. On the other hand, in which the transmitter circuit TX1 stops, etc. In this case, the time-out signal TO1 is output. With the regular request signal RT12, abnormalities in the operation of the transmitter circuit TX1 can be detected.

在此，計時器TM1計算輸出自振盪器電路OSC2之時脈訊號的數目。此外，藉由輸出自該接收器電路RX1的脈波偵測位訊號PD1或輸出自UVLO電路UVLO2之非規律的請求訊號RT21來重設計時器TM1。也就是說，藉由輸出自輸出自或(OR)閘O2的重設訊號RST2來重設計時器TM1，而或(OR)閘O2的輸入為脈波偵測訊號PD1和非規律的請求訊號RT21。 Here, the timer TM1 counts the number of clock signals output from the oscillator circuit OSC2. In addition, the timer TM1 is reset by the pulse detection bit signal PD1 output from the receiver circuit RX1 or the irregular request signal RT21 output from the UVLO circuit UVLO2. That is, the timer TM1 is reset by the reset signal RST2 output from the OR gate O2, and the input of the OR gate O2 is the pulse detection signal PD1 and the irregular request signal RT21.

另一方面，輸出自錯誤偵測電路EDC之錯誤偵測訊號ED1經由或(OR)閘O5而被輸入至發射器電路TX2作為輸入資料訊號Din2。錯誤偵測訊號ED1在正常狀態中為L位準，並且在其中偵測到任何錯誤的異常狀態中變成H位準。在此，輸出自UVLO電路UVLO2之非規律的請求訊號RT21也被輸入至該或(OR)閘O5，該非規律的請求訊號RT21在正常狀態中為L位準，並且在其中電源電壓減小的異常狀態中變成H位準。也就是說，該非規律的請求訊號RT21也做為錯誤訊號而和該錯誤偵測訊號ED1一起被輸入至發射器電路TX2。 On the other hand, the error detection signal ED1 output from the error detection circuit EDC is input to the transmitter circuit TX2 via the OR gate O5 as the input data signal Din2. The error detection signal ED1 is L level in the normal state, and becomes H level in the abnormal state in which any error is detected. Here, the irregular request signal RT21 output from the UVLO circuit UVLO2 is also input to the OR gate O5. The irregular request signal RT21 is at the L level in the normal state, and the power supply voltage decreases In abnormal state, it becomes H level. In other words, the irregular request signal RT21 is also used as an error signal and is input to the transmitter circuit TX2 together with the error detection signal ED1.

此外，該非規律的請求訊號RT21也被輸入至發射器電路TX2。在其中之該非規律的請求訊號RT21從L位準轉變至H位準或從H位準轉變至L位準的時序時，輸入資料訊號Din2的值從發射器電路TX2被重新發送至接收 器電路RX2。也就是說，不僅當電源電壓減小時，而且也在其中之電源電壓藉由被開啟而增加並且轉變至正常值的時序時，發送側上之資料訊號的值及接收側上之資料訊號的值被同步化。 In addition, the irregular request signal RT21 is also input to the transmitter circuit TX2. At the timing when the irregular request signal RT21 changes from L level to H level or from H level to L level, the value of the input data signal Din2 is retransmitted from the transmitter circuit TX2 to the receiving 器电路RX2. That is, not only when the power supply voltage decreases, but also when the power supply voltage increases and turns to the normal timing by being turned on, the value of the data signal on the sending side and the value of the data signal on the receiving side Be synchronized.

此外，輸出自計數器CTR2之規律的請求訊號RT22被輸入至發射器電路TX2，該規律的請求訊號RT22為，舉例來說，在輸出自振盪器電路OSC2之時脈訊號的每10個計數時變成H位準的訊號。藉由規律的請求訊號RT22，即使當資料值沒有任何改變時，該資料值被重新發送於每10個計數。因此，即使當由接收器電路RX2所重新建構的資料值藉由雜訊等等而被反轉時，正確的值可以被快速地重新獲得。 In addition, a regular request signal RT22 output from the counter CTR2 is input to the transmitter circuit TX2. The regular request signal RT22 is, for example, becomes every 10 counts of the clock signal output from the oscillator circuit OSC2 H level signal. With the regular request signal RT22, even when there is no change in the data value, the data value is retransmitted every 10 counts. Therefore, even when the data value reconstructed by the receiver circuit RX2 is inverted by noise or the like, the correct value can be quickly recovered.

此外，計數器CTR2藉由脈波訊號P20或輸出自UVLO電路UVLO2之非規律的請求訊號RT21而被重設。也就是說，計數器CTR2藉由輸出自或(OR)閘O3的重設訊號RST3而被重設，而或(OR)閘O3的輸入為脈波訊號P20和非規律的請求訊號RT21。 In addition, the counter CTR2 is reset by the pulse signal P20 or the irregular request signal RT21 output from the UVLO circuit UVLO2. That is, the counter CTR2 is reset by the reset signal RST3 output from the OR gate O3, and the input of the OR gate O3 is the pulse signal P20 and the irregular request signal RT21.

發射器電路TX2根據輸入資料訊號Din2而輸出輸出脈波訊號P21,P22，該等輸出脈波訊號P21,P22經由主要線圈L21和次要線圈L22而被輸入至接收器電路RX2，接收器電路RX2重新建構該資料訊號，並且輸出作為該輸出資料訊號Dout2。 The transmitter circuit TX2 outputs and outputs pulse signals P21 and P22 according to the input data signal Din2. The output pulse signals P21 and P22 are input to the receiver circuit RX2 and the receiver circuit RX2 through the primary coil L21 and the secondary coil L22. The data signal is reconstructed and output as the output data signal Dout2.

輸出資料訊號Dout2經由或(OR)閘O6而被輸入至微電腦MCU。在此，輸出自UVLO電路UVLO1之非規律 的請求訊號RT11被輸入至或(OR)閘O6。此外，輸出自計時器TM2之逾時訊號TO2被輸入至或(OR)閘O6。也就是說，該非規律的請求訊號RT11和逾時訊號TO2做為錯誤偵測訊號ED2而與該輸出資料訊號Dout2一起被輸入至該微電腦MCU。 The output data signal Dout2 is input to the microcomputer MCU via the OR gate O6. Here, the irregularity output from the UVLO circuit UVLO1 The request signal RT11 is input to the OR gate O6. In addition, the time-out signal TO2 output from the timer TM2 is input to the OR gate O6. In other words, the irregular request signal RT11 and the time-out signal TO2 are input to the microcomputer MCU as the error detection signal ED2 together with the output data signal Dout2.

在此，逾時訊號TO2在正常狀態中為L位準，並且當在預定周期(例如，40個計數)的流逝之後並未偵測到脈波偵測位訊號PD2時變成H位準。此外，逾時訊號TO2重設該接收器電路RX2。注意，在正常操作模式中，在來自發射器電路TX2之每10個計數時，藉由規律的請求訊號RT22而重新發送該資料值，並且從該接收器電路RX2輸出脈波偵測位訊號PD2。因此，計時器TM2將不會到達40個計數。另一方面，在其中發射器電路TX2停止等的情況中，逾時訊號TO2被輸出。藉由規律的請求訊號RT22，在該發射器電路TX2的操作中的異常能夠被偵測到。 Here, the timeout signal TO2 is at the L level in the normal state, and becomes the H level when the pulse wave detection bit signal PD2 is not detected after the lapse of a predetermined period (for example, 40 counts). In addition, the timeout signal TO2 resets the receiver circuit RX2. Note that in the normal operation mode, at every 10 counts from the transmitter circuit TX2, the data value is retransmitted by the regular request signal RT22, and the pulse detection bit signal PD2 is output from the receiver circuit RX2 . Therefore, the timer TM2 will not reach 40 counts. On the other hand, in the case where the transmitter circuit TX2 stops, etc., the time-out signal TO2 is output. With the regular request signal RT22, anomalies in the operation of the transmitter circuit TX2 can be detected.

在此，計時器TM2計算輸出自振盪器電路OSC1之時脈訊號的數目。此外，藉由輸出自該接收器電路RX2的脈波偵測位訊號PD2或輸出自UVLO電路UVLO1之非規律的請求訊號RT11來重設計時器TM2。也就是說，藉由輸出自輸出自或(OR)閘O4的重設訊號RST4來重設計時器TM2，而或(OR)閘O4的輸入為脈波偵測訊號PD2和非規律的請求訊號RT11。 Here, the timer TM2 counts the number of clock signals output from the oscillator circuit OSC1. In addition, the timer TM2 is reset by the pulse detection bit signal PD2 output from the receiver circuit RX2 or the irregular request signal RT11 output from the UVLO circuit UVLO1. That is, the timer TM2 is reset by the reset signal RST4 output from the OR gate O4, and the input of the OR gate O4 is the pulse detection signal PD2 and the irregular request signal RT11.

<半導體裝置系統2的示範應用> <Demonstration Application of Semiconductor Device System 2>

半導體裝置系統2的控制目標為，舉例來說，由絕緣閘雙載子電晶體(IGBT)所代表之功率電晶體。在此情況中，半導體裝置系統2依據由接收器電路RX1所再生之輸出資料訊號Dout1來控制功率電晶體的開啟/關斷(ON/OFF)，以控制電源與負載之間的導通狀態。 The control target of the semiconductor device system 2 is, for example, a power transistor represented by an insulated gate double carrier transistor (IGBT). In this case, the semiconductor device system 2 controls the ON/OFF of the power transistor according to the output data signal Dout1 regenerated by the receiver circuit RX1 to control the conduction state between the power supply and the load.

明確地說，依據第三實施例之半導體裝置系統2被應用至，舉例來說，驅動如圖20所示之三相馬達(負載)的反相器裝置。圖20為顯示應用該半導體裝置系統2之反相器裝置的示圖。圖20中所示之反相器裝置在其高側和低側各自包含三個功率電晶體驅動器PTD及三個錯誤偵測電路EDC，其分別對應於u-相、v-相、及w-相(總共六個)。 Specifically, the semiconductor device system 2 according to the third embodiment is applied to, for example, an inverter device that drives a three-phase motor (load) as shown in FIG. 20. FIG. 20 is a diagram showing an inverter device to which the semiconductor device system 2 is applied. The inverter device shown in FIG. 20 includes three power transistor drivers PTD and three error detection circuits EDC on its high side and low side, which respectively correspond to u-phase, v-phase, and w- Phase (six in total).

輸出自微電腦MCU的控制訊號(例如，UH,UL)經由該等發射器電路TX1、線圈、及該等接收器電路RX1而被發送至該等功率電晶體驅動器PTD，並且為控制目標之IGBTs的開啟/關斷(ON/OFF)被控制。另一方面，由該等錯誤偵測電路EDC所偵測到之錯誤訊號經由該等發射器電路TX2、該等線圈、及該等接收器電路RX2而被發送至該微電腦MCU。 The control signals (for example, UH, UL) output from the microcomputer MCU are sent to the power transistor drivers PTD through the transmitter circuits TX1, the coils, and the receiver circuits RX1, and are used to control the target IGBTs. ON/OFF is controlled. On the other hand, the error signals detected by the error detection circuits EDC are sent to the microcomputer MCU via the transmitter circuits TX2, the coils, and the receiver circuits RX2.

在此，圖21為顯示應用該半導體裝置系統2之反相器裝置之操作的時序圖。如同圖21之圖表中所示，輸出自微電腦MCU的控制訊號(例如，UH,UL)為PWM控制訊號，並且以類比方式來控制流經馬達之電流(例如， IU)。在此，控制訊號(例如，UH,UL)對應於該輸入資料訊號Din1。 Here, FIG. 21 is a timing chart showing the operation of the inverter device to which the semiconductor device system 2 is applied. As shown in the graph of FIG. 21, the control signals (for example, UH, UL) output from the microcomputer MCU are PWM control signals, and the current flowing through the motor is controlled in an analog manner (for example, IU). Here, the control signal (for example, UH, UL) corresponds to the input data signal Din1.

(其他實施例) (Other embodiments)

半導體裝置的安裝實例並不限於圖2中所示者。下面，參照圖22及23來說明半導體裝置的其他代表性安裝實例。圖22為在電容器被使用作為絕緣耦合元件的情況中之半導體裝置的安裝實例，圖23顯示其中GMR(巨磁阻)元件被使用作為絕緣耦合元件的情況中之半導體裝置的安裝實例。 The mounting example of the semiconductor device is not limited to that shown in FIG. 2. Next, other representative mounting examples of semiconductor devices will be described with reference to FIGS. 22 and 23. 22 is a mounting example of a semiconductor device in the case where a capacitor is used as an insulating coupling element, and FIG. 23 shows a mounting example of a semiconductor device in a case where a GMR (giant magnetoresistive) element is used as an insulating coupling element.

在圖22中，用作為圖2中所示的安裝實例中之絕緣耦合元件的線圈被電容器所取代。更明確地說，主要線圈L11被電容器的其中一個電極PL1所取代，並且次要線圈L12被電容器的另一個電極PL2所取代。 In FIG. 22, the coil used as the insulating coupling element in the mounting example shown in FIG. 2 is replaced with a capacitor. More specifically, the primary coil L11 is replaced by one electrode PL1 of the capacitor, and the secondary coil L12 is replaced by the other electrode PL2 of the capacitor.

在圖23中，用作為圖2中所示的安裝實例中之絕緣耦合元件的線圈被GMR(巨磁阻)元件所取代。更明確地說，在主要線圈L11保持不變的同時，次要線圈L12被GMR(巨磁阻)元件R12所取代。在此安裝實例中也，連接至該發射器電路TX1之該等輸出的墊塊(pad)被形成於半導體晶片CHP1處，並且分別連接至主要線圈L11之相反末端的墊塊被形成於半導體晶片CHP2處。然後，該發射器電路TX1經由該等墊塊和接合線BW而連接至形成在半導體晶片CHP2處的該主要線圈L11。 In FIG. 23, the coil used as the insulating coupling element in the mounting example shown in FIG. 2 is replaced with a GMR (giant magnetoresistive) element. More specifically, while the primary coil L11 remains unchanged, the secondary coil L12 is replaced by a GMR (giant magnetoresistive) element R12. Also in this installation example, pads connected to the outputs of the transmitter circuit TX1 are formed at the semiconductor wafer CHP1, and pads respectively connected to opposite ends of the main coil L11 are formed at the semiconductor wafer CHP2. Then, the transmitter circuit TX1 is connected to the main coil L11 formed at the semiconductor wafer CHP2 via the pads and the bonding wires BW.

如上所述，該等絕緣耦合元件的類型和配置並不被特 別限定。注意，雖然已經說明該等絕緣耦合元件被形成於半導體晶片處，但是該等絕緣耦合元件也可以被形成為外部附接組件。 As mentioned above, the type and configuration of these insulating coupling elements are not Don't limit it. Note that although it has been described that the insulating coupling elements are formed at the semiconductor wafer, the insulating coupling elements may also be formed as external attachment components.

上面，雖然由本案發明人所做成的發明已經根據該等實施例來加以明確地說明，但是本發明並不限定於上面所述的該等實施例，而且不用說，在不違離本發明之精神的範圍之內可做成各式各樣的改變。 In the above, although the invention made by the inventor of the present application has been clearly described based on the embodiments, the present invention is not limited to the embodiments described above, and needless to say, without departing from the present invention Various changes can be made within the scope of the spirit.

舉例來說，隨著依據該等實施例的半導體裝置，半導體基板、半導體層、擴散層(擴散區域)等等的導電類型(p-型或n-型)可以被反轉。因此，在n-型和p-型的其中一個導電類型為第一導電類型且另一個導電類型為第二導電類型的情況中，第一導電類型可為p-型，而且第二導電類型可為n-型。相反地，第一導電類型可為n-型，而且第二導電類型可為p-型。 For example, with the semiconductor devices according to the embodiments, the conductivity types (p-type or n-type) of the semiconductor substrate, semiconductor layer, diffusion layer (diffusion region), etc. can be reversed. Therefore, in the case where one of the n-type and p-type conductivity types is the first conductivity type and the other conductivity type is the second conductivity type, the first conductivity type may be p-type, and the second conductivity type may be It is n-type. Conversely, the first conductivity type may be n-type, and the second conductivity type may be p-type.

第一至第三和其他實施例可視習於此技藝者所想要的來予以組合。 The first to third and other embodiments can be combined as desired by those skilled in the art.

雖然本發明已經按照幾個實施例來加以說明，但是習於此技藝者可認知本發明在附加之申請專利範圍的精神和範疇之內用各式各樣的變型來予以施行，而且本發明並不限定於上面所述的該等實例。 Although the present invention has been described according to several embodiments, those skilled in the art can recognize that the present invention can be implemented with various modifications within the spirit and scope of the additional patent application scope, and the present invention does not It is not limited to the examples described above.

此外，申請專利範圍的範疇並不限定於上面所述的該等實施例。 In addition, the scope of the patent application scope is not limited to the above-mentioned embodiments.

再者，注意到，申請人想要包含所有請求項元件的等同之物，甚至連稍後在審查過程期間所做之任何申請專利 範圍的修正亦被包含在內。 Furthermore, it was noted that the applicant wanted to include the equivalent of all the requested elements, and even any patent applications made later during the examination process Scope amendments are also included.

TX1‧‧‧發射器電路 TX1‧‧‧Transmitter circuit

L11‧‧‧主要線圈 L11‧‧‧Main coil

L12‧‧‧次要線圈 L12‧‧‧ Secondary coil

RX1‧‧‧接收器電路 RX1‧‧‧ receiver circuit

CHP1、CHP2‧‧‧半導體晶片 CHP1, CHP2 ‧‧‧ semiconductor chip

VDD1、VDD2‧‧‧電源電壓 VDD1, VDD2 ‧‧‧ power supply voltage

GND1、GND2‧‧‧接地電壓 GND1, GND2‧‧‧Ground voltage

1‧‧‧半導體裝置 1‧‧‧Semiconductor device

PGC‧‧‧脈波產生電路 PGC‧‧‧Pulse Wave Generation Circuit

OD1、OD2‧‧‧輸出驅動器 OD1, OD2‧‧‧ output driver

10‧‧‧輸出停止電路 10‧‧‧Output stop circuit

P10‧‧‧脈波訊號 P10‧‧‧Pulse signal

P11、P12‧‧‧輸出脈波訊號 P11, P12‧‧‧Output pulse signal

Din1‧‧‧輸入資料訊號 Din1‧‧‧Input data signal

VR‧‧‧接收訊號 VR‧‧‧Receive signal

STP‧‧‧停止訊號 STP‧‧‧Stop signal

Dout1‧‧‧輸出資料訊號 Dout1‧‧‧Output data signal

Claims (9)

一種發射器電路，包括：脈波產生電路，根據輸入資料的複數個邊緣而產生脈波訊號；第一輸出驅動器，根據該脈波訊號，依據該等邊緣的其中一個邊緣而將第一輸出脈波訊號輸出至外部絕緣耦合元件之第一端；第二輸出驅動器，根據該脈波訊號，依據該等邊緣的另一個邊緣而將第二輸出脈波訊號輸出至該絕緣耦合元件之第二端；以及輸出停止電路，使該第一及第二輸出脈波訊號停止被輸出於一段從當電源電壓被開啟時開始的預定期間，其中，該輸出停止電路包含：鎖存器電路，感測該電源電壓的該開啟並且維持該第一及第二輸出脈波訊號之該輸出的該停止；以及計時器，其中回應於輸出自該計時器的訊號，該鎖存器電路解除該第一及第二輸出脈波訊號之該輸出的該停止，該輸出停止電路另包含第一及第二電容器元件，該鎖存器電路具有經由該第一電容器元件而被連接至電源的第一儲存節點，並且具有經由該第二電容器元件而被接地的第二儲存節點，該鎖存器電路分別在該第一及第二儲存節點保持彼此倒反的電壓，以及 回應於輸出自該計時器的該訊號，該鎖存器電路藉由在該第一及第二儲存節點轉變時所保持的該等電壓而解除該第一及第二輸出脈波訊號之該輸出的該停止。 A transmitter circuit includes: a pulse wave generating circuit that generates a pulse wave signal according to a plurality of edges of input data; a first output driver, based on the pulse wave signal, outputs a first pulse according to one of the edges The wave signal is output to the first end of the external insulating coupling element; the second output driver outputs the second output pulse signal to the second end of the insulating coupling element according to the pulse signal and the other of the edges And an output stop circuit to stop the first and second output pulse signals from being output for a predetermined period from when the power supply voltage is turned on, wherein the output stop circuit includes: a latch circuit to sense the The turning on of the power supply voltage and maintaining the stopping of the output of the first and second output pulse signals; and a timer, wherein in response to the signal output from the timer, the latch circuit releases the first and second The stop of the output of the two-output pulse signal, the output stop circuit further includes first and second capacitor elements, the latch circuit has a first storage node connected to the power supply through the first capacitor element, and Having a second storage node that is grounded via the second capacitor element, the latch circuit maintains mutually inverted voltages at the first and second storage nodes, and In response to the signal output from the timer, the latch circuit releases the output of the first and second output pulse signals by the voltages held when the first and second storage nodes transition The stop. 一種發射器電路，包括：脈波產生電路，根據輸入資料的複數個邊緣而產生脈波訊號；第一輸出驅動器，根據該脈波訊號，依據該等邊緣的其中一個邊緣而將第一輸出脈波訊號輸出至外部絕緣耦合元件之第一端；第二輸出驅動器，根據該脈波訊號，依據該等邊緣的另一個邊緣而將第二輸出脈波訊號輸出至該絕緣耦合元件之第二端；以及輸出停止電路，使該第一及第二輸出脈波訊號停止被輸出於一段從當電源電壓被開啟時開始的預定期間，其中，該輸出停止電路包含：第一及第二電容器元件；N-型電晶體，具有其源極連接至地，並且具有其汲極經由該第一電容器元件而被連接至電源；以及P-型電晶體，具有其源極連接至該電源，並且具有其汲極經由該第二電容器元件而被連接至該地，其中該N-型電晶體具有其閘極連接至該P-型電晶體的該汲極，並且該P-型電晶體具有其閘極連接至該N-型電晶體的該汲極，並且該第一及第二輸出脈波訊號之該輸出的該停止依據該 N-型電晶體的閘極電壓和該P-型電晶體的閘極電壓而被解除。 A transmitter circuit includes: a pulse wave generating circuit that generates a pulse wave signal according to a plurality of edges of input data; a first output driver, based on the pulse wave signal, outputs a first pulse according to one of the edges The wave signal is output to the first end of the external insulating coupling element; the second output driver outputs the second output pulse signal to the second end of the insulating coupling element according to the pulse signal and the other of the edges And an output stop circuit to stop the first and second output pulse signals from being output for a predetermined period from when the power supply voltage is turned on, wherein the output stop circuit includes: first and second capacitor elements; An N-type transistor having its source connected to ground and having its drain connected to the power supply via the first capacitor element; and a P-type transistor having its source connected to the power supply and having its The drain is connected to the ground via the second capacitor element, wherein the N-type transistor has its gate connected to the drain of the P-type transistor, and the P-type transistor has its gate Connected to the drain of the N-type transistor, and the stop of the output of the first and second output pulse signals is based on the The gate voltage of the N-type transistor and the gate voltage of the P-type transistor are released. 一種發射器電路，包括：脈波產生電路，根據輸入資料的複數個邊緣而產生脈波訊號；第一輸出驅動器，根據該脈波訊號，依據該等邊緣的其中一個邊緣而將第一輸出脈波訊號輸出至外部絕緣耦合元件之第一端；第二輸出驅動器，根據該脈波訊號，依據該等邊緣的另一個邊緣而將第二輸出脈波訊號輸出至該絕緣耦合元件之第二端；以及輸出停止電路，使該第一及第二輸出脈波訊號停止被輸出於一段從當電源電壓被開啟時開始的預定期間，其中，該輸出停止電路藉由使該脈波產生電路停止產生該脈波訊號於一段從當該電源電壓被開啟時開始的預定期間，以使該第一及第二輸出脈波訊號停止被輸出。 A transmitter circuit includes: a pulse wave generating circuit that generates a pulse wave signal according to a plurality of edges of input data; a first output driver, based on the pulse wave signal, outputs a first pulse according to one of the edges The wave signal is output to the first end of the external insulating coupling element; the second output driver outputs the second output pulse signal to the second end of the insulating coupling element according to the pulse signal and the other of the edges ; And an output stop circuit to stop the first and second output pulse signals from being output for a predetermined period from when the power supply voltage is turned on, wherein the output stop circuit stops the pulse wave generation circuit from generating The pulse signal is for a predetermined period from when the power supply voltage is turned on, so that the first and second output pulse signals are stopped from being output. 如申請專利範圍第3項之發射器電路，其中該輸出停止電路包含：電容器元件，係連接至電源和地的其中一者；以及電阻器元件，係連接至電源和地的另一者，其中該第一及第二輸出脈波訊號之該輸出的該停止依據介於該電容器元件與該電阻器元件間之連接節點的電壓而被解除。 A transmitter circuit as claimed in item 3 of the patent scope, wherein the output stop circuit includes: a capacitor element connected to one of the power supply and ground; and a resistor element connected to the other of the power supply and ground, where The stop of the output of the first and second output pulse signals is released according to the voltage of the connection node between the capacitor element and the resistor element. 一種半導體裝置，包括： 發射器電路，根據輸入資料而發送第一及第二輸出脈波訊號；接收器電路，接收該第一及第二輸出脈波訊號，並且重新建構該輸入資料；以及主要絕緣耦合元件及次要絕緣耦合元件，使該發射器電路和該接收器電路互相電磁性地耦合，其中該發射器電路包含：脈波產生電路，根據該輸入資料的複數個邊緣而產生脈波訊號；第一輸出驅動器，根據該脈波訊號，依據該等邊緣的其中一個邊緣而將該第一輸出脈波訊號輸出至該主要絕緣耦合元件之第一端；第二輸出驅動器，根據該脈波訊號，依據該等邊緣的另一個邊緣而將該第二輸出脈波訊號輸出至該主要絕緣耦合元件之第二端；以及輸出停止電路，使該第一及第二輸出脈波訊號停止被輸出於一段從當電源電壓被開啟時開始的預定期間，其中，該輸出停止電路包含：鎖存器電路，感測該電源電壓的該開啟並且維持該第一及第二輸出脈波訊號之該輸出的該停止；以及計時器，其中回應於輸出自該計時器的訊號，該鎖存器電路解除該第一及第二輸出脈波訊號之該輸出的該停止，其中，該輸出停止電路另包含第一及第二電容器元 件，該鎖存器電路具有經由該第一電容器元件而被連接至電源的第一儲存節點，並且具有經由該第二電容器元件而被接地的第二儲存節點，該鎖存器電路分別在該第一及第二儲存節點保持彼此倒反的電壓，以及回應於輸出自該計時器的該訊號，該鎖存器電路藉由在該第一及第二儲存節點轉變時所保持的該等電壓而解除該第一及第二輸出脈波訊號之該輸出的該停止。 A semiconductor device, including: The transmitter circuit sends first and second output pulse signals according to the input data; the receiver circuit receives the first and second output pulse signals and reconstructs the input data; and the main insulating coupling element and the secondary Insulating coupling element to electromagnetically couple the transmitter circuit and the receiver circuit, wherein the transmitter circuit includes: a pulse wave generating circuit that generates a pulse wave signal according to a plurality of edges of the input data; a first output driver , According to the pulse signal, output the first output pulse signal to the first end of the main insulating coupling element according to one of the edges; the second output driver, according to the pulse signal, according to the The other edge of the edge to output the second output pulse signal to the second end of the main insulating coupling element; and an output stop circuit to stop the first and second output pulse signals from being output to a section of the slave power supply A predetermined period starting when the voltage is turned on, wherein the output stop circuit includes: a latch circuit that senses the turn-on of the power supply voltage and maintains the stop of the output of the first and second output pulse signals; and A timer, wherein in response to the signal output from the timer, the latch circuit releases the stop of the output of the first and second output pulse signals, wherein the output stop circuit further includes first and second Capacitor element Device, the latch circuit has a first storage node connected to the power supply via the first capacitor element, and has a second storage node grounded via the second capacitor element, the latch circuit The first and second storage nodes maintain mutually inverted voltages, and in response to the signal output from the timer, the latch circuit maintains the voltages held when the first and second storage nodes transition And the stop of the output of the first and second output pulse signals is released. 一種半導體裝置，包括：發射器電路，根據輸入資料而發送第一及第二輸出脈波訊號；接收器電路，接收該第一及第二輸出脈波訊號，並且重新建構該輸入資料；以及主要絕緣耦合元件及次要絕緣耦合元件，使該發射器電路和該接收器電路互相電磁性地耦合，其中該發射器電路包含：脈波產生電路，根據該輸入資料的複數個邊緣而產生脈波訊號；第一輸出驅動器，根據該脈波訊號，依據該等邊緣的其中一個邊緣而將該第一輸出脈波訊號輸出至該主要絕緣耦合元件之第一端；第二輸出驅動器，根據該脈波訊號，依據該等邊緣的另一個邊緣而將該第二輸出脈波訊號輸出至該主要絕緣耦 合元件之第二端；以及輸出停止電路，使該第一及第二輸出脈波訊號停止被輸出於一段從當電源電壓被開啟時開始的預定期間，其中，該輸出停止電路包含：第一及第二電容器元件；N-型電晶體，具有其源極連接至地，並且具有其汲極經由該第一電容器元件而被連接至電源；以及P-型電晶體，具有其源極連接至該電源，並且具有其汲極經由該第二電容器元件而被連接至該地，其中該N-型電晶體具有其閘極連接至該P-型電晶體的該汲極，並且該P-型電晶體具有其閘極連接至該N-型電晶體的該汲極，並且該第一及第二輸出脈波訊號之該輸出的該停止依據該N-型電晶體的閘極電壓和該P-型電晶體的閘極電壓而被解除。 A semiconductor device includes: a transmitter circuit that transmits first and second output pulse signals according to input data; a receiver circuit that receives the first and second output pulse signals and reconstructs the input data; and mainly An insulating coupling element and a secondary insulating coupling element electromagnetically couple the transmitter circuit and the receiver circuit to each other, wherein the transmitter circuit includes: a pulse wave generating circuit that generates a pulse wave according to a plurality of edges of the input data Signal; the first output driver, according to the pulse signal, according to one of the edges to output the first output pulse signal to the first end of the main insulating coupling element; the second output driver, according to the pulse Wave signal, the second output pulse signal is output to the main insulating coupler according to the other edge of the edges The second end of the coupling element; and an output stop circuit to stop the first and second output pulse signals from being output for a predetermined period from when the power supply voltage is turned on, wherein the output stop circuit includes: a first And a second capacitor element; an N-type transistor having its source connected to ground and having its drain connected to the power supply via the first capacitor element; and a P-type transistor having its source connected to The power supply, and has its drain connected to the ground via the second capacitor element, wherein the N-type transistor has the gate connected to the P-type transistor, and the P-type The transistor has its gate connected to the drain of the N-type transistor, and the stop of the output of the first and second output pulse signals depends on the gate voltage of the N-type transistor and the P -The gate voltage of the transistor is released. 一種半導體裝置，包括：發射器電路，根據輸入資料而發送第一及第二輸出脈波訊號；接收器電路，接收該第一及第二輸出脈波訊號，並且重新建構該輸入資料；以及主要絕緣耦合元件及次要絕緣耦合元件，使該發射器電路和該接收器電路互相電磁性地耦合，其中該發射器電路包含：脈波產生電路，根據該輸入資料的複數個邊緣而產生 脈波訊號；第一輸出驅動器，根據該脈波訊號，依據該等邊緣的其中一個邊緣而將該第一輸出脈波訊號輸出至該主要絕緣耦合元件之第一端；第二輸出驅動器，根據該脈波訊號，依據該等邊緣的另一個邊緣而將該第二輸出脈波訊號輸出至該主要絕緣耦合元件之第二端；以及輸出停止電路，使該第一及第二輸出脈波訊號停止被輸出於一段從當電源電壓被開啟時開始的預定期間，其中，該輸出停止電路藉由使該脈波產生電路停止產生該脈波訊號於一段從當該電源電壓被開啟時開始的預定期間，以使該第一及第二輸出脈波訊號停止被輸出。 A semiconductor device includes: a transmitter circuit that transmits first and second output pulse signals according to input data; a receiver circuit that receives the first and second output pulse signals and reconstructs the input data; and mainly An insulating coupling element and a secondary insulating coupling element electromagnetically couple the transmitter circuit and the receiver circuit to each other, wherein the transmitter circuit includes: a pulse wave generating circuit generated according to a plurality of edges of the input data The pulse signal; the first output driver, according to the pulse signal, according to one of the edges to output the first output pulse signal to the first end of the main insulating coupling element; the second output driver, according to The pulse signal outputs the second output pulse signal to the second end of the main insulating coupling element according to the other edge of the edges; and an output stop circuit to enable the first and second output pulse signals The stop is output for a predetermined period from when the power supply voltage is turned on, wherein the output stop circuit stops the pulse wave generation circuit from generating the pulse signal for a predetermined period from when the power supply voltage is turned on During this period, the first and second output pulse signals are stopped from being output. 如申請專利範圍第7項之半導體裝置，其中該輸出停止電路包含：電容器元件，係連接至電源和地的其中一者；以及電阻器元件，係連接至電源和地的另一者，其中該第一及第二輸出脈波訊號之該輸出的該停止依據介於該電容器元件與該電阻器元件間之連接節點的電壓而被解除。 A semiconductor device as claimed in item 7 of the patent application, wherein the output stop circuit includes: a capacitor element connected to one of the power supply and ground; and a resistor element connected to the other of the power supply and ground, where the The stop of the output of the first and second output pulse signals is released according to the voltage of the connection node between the capacitor element and the resistor element. 如申請專利範圍第5至8項中任一項之半導體裝置，其中該主要絕緣耦合元件和該次要絕緣耦合元件為在半導體晶片中分別被形成在堆疊於頂部-至-底部方向上的兩個互連層中之線圈。 The semiconductor device according to any one of claims 5 to 8, wherein the primary insulating coupling element and the secondary insulating coupling element are formed in a semiconductor wafer in two directions stacked in the top-to-bottom direction, respectively Coils in an interconnection layer.
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