JP2009095074A - Semiconductor switching circuit - Google Patents
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- JP2009095074A JP2009095074A JP2007260710A JP2007260710A JP2009095074A JP 2009095074 A JP2009095074 A JP 2009095074A JP 2007260710 A JP2007260710 A JP 2007260710A JP 2007260710 A JP2007260710 A JP 2007260710A JP 2009095074 A JP2009095074 A JP 2009095074A
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- 239000004065 semiconductor Substances 0.000 title claims description 12
- 101100457838 Caenorhabditis elegans mod-1 gene Proteins 0.000 description 3
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- 238000000034 method Methods 0.000 description 3
- 101100014507 Arabidopsis thaliana GDU1 gene Proteins 0.000 description 2
- 101100014509 Arabidopsis thaliana GDU3 gene Proteins 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
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- 238000005859 coupling reaction Methods 0.000 description 1
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- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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Abstract
Description
この発明は、複数個直並列接続された電圧駆動型半導体素子（以下、単に素子とも略記する）の素子電圧および素子電流を平衡化（バランス）させるための、素子接続方法と駆動方法を改良した半導体スイッチ回路に関する。 The present invention has improved an element connection method and a driving method for balancing the device voltage and the device current of a plurality of voltage-driven semiconductor devices (hereinafter also simply referred to as devices) connected in series and parallel. The present invention relates to a semiconductor switch circuit.
近年、電力変換装置に対する大容量化のために、素子を直並列接続する場合、各素子のスイッチングタイミングのばらつきによって、素子に印加される電圧や電流がばらつく可能性がある。これにより、素子の定格に対して過電圧や過電流となった場合、素子破壊を招くことがある。そのため、素子を直列接続する場合には、電圧分担と電流分担を均一化する技術が重要となってくる。 In recent years, when elements are connected in series and parallel in order to increase the capacity of a power converter, there is a possibility that the voltage and current applied to the elements vary due to variations in switching timing of the elements. As a result, when an overvoltage or overcurrent is generated with respect to the rating of the element, the element may be destroyed. Therefore, when elements are connected in series, a technique for equalizing voltage sharing and current sharing becomes important.
従来技術として、例えば特許文献１に開示されている図３のような回路がある。
図示のように３直列２並列のIGBT素子(Q1a〜Q1c,Q2a~Q2c)、各素子のゲート駆動回路GDU1a~GDU2c、１：１の巻数比で構成された４つの磁気回路MC1a~MC2c、およびコモンモードの磁気回路MCxなどから構成される。
これらの磁気回路は、全IGBTのゲート線を磁気結合するように接続され、各ゲート駆動回路のオン・オフタイミングがばらついても、各ゲート電流を一致させるように動作する。その結果、スイッチングタイミングを同期させることができる。つまり、直並列接続された各素子の電圧，電流を、簡単な回路でバランスさせるものである。
As a conventional technique, for example, there is a circuit as shown in FIG.
As shown, three series and two parallel IGBT elements (Q1a to Q1c, Q2a to Q2c), gate drive circuits GDU1a to GDU2c of each element, four magnetic circuits MC1a to MC2c configured with a 1: 1 turns ratio, and It consists of a common mode magnetic circuit MCx.
These magnetic circuits are connected so as to magnetically couple the gate lines of all IGBTs, and operate so as to make the gate currents coincide with each other even if the on / off timings of the gate drive circuits vary. As a result, the switching timing can be synchronized. That is, the voltage and current of each element connected in series and parallel are balanced by a simple circuit.
上記図３のようにすることで、各素子の電圧，電流を、簡単な回路でバランスさせることができるが、このような回路では各素子に対し１つずつゲート駆動回路が必要となり、回路が複雑，大型化するという問題が生じる。
したがって、この発明の課題は、直並列接続素子の電圧，電流を、簡単な回路でバランスさせることにある。
With the configuration shown in FIG. 3, the voltage and current of each element can be balanced by a simple circuit. In such a circuit, one gate driving circuit is required for each element, and the circuit is The problem of increasing complexity and size arises.
Accordingly, an object of the present invention is to balance the voltage and current of series-parallel connection elements with a simple circuit.
このような課題を解決するため、請求項１の発明では、複数個直並列接続された電圧駆動型半導体素子（素子）と、これらを駆動するためのゲート駆動回路を備えた半導体スイッチ回路において、
前記各ゲート駆動回路を前記素子の直列接続数と同数設けるとともにゲート線を互いに磁気結合させ、磁気結合させた後段のゲート線とエミッタ線を、直列接続素子の並列接続数に応じ分岐して、素子のゲート端子とエミッタ端子に入力し、かつ並列接続されている素子のコレクタおよびエミッタの主端子どうしを互いに接続することを特徴とする。
In order to solve such a problem, in the invention of claim 1, in a semiconductor switch circuit comprising a plurality of voltage-driven semiconductor elements (elements) connected in series and parallel and a gate drive circuit for driving them,
Each gate drive circuit is provided in the same number as the series connection of the elements and the gate lines are magnetically coupled to each other, and the subsequent gate lines and emitter lines magnetically coupled are branched according to the number of parallel connections of the series connection elements, The collector and emitter main terminals of the elements that are input to the gate terminal and the emitter terminal of the element and are connected in parallel are connected to each other.
上記請求項１の発明においては、前記並列接続される各素子へのゲート配線のインピ−ダンスが互いに等しくなるようにすることができ（請求項２の発明）、または、これら請求項１または２の発明においては、前記並列接続される素子のコレクタおよびエミッタの主端子どうしを互いに接続する配線の浮遊インダクタンスを、各素子のコレクタ−エミッタ間に存在する内部インダクタンスよりも十分小さくなるようにすることができる（請求項３の発明）。 In the first aspect of the present invention, the impedances of the gate wirings to the elements connected in parallel can be made equal to each other (the second aspect of the present invention), or the first and second aspects of the present invention. In the invention, the stray inductance of the wiring connecting the main terminals of the collector and emitter of the elements connected in parallel is made sufficiently smaller than the internal inductance existing between the collector and emitter of each element. (Invention of claim 3).
この発明によれば、ゲート駆動回路を素子数分ではなく直列数分としたため、ゲート駆動回路の点数を大幅に削減でき、その結果、コスト低減や信頼性向上を実現できるという利点が得られる。 According to the present invention, since the number of gate drive circuits is not the number of elements but the number of series, the number of gate drive circuits can be greatly reduced, and as a result, the cost can be reduced and the reliability can be improved.
図１はこの発明の実施の形態を説明するための構成図である。
これも図３と同様、素子(Q11〜Q13,Q21~Q23)が３直列２並列の例で、GDU1~GDU3はゲート駆動回路、磁気回路MC1，MC2は各ゲート線を磁気結合するための磁気回路である。この磁気回路の作用により、素子のゲート信号タイミングを同調させ、電圧バランスを実現している。
FIG. 1 is a block diagram for explaining an embodiment of the present invention.
This is also an example in which the elements (Q11 to Q13, Q21 to Q23) are three in series and two in parallel, as in FIG. 3, GDU1 to GDU3 are gate drive circuits, and magnetic circuits MC1 and MC2 are magnetic elements for magnetically coupling the gate lines. Circuit. Due to the action of this magnetic circuit, the gate signal timing of the element is tuned to achieve voltage balance.
ここで、ゲート駆動回路は素子直列数だけ設置し（ここでは３個）、その出力信号を磁気結合した後段より並列数（ここでは２つ）に応じて分岐し（分岐線L11~L32参照）、各素子へ接続している。また、並列接続されている素子のコレクタおよびエミッタの主端子（図１のＣおよびＥ端子）同士を接続する。このとき、並列接続されている素子へのゲート信号伝達時間を同じにして、スイッチングタイミングがばらつかないようにするため、分岐した各ゲート配線のインピーダンスを同等に設定する。 Here, gate drive circuits are installed in the number of elements in series (here, 3), and the output signals are magnetically coupled and then branched according to the number of parallel (here, 2) (see branch lines L11 to L32). , Connected to each element. Also, the collector and emitter main terminals (C and E terminals in FIG. 1) of the elements connected in parallel are connected to each other. At this time, the gate signal transmission time to the elements connected in parallel is made the same so that the switching timing does not vary, and the impedance of each branched gate wiring is set to be equal.
さらに、素子のオフ過渡時に、配線インダクタンスに起因するサージ電圧値をバランスさせるために、並列接続素子の主端子（コレクタ，エミッタ）を接続している配線のインダクタンスを、素子内部に浮遊するインダクタンス値よりも十分小さい値に設定する。この点に関し、図２の素子２並列回路を参照して説明する。図２において、M1,M2が並列接続の素子、C1,C2およびE1,E2が、各素子のコレクタおよびエミッタ端子、lmod1,lmod2が各素子の内部インダクタンスである。lmod1,lmod2は同じ素子を用い、同値（lmod）にする。また、l1,l2が２モジュールM1,M2を接続する配線に浮遊するインダクタンス分である。 Furthermore, in order to balance the surge voltage value due to wiring inductance during the off-transition of the element, the inductance of the wiring connecting the main terminals (collector, emitter) of the parallel connection element is the inductance value that floats inside the element. Set to a sufficiently smaller value. This point will be described with reference to the element 2 parallel circuit of FIG. In FIG. 2, M1 and M2 are elements connected in parallel, C1, C2 and E1, E2 are collector and emitter terminals of each element, and l mod1 and l mod2 are internal inductances of each element. l mod1 and l mod2 use the same element and have the same value (l mod ). Further, l 1 and l 2 are inductance components floating on the wiring connecting the two modules M1 and M2.
ここで、各素子がターンオフし、各電流l1およびl2が遮断され、これらが同じ電流変化率di/dtで減少していると仮定する。このとき、各素子に印加されるサージ電圧上昇値VCE1,VCE2は次式で表わされる。
VCE1=（lmod＋l1）×di/dt （１）
VCE2=（lmod＋l2）×di/dt （２）
これらの式より、l1,l2のばらつきによって、各素子に印加される電圧がアンバランスとなることが分かる。
Here, it is assumed that each element is turned off, each current l 1 and l 2 is cut off, and these are decreasing at the same current change rate di / dt. At this time, surge voltage rise values V CE1 and V CE2 applied to each element are expressed by the following equations.
V CE1 = (l mod + l 1 ) × di / dt (1)
V CE2 = (l mod + l 2 ) × di / dt (2)
From these equations, it can be seen that the voltage applied to each element is unbalanced due to variations in l 1 and l 2 .
そこで、l1およびl2をlmodよりも十分小さい値に設定する。これにより、各電圧は次式のように近似される。
VCE1≒lmod×di/dt （１’）
VCE2≒lmod×di/dt （２’）
こうして、各素子のサージ電圧上昇値をほぼ同じ値にすることができる。
Therefore, l 1 and l 2 are set to values sufficiently smaller than l mod . Thereby, each voltage is approximated as follows.
V CE1 ≒ l mod × di / dt (1 ')
V CE2 ≒ l mod × di / dt (2 ')
Thus, the surge voltage increase value of each element can be made substantially the same value.
なお、電圧駆動型半導体素子として上記ではIGBTを用いたが、MOSFET（金属酸化膜電界効果トランジスタ）などを用いることができるのは言うまでも無い。 Although the IGBT is used as the voltage-driven semiconductor element in the above, it goes without saying that a MOSFET (metal oxide field effect transistor) or the like can be used.
GDU1~GDU3…ゲート駆動回路、MC1，MC2…磁気回路、Q11〜Q13,Q21~Q23…IGBT（絶縁ゲートバイポーラトランジスタ）を含む電圧駆動型半導体素子、L11~L32…分岐線、l1,l2…配線インダクタンス、lmod1，lmod2…内部インダクタンス。 GDU1 to GDU3… Gate drive circuit, MC1, MC2… Magnetic circuit, Q11 to Q13, Q21 to Q23… Voltage drive type semiconductor element including IGBT (insulated gate bipolar transistor), L11 to L32… Branch line, l 1 , l 2 … Wiring inductance, l mod1 , l mod2 … internal inductance.
Claims (3)
前記各ゲート駆動回路を前記素子の直列接続数と同数設けるとともにゲート線を互いに磁気結合させ、磁気結合させた後段のゲート線とエミッタ線を、直列接続素子の並列接続数に応じ分岐して、素子のゲート端子とエミッタ端子に入力し、かつ並列接続されている素子のコレクタおよびエミッタの主端子どうしを互いに接続することを特徴とする半導体スイッチ回路。 In a semiconductor switch circuit comprising a plurality of voltage-driven semiconductor elements (elements) connected in series and parallel and a gate drive circuit for driving them,
Each gate drive circuit is provided in the same number as the series connection of the elements and the gate lines are magnetically coupled to each other, and the subsequent gate lines and emitter lines magnetically coupled are branched according to the number of parallel connections of the series connection elements, A semiconductor switch circuit comprising: a collector terminal and an emitter main terminal of an element which are input to a gate terminal and an emitter terminal of the element and connected in parallel to each other.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014168607A1 (en) * | 2013-04-09 | 2014-10-16 | Otis Elevator Company | Architecture of drive unit employing gallium nitride switches |
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| JPS5022564A (en) * | 1973-06-27 | 1975-03-11 | ||
| JP2000350475A (en) * | 1999-05-31 | 2000-12-15 | Hitachi Ltd | Semiconductor circuit |
| JP2004096829A (en) * | 2002-08-29 | 2004-03-25 | Fuji Electric Holdings Co Ltd | Controller of voltage-driven semiconductor device connected in parallel |
| JP2005093698A (en) * | 2003-09-17 | 2005-04-07 | Fuji Electric Holdings Co Ltd | Semiconductor module for electric power |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5022564A (en) * | 1973-06-27 | 1975-03-11 | ||
| JP2000350475A (en) * | 1999-05-31 | 2000-12-15 | Hitachi Ltd | Semiconductor circuit |
| JP2004096829A (en) * | 2002-08-29 | 2004-03-25 | Fuji Electric Holdings Co Ltd | Controller of voltage-driven semiconductor device connected in parallel |
| JP2005093698A (en) * | 2003-09-17 | 2005-04-07 | Fuji Electric Holdings Co Ltd | Semiconductor module for electric power |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2014168607A1 (en) * | 2013-04-09 | 2014-10-16 | Otis Elevator Company | Architecture of drive unit employing gallium nitride switches |
| CN105103423A (en) * | 2013-04-09 | 2015-11-25 | 奥的斯电梯公司 | Architecture of drive unit employing gallium nitride switches |
| CN105103423B (en) * | 2013-04-09 | 2019-03-08 | 奥的斯电梯公司 | Using the framework of the driving unit of gallium nitride switch |
| US10366935B2 (en) | 2013-04-09 | 2019-07-30 | Otis Elevator Company | Architecture of drive unit employing gallium nitride switches |
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