TWI671913B - 半導體裝置及其製造方法 - Google Patents
半導體裝置及其製造方法 Download PDFInfo
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- TWI671913B TWI671913B TW107114836A TW107114836A TWI671913B TW I671913 B TWI671913 B TW I671913B TW 107114836 A TW107114836 A TW 107114836A TW 107114836 A TW107114836 A TW 107114836A TW I671913 B TWI671913 B TW I671913B
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- copper
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 88
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000010949 copper Substances 0.000 claims abstract description 267
- 229910052802 copper Inorganic materials 0.000 claims abstract description 226
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 197
- 239000010409 thin film Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000463 material Substances 0.000 claims description 101
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 42
- 229910052750 molybdenum Inorganic materials 0.000 claims description 42
- 239000011733 molybdenum Substances 0.000 claims description 42
- -1 copper nitride Chemical class 0.000 claims description 29
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 11
- 239000001272 nitrous oxide Substances 0.000 claims description 10
- 238000005240 physical vapour deposition Methods 0.000 claims description 7
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 6
- 229910000077 silane Inorganic materials 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims 2
- 230000001131 transforming effect Effects 0.000 claims 1
- 239000013078 crystal Substances 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 16
- 101000606064 Cupiennius salei Cupiennin-1a Proteins 0.000 description 8
- 101000760666 Cupiennius salei Cupiennin-2a Proteins 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 7
- 101000761027 Cupiennius salei Cupiennin-1c Proteins 0.000 description 6
- 101000760654 Cupiennius salei Cupiennin-2c Proteins 0.000 description 6
- 238000012360 testing method Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 101000760656 Cupiennius salei Cupiennin-2b Proteins 0.000 description 4
- 101000606068 Cupiennius salei Cupiennin-1b Proteins 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910000431 copper oxide Inorganic materials 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 1
- YSRUGFMGLKANGO-UHFFFAOYSA-N zinc hafnium(4+) indium(3+) oxygen(2-) Chemical compound [O-2].[Zn+2].[In+3].[Hf+4] YSRUGFMGLKANGO-UHFFFAOYSA-N 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Classifications
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current
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- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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Abstract
一種半導體裝置包括第一基板以設置於第一基板上的薄膜電晶體。薄膜晶體包括閘極、半導體圖案、第一絕緣層、源極以及汲極。第一絕緣層設置於閘極與半導體圖案之間。源極與汲極彼此分離且各自與半導體圖案對應設置。源極與汲極的至少一者具有第一銅圖案層與第一氮氧化銅圖案層。第一氮氧化銅圖案層覆蓋第一銅圖案層。第一銅圖案層設置於第一氮氧化銅圖案層與第一基板之間。此外,上述半導體裝置的製造方法也被提出。
Description
本發明是有關於一種電子裝置及其製造方法,且特別是有關於一種半導體裝置及其製造方法。
銅(copper;Cu)具有高導電率、低電阻及低成本的優勢,因此,銅常作為薄膜電晶體之源極與汲極的材料之一。然而,銅與其上之膜層的附著(adhesion)不佳時,銅易受外界水氣的影響而劣化,進而影響薄膜電晶體的電性。舉例而言,源極與汲極之銅層劣化時,薄膜電晶體之汲極電流(ID)與閘極電壓(VGS)的關係曲線(I-V curve)會偏移,而造成漏電流。此時,若顯示面板採用上述薄膜電晶體作為畫素開關,薄膜電晶體無法正常地關閉畫素,而會出現顯示異常的問題(例如:黑白棋盤格畫面的黑格泛白)。
本發明提供一種半導體裝置,不易產生漏電流的問題,信賴性佳。
本發明提供一種半導體裝置的製作方法,能實現不易產生漏電流問題且信賴性佳的半導體裝置。
本發明的一實施例的半導體裝置包括第一基板以及薄膜電晶體。薄膜電晶體設置於第一基板上。薄膜晶體包括閘極、半導體圖案、第一絕緣層、源極以及汲極。第一絕緣層設置於閘極與半導體圖案之間。源極與汲極彼此分離且各自與半導體圖案對應設置。源極與汲極的至少一者具有第一銅圖案層與第一氮氧化銅圖案層。第一氮氧化銅圖案層覆蓋第一銅圖案層。第一銅圖案層設置於第一氮氧化銅圖案層與第一基板之間。
在本發明的一實施例中,上述的第一銅圖案層具有第一頂面、第一底面以及連接於第一底面與第一頂面之間的第一側壁,而第一氮氧化銅圖案層覆蓋第一頂面及第一側壁。
在本發明的一實施例中,上述的源極與汲極的至少一者更具有第一鉬圖案層,第一銅圖案層設置於第一氮氧化銅圖案層與第一鉬圖案層之間。
在本發明的一實施例中,上述的半導體裝置更包括資料線,與薄膜電晶體的源極電性連接。資料線具有第二銅圖案層與第二氮氧化銅圖案層。第二氮氧化銅圖案層覆蓋第二銅圖案層。第二銅圖案層設置於第二氮氧化銅圖案層與第一基板之間。
在本發明的一實施例中,上述的第二銅圖案層具有第二頂面、第二底面以及連接於第二底面與第二頂面之間的第二側壁,而第二氮氧化銅圖案層覆蓋第二頂面及第二側壁。
在本發明的一實施例中,上述的資料線更具有第二鉬圖案層。第二銅圖案層設置於第二氮氧化銅圖案層與第二鉬圖案層之間。
在本發明的一實施例中,上述的第一氮氧化銅圖案層直接與第一銅圖案層接觸。
在本發明的一實施例中,上述的半導體裝置更包括氧化矽層,覆蓋第一氮氧化銅圖案層且與第一氮氧化銅圖案層接觸。
在本發明的一實施例中,上述的半導體裝置更包括畫素電極,與汲極電性連接。
本發明的一實施例提供一種半導體裝置的製造方法包括下列步驟:提供第一基板;於第一基板上形成閘極、第一絕緣層以及半導體圖案,其中第一絕緣層設置於閘極與半導體圖案之間;利用物理氣相沉積在第一基板上形成銅材料層;通入氮氣,以在銅材料層上形成氮化銅材料層;圖案化銅材料層與氮化銅材料層,以形成第一銅圖案層與第一氮化銅圖案層;以及通入一氧化二氮,一氧化二氮與第一氮化銅圖案層反應,以形成第一氮氧化銅圖案層,該第一氮氧化銅圖案層覆蓋該第一銅圖案,其中第一銅圖案層以及第一氮氧化銅圖案層構成源極與汲極,而源極與汲極彼此分離且各自與半導體圖案對應設置。
在本發明的一實施例中,上述的半導體裝置的製造方法更包括:在形成第一氮氧化銅圖案層之後,通入矽烷,矽烷與一氧化二氮反應,以形成氧化矽層,其中氧化矽層覆蓋源極與汲極。
基於上述,在本發明的實施例的半導體裝置及其製造方法中,源極與汲極的至少一者的表面分別具有氮氧化銅圖案層,以及/或資料線的表面具有氮氧化銅圖案層,因氮氧化銅圖案層具有緻密的材料特性,及/或氮氧化銅圖案層與氧化矽層的附著佳。藉此,外界水氣不易入侵源極與汲極之至少一者的銅圖案層,而本發明的實施例的半導體裝置的信賴性佳。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
100、200‧‧‧半導體裝置
110‧‧‧第一基板
120‧‧‧薄膜電晶體
122‧‧‧閘極
124‧‧‧第一絕緣層
126‧‧‧半導體圖案
128a、128a’‧‧‧源極
128b、128b’‧‧‧汲極
130‧‧‧氧化矽層
140‧‧‧畫素電極
A-A’‧‧‧剖線’
Cu‧‧‧銅材料層
Cu’‧‧‧銅圖案層
Cu-t‧‧‧頂面區域
Cu-1‧‧‧第一銅圖案層
Cu-1a‧‧‧第一頂面
Cu-1b‧‧‧第一底面
Cu-1c‧‧‧第一側壁
Cu’-1e、Cu’-2e‧‧‧側壁區域
Cu-2‧‧‧第二銅圖案層
Cu-2a‧‧‧第二頂面
Cu-2b‧‧‧第二底面
Cu-2c‧‧‧第二側壁
CuN‧‧‧氮化銅材料層
CuN’-1‧‧‧第一氮化銅材料層
CuN’-2‧‧‧第二氮化銅材料層
CuN-1‧‧‧第一氮化銅圖案層
CuN-2‧‧‧第二氮化銅圖案層
CuNO’-1‧‧‧第一氮氧化銅材料層
CuNO’-2‧‧‧第二氮氧化銅材料層
CuNO-1‧‧‧第一氮氧化銅圖案層
CuNO-2‧‧‧第二氮氧化銅圖案層
DL‧‧‧資料線
H‧‧‧接觸窗
Mo‧‧‧鉬材料層
Mo’‧‧‧鉬圖案層
Mo’-1‧‧‧第一鉬材料層
Mo’-2‧‧‧第二鉬材料層
Mo-1‧‧‧第一鉬圖案層
Mo-2‧‧‧第二鉬圖案層
SL‧‧‧掃描線
R1、R2‧‧‧局部
圖1A至圖1F是依照本發明的實施例的半導體裝置的製造流程剖面示意圖。
圖2為本發明的實施例之半導體裝置的上視示意圖。
圖3是依照比較例的半導體裝置的剖面示意圖。
圖4是依照比較例的半導體裝置於電子顯微鏡下的局部剖面影像。
圖5是依照本發明的實施例的半導體裝置於電子顯微鏡下的局部剖面影像。
在附圖中,為了清楚起見,放大了層、膜、面板、區域等的厚度。在整個說明書中,相同的附圖標記表示相同的元件。應當理解,當諸如層、膜、區域或基板的元件被稱為在另一元件「上」或「連接到」另一元件時,其可以直接在另一元件上或與另一元件連接,或者中間元件可以也存在。相反,當元件被稱為「直接在另一元件上」或「直接連接到」另一元件時,不存在中間元件。如本文所使用的,「連接」可以指物理及/或電性連接。再者,「電性連接」或「耦合」係可為二元件間存在其它元件。
本文使用的「約」、「近似」、或「實質上」包括所述值和在本領域普通技術人員確定的特定值的可接受的偏差範圍內的平均值,考慮到所討論的測量和與測量相關的誤差的特定數量(即,測量系統的限制)。例如,「約」可以表示在所述值的一個或多個標準偏差內,或±30%、±20%、±10%、±5%內。再者,本文使用的「約」、「近似」或「實質上」可依光學性質、蝕刻性質或其它性質,來選擇較可接受的偏差範圍或標準偏差,而可不用一個標準偏差適用全部性質。
除非另有定義,本文使用的所有術語(包括技術和科學術語)具有與本發明所屬領域的普通技術人員通常理解的相同的含義。將進一步理解的是,諸如在通常使用的字典中定義的那些術語應當被解釋為具有與它們在相關技術和本發明的上下文中的含義一致的含義,並且將不被解釋為理想化的或過度正式的意
義,除非本文中明確地這樣定義。
本文參考作為理想化實施方式的示意圖的截面圖來描述示例性實施方式。因此,可以預期到作為例如製造技術及/或公差的結果的圖示的形狀變化。因此,本文所述的實施方式不應被解釋為限於如本文所示的區域的特定形狀,而是包括例如由製造導致的形狀偏差。例如,示出或描述為平坦的區域通常可以具有粗糙及/或非線性特徵。此外,所示的銳角可以是圓的。因此,圖中所示的區域本質上是示意性的,並且它們的形狀不是旨在示出區域的精確形狀,並且不是旨在限制權利要求的範圍。
現將詳細地參考本發明的示範性實施例,示範性實施例的實例說明於所附圖式中。只要有可能,相同元件符號在圖式和描述中用來表示相同或相似部分。
圖1A至圖1F是依照本發明的實施例的半導體裝置的製造流程剖面示意圖。圖2為本發明的實施例的半導體裝置的上視示意圖。具體而言,圖1F的剖面是對應於圖2的的剖線A-A’。
請參考圖1A,本實施例中,首先,提供第一基板110。接著,在第一基板110上依序形成閘極122、第一絕緣層124以及半導體圖案126。第一絕緣層124覆蓋閘極122。半導體圖案126設置於第一絕緣層124上。第一絕緣層124設置於閘極122與半導體圖案126之間。在本實施例中,於形成閘極122時,可選擇性地一起形成掃描線SL(標示於圖2),但本發明不以此為限。
舉例而言,在本實施例中,可利用物理氣相沉積(Physical
Vapor Deposition;PVD)形成閘極122與掃描線SL。閘極122的材料可為銅、鉻(chromiun;Cr)、鎢(tungsten;W)、鈦(titanium;Ti)、鉭(tantalum;Ta)、鉬(Molybdenum;Mo)、其它適當的導電材料或上述至少兩種材料的組合,但本發明不以此為限。
舉例而言,在本實施例中,可利用化學氣相沉積(Chemical Vapor Deposition;CVD)形成第一絕緣層124,但本發明不以此為限。第一絕緣層124的材料可為二氧化矽(silicon dioxide;SiO2)、氮化矽(silicon nitride;Si3N4)、二氧化鉿(hafnium dioxide;HfO2)、或上述至少兩種材料的組合。然而,本發明不以此為限,在其他實施例中,第一絕緣層124也可為其他高介電常數(high dielectric constant)材料,以有效地電性隔離閘極122與半導體層126。
舉例而言,在本實施例中,可利用物理氣相沉積形成半導體材料層(未繪示);然後,再圖案化半導體材料層,進而形成半導體圖案126。在本實施例中,半導體圖案126例如是多個膜層的堆疊結構,所述多個膜層可包括半導體材料(未繪示)及歐姆接觸層(Ohmic contact layer;未繪示)。半導體圖案126之半導體材料可選擇性地採用氧化銦鎵鋅(Indium Gallium Zinc Oxide;IGZO)、氧化鉿銦鋅(Hafnium Indium Zinc Oxide;HIZO)、氧化銦鋅(Indium Zinc Oxide;IZO)或其他金屬氧化物,以使後續形成之薄膜電晶體120(標示於圖1D)在採用小面積之半導體圖案126的情況下仍具有高電子遷移率。然而,本發明不限於此,在其它實施例中,半導體圖案126的半導體材料也可採用其它適當種
類的半導體。此外,本發明也不限制半導體圖案126一定要包括歐姆接觸層。
請參考圖1A,接著,在本實施例中,可選擇性地於第一基板110上依序形成鉬材料層Mo及銅材料層Cu,其中鉬材料層Mo覆蓋半導體圖案126,銅材料層Cu配置於鉬材料層Mo上。舉例而言,在本實施例中,可利用物理氣相沉積(例如:濺射)形成鉬材料層Mo及銅材料層Cu,但本發明不以此為限。
請參考圖1B,接著,通入氮氣(nitrogen gas;N2),以在銅材料層Cu上形成氮化銅材料層CuN。請參照圖1A及圖1B,詳細而言,在形成具有預定膜厚的銅材料層Cu後(如圖1A所示),通入氮氣以使氮氣與銅材料層Cu的頂面區域Cu-t(標示於圖1A)反應,而形成氮化銅材料層CuN(如圖1B所示)。氮化銅材料層CuN可以化學式CuNm表示,其中m可為正整數。
請參照圖1B及圖1C,接著,圖案化氮化銅材料層CuN、銅材料層Cu及鉬材料層Mo,以使氮化銅材料層CuN形成第一氮化銅材料層CuN’-1及第二氮化銅材料層CuN’-2,使銅材料層Cu形成第一銅材料層Cu’-1及第二銅材料層Cu’-2,且使鉬材料層Mo形成第一鉬材料層Mo’-1及第二鉬材料層Mo’-2。在本實施例中,可使用同一圖案化光阻(patterned photoresist;未繪示)為罩幕,圖案化氮化銅材料層CuN、銅材料層Cu及鉬材料層Mo,以形成第一氮化銅材料層CuN’-1、第二氮化銅材料層CuN’-2、第一銅材料層Cu’-1、第二銅材料層Cu’-2、第一鉬材料層Mo’-1及第
二鉬材料層Mo’-2,其中第一氮化銅材料層CuN’-1、第一銅材料層Cu’-1及第一鉬材料層Mo’-1互相重合,第二氮化銅材料層CuN’-2、第二銅材料層Cu’-2及第二鉬材料層Mo’-2互相重合。
舉例而言,在本實施例中,可在所述圖案化光阻(未繪示)遮蔽氮化銅材料層CuN、銅材料層Cu及鉬材料層Mo的情況下,使用在同一種蝕刻液,同時去除氮化銅材料層CuN、銅材料層Cu及鉬材料層Mo中未被所述圖案化光阻遮蔽的部分,以形成第一氮化銅材料層CuN’-1、第二氮化銅材料層CuN’-2、第一銅材料層Cu’-1、第二銅材料層Cu’-2、第一鉬材料層Mo’-1及第二鉬材料層Mo’-2。然而,本發明不以此為限,在其他實施例中,也可在圖案化光阻(未繪示)遮蔽氮化銅材料層CuN、銅材料層Cu及鉬材料層Mo的情況下,使用在多種不同的蝕刻液,分次去除氮化銅材料層CuN、銅材料層Cu及鉬材料層Mo中未被圖案化光阻遮蔽的部分。
請參照圖1C及圖1D,接著,通入一氧化二氮(nitrous oxide;N2O),一氧化二氮至少與第一氮化銅材料層CuN’-1及第一銅材料層Cu’-1的側壁區域Cu’-1e反應,以形成第一氮氧化銅圖案層CuNO-1;其中,未暴露於一氧化二氮中之部分的第一銅材料層Cu’-1(亦即,側壁區域Cu’-1e以外之第一銅材料層Cu’-1的其它區域)則形成第一銅圖案層Cu-1。一氧化二氮與第二氮化銅材料層CuN’-2及第二銅材料層Cu’-2的側壁區域Cu’-2e反應,以形成第二氮氧化銅圖案層CuNO-2,其中,未暴露於一氧化二氮
中之部分的第二銅材料層Cu’-2(亦即,側壁區域Cu’-2e以外之第二銅材料層Cu’-2的其它區域)則形成第二銅圖案層Cu-2。第一氮氧化銅圖案層CuNO-1與第二氮氧化銅圖案層CuNO-2可以化學式CuNxOy表示,其中x與y為正整數。
請參照圖1D,在本實施例中,第一氮氧化銅圖案層CuNO-1覆蓋第一銅圖案層Cu-1。詳言之,第一銅圖案層Cu-1具有第一頂面Cu-1a、第一底面Cu-1b以及連接於第一底面Cu-1b與第一頂面Cu-1a之間的第一側壁Cu-1c,而第一氮氧化銅圖案層CuNO-1覆蓋第一頂面Cu-1a及第一側壁Cu-1c。第一銅圖案層Cu-1設置於第一氮氧化銅圖案層CuNO-1與第一鉬圖案層Mo-1之間。第一氮氧化銅圖案層CuNO-1與第一銅圖案層Cu-1可直接接觸。第一銅圖案層Cu-1與第一鉬圖案層Mo-1可直接接觸。類似地,第二銅圖案層Cu-2具有第二頂面Cu-2a、第二底面Cu-2b以及連接於第二底面Cu-2b與第二頂面Cu-2a之間的第二側壁Cu-2c,而第二氮氧化銅圖案層CuNO-2覆蓋第二頂面Cu-2a與第二側壁Cu-2c。第二銅圖案層Cu-2設置於第二氮氧化銅圖案層CuNO-2與第二鉬圖案層Mo-2之間。第二氮氧化銅圖案層CuNO-2與第二銅圖案層Cu-2可直接接觸。第二銅圖案層Cu-2與第二鉬圖案層Mo-2可直接接觸。
在本實施例中,部份的第一鉬圖案層Mo-1、部份的第一銅圖案層Cu-1以及部份的第一氮氧化銅圖案層CuNO-1可構成源極128a。另一部份的第一鉬圖案層Mo-1、另一部份的第一銅圖案
層Cu-1以及另一部份的第一氮氧化銅圖案層CuNO-1可構成汲極128b。源極128a與汲極128b結構上彼此分離且各自與半導體圖案126對應設置。在本實施例中,第二鉬圖案層Mo-2、第二銅圖案層Cu-2以及第二氮氧化銅圖案層CuNO-2可構成資料線DL,其中資料線DL與源極128a電性連接。閘極122、第一絕緣層124、半導體圖案126、源極128a以及汲極128b可構成薄膜電晶體120。在本實施例中,薄膜電晶體120是以底部閘極型薄膜電晶體(bottom gate TFT)為示例。然而,本發明不限於此,在其它實施例中,薄膜電晶體120也可為頂部閘極型薄膜電晶體(top gate TFT)或其它適當型式的薄膜電晶體。
在本實施例中,由於在第一頂面Cu-1a上之部分第一氮氧化銅圖案層CuNO-1與在第一側面Cu-1c上之部分第一氮氧化銅圖案層CuNO-1的形成過程不同,在第二頂面Cu-2b上之部分第二氮氧化銅圖案層CuNO-2與在第二側面Cu-2c上之部分第二氮氧化銅圖案層CuNO-2的形成過程不同,因此在第一頂面Cu-1a上之部分第一氮氧化銅圖案層CuNO-1的膜厚T1與在第一側面Cu-1c上之部分第一氮氧化銅圖案層CuNO-1的膜厚t1可能略有不同,在第二頂面Cu-2a上之部分第二氮氧化銅圖案層CuNO-2的膜厚T2與在第二側面Cu-2c上之部分第二氮氧化銅圖案層CuNO-2的膜厚t2可能略有不同。舉例而言,在本實施例中,在第一頂面Cu-1a上之部分第一氮氧化銅圖案層CuNO-1的膜厚T1可略微大於在第一側面Cu-1c上之部分第一氮氧化銅圖案層CuNO-1的膜厚t1,
在第二頂面Cu-2a上之部分第二氮氧化銅圖案層CuNO-2的膜厚T2可略微大於在第二側面Cu-2c上之部分第二氮氧化銅圖案層CuNO-2的膜厚t2。舉例而言,300ÅT1600Å,200Åt1500ÅÅ,300ÅT2600Å,而200Åt2500Å。然而,本發明不限於此,在其它實施例中,在第一頂面Cu-1a上之部分第一氮氧化銅圖案層CuNO-1的膜厚T1也可能實質上等於在第一側面Cu-1c上之部分第一氮氧化銅圖案層CuNO-1的膜厚t1,在第二頂面Cu-2a上之部分第二氮氧化銅圖案層CuNO-2的膜厚T2也可能實質上等於在第二側面Cu-2c上之部分第二氮氧化銅圖案層CuNO-2的膜厚t2。
請參考圖1E,在本實施例中,接著,通入矽烷(silane;SiH4),矽烷與上述的一氧化二氮反應,以形成氧化矽層130。氧化矽層130覆蓋源極128a與汲極128b。氧化矽層130覆蓋第一氮氧化銅圖案層CuNO-1及第二氮氧化銅圖案層CuNO-2,且與第一氮氧化銅圖案層CuNO-1及第二氮氧化銅圖案層CuNO-2接觸。氧化矽層130更覆蓋源極128a與汲極128b未覆蓋的部分的半導體圖案126。
請參考圖1F,接著,可在氧化矽層130中形成接觸窗H,以暴露出部份的汲極128b。然後,在氧化矽層130上形成畫素電極140,畫素電極140透過接觸窗H與汲極128b電性連接。於此,便完成了本實施例之半導體裝置100。
請參考圖1F及圖2,在本實施例中,掃描線SL與資料
線DL交叉設置。由圖2可知,掃描線SL與閘極122屬同一第一導電層,源極128a、汲極128b以及資料線DL屬同一第二導電層。資料線DL的表面具有第二氮氧化銅圖案層CuNO-2。源極128a的表面與汲極128b的表面具有第一氮氧化銅圖案層CuNO-1。值得一提的是,在本實施例中,由於源極128a與汲極128b的第一氮氧化銅圖案層CuNO-1及資料線DL的第二氮氧化銅圖案層CuNO-2具有緻密的材料結構,源極128a與汲極128b的第一氮氧化銅圖案層CuNO-1覆蓋源極128a與汲極128b的第一銅圖案層Cu-1,資料線DL的第二氮氧化銅圖案層CuNO-2覆蓋資料線DL的第二銅圖案層Cu-2。藉此,源極128a與汲極128b的第一銅圖案層Cu-1及資料線DL的第二銅圖案層Cu-2不易到外界水氣入侵入而降低產生劣化的情形。以下透過圖3、圖4及圖5舉例說明之。
圖3是依照比較例的半導體裝置的剖面示意圖。請參照圖1F及圖3,比較例的半導體裝置200與圖1F之本發明的實施例的半導體裝置100類似,兩者的差異在於:比較例之半導體裝置200的源極128a’與汲極128b’係由鉬圖案層Mo’與銅圖案層Cu’堆疊成,比較例之銅圖案層Cu’上未覆蓋有氮氧化銅圖案層。圖4是依照比較例的半導體裝置的局部於電子顯微鏡下的剖面影像。圖4之半導體裝置的局部剖面影像係對應圖3之半導體裝置200的局部R2的剖面。
請參見圖4,其示出比較例之半導體裝置200尚未進行高溫高濕測試前半導體裝置200之局部R2的剖面影像(如圖4之0
小時的欄位)及已進行高溫高濕測試1000小時後半導體裝置200之局部R2的剖面影像(如圖4之1000小時的欄位)。如圖4所示,由於銅圖案層Cu’與氧化矽層130的附著(adhesion)差,因此半導體裝置200經過1000小時的高溫高濕測試後,銅圖案層Cu’受到水氣入侵而向四周膨脹,進而造成薄膜電晶體產生漏電流的問題。
圖5是依照本發明的實施例的半導體裝置於電子顯微鏡下的局部剖面影像。圖5之半導體裝置的局部剖面影像係對應圖1F之半導體裝置100的局部R1的剖面。請參見圖5,其示出尚未進行高溫高濕測試前本發明之實施例的半導體裝置100之局部R1的剖面影像(如圖5之0小時的欄位)及已進行高溫高濕測試1000小時後半導體裝置100之局部R1的剖面影像(如圖5之1000小時的欄位)。如圖5所示,由於氮氧化銅圖案層(包括第一氮氧化銅圖案層CuNO-1與第二氮氧化銅圖案層CuNO-2)與氧化矽層130的附著(adhesion)佳,因此半導體裝置100經過1000小時的高溫高濕測試後,銅圖案層(包括第一銅圖案層Cu-1及第二銅圖案層Cu-2)不易受到水氣入侵,而薄膜電晶體120不易產生漏電流的問題,本實施例之半導體裝置100的信賴性佳。
綜上所述,在本發明的實施例的半導體裝置及其製造方法中,源極與汲極的至少一者的表面分別具有氮氧化銅圖案層,以及/或資料線的表面具有氮氧化銅圖案層,因氮氧化銅圖案層具有緻密的材料特性,及/或氮氧化銅圖案層與氧化矽層的附著佳。
藉此,外界水氣不易入侵源極與汲極之至少一者的銅圖案層,而本發明的實施例的半導體裝置的信賴性佳。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
Claims (10)
- 一種半導體裝置,包括:一第一基板;以及一薄膜電晶體,設置於該第一基板上,其中該薄膜電晶體包括:一閘極;一半導體圖案;一第一絕緣層,設置於該閘極與該半導體圖案之間;一源極以及一汲極,彼此分離且各自與該半導體圖案對應設置;其中,該源極與該汲極的至少一者具有一第一銅圖案層與一第一氮氧化銅圖案層,該第一氮氧化銅圖案層覆蓋該第一銅圖案層,且該第一銅圖案層設置於該第一氮氧化銅圖案層與該第一基板之間;該第一銅圖案層具有一第一頂面、一第一底面以及連接於該第一底面與該第一頂面之間的一第一側壁,而該第一氮氧化銅圖案層覆蓋該第一頂面及該第一側壁。
- 如申請專利範圍第1項所述的半導體裝置,其中該源極與該汲極的該至少一者更具有一第一鉬圖案層,該第一銅圖案層設置於該第一氮氧化銅圖案層與該第一鉬圖案層之間。
- 如申請專利範圍第1項所述的半導體裝置,更包括:一資料線,與該薄膜電晶體的該源極電性連接,其中該資料線具有一第二銅圖案層與一第二氮氧化銅圖案層,該第二氮氧化銅圖案層覆蓋該第二銅圖案層,且該第二銅圖案層設置於該第二氮氧化銅圖案層與該第一基板之間。
- 如申請專利範圍第3項所述的半導體裝置,其中該第二銅圖案層具有一第二頂面、一第二底面以及連接於該第二底面與該第二頂面之間的一第二側壁,而該第二氮氧化銅圖案層覆蓋該第二頂面及該第二側壁。
- 如申請專利範圍第3項所述的半導體裝置,其中該資料線更具有一第二鉬圖案層,該第二銅圖案層設置於該第二氮氧化銅圖案層與該第二鉬圖案層之間。
- 如申請專利範圍第1項所述的半導體裝置,其中該第一氮氧化銅圖案層直接與該第一銅圖案層接觸。
- 如申請專利範圍第1項所述的半導體裝置,更包括:一氧化矽層,覆蓋該第一氮氧化銅圖案層,且與該第一氮氧化銅圖案層接觸。
- 如申請專利範圍第1項所述的半導體裝置,更包括:一畫素電極,與該汲極電性連接。
- 一種半導體裝置的製造方法,包括:提供一第一基板;於該第一基板上形成一閘極、一第一絕緣層以及一半導體圖案,其中該第一絕緣層設置於該閘極與該半導體圖案之間;利用一物理氣相沉積在該第一基板上形成一銅材料層;通入氮氣,以在該銅材料層上形成一氮化銅材料層;圖案化該銅材料層與該氮化銅材料層,以形成一第一銅材料層與一第一氮化銅材料層;以及通入一氧化二氮,以形成一第一氮氧化銅圖案層與一第一銅圖案層,該第一氮氧化銅圖案層覆蓋該第一銅圖案層,其中該第一銅圖案層以及該第一氮氧化銅圖案層構成一源極與一汲極,而該源極與該汲極彼此分離且各自與該半導體圖案對應設置。
- 如申請專利範圍第9項所述的半導體裝置的製造方法,更包括:在形成該第一氮氧化銅圖案層之後,通入矽烷,該矽烷與該一氧化二氮反應,以形成一氧化矽層,其中該氧化矽層覆蓋該源極與該汲極。
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200727491A (en) * | 2005-11-08 | 2007-07-16 | Samsung Electronics Co Ltd | Thin film transistor substrate for display |
CN103765597A (zh) * | 2012-11-02 | 2014-04-30 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制作方法、阵列基板、显示装置和阻挡层 |
EP2916360A1 (en) * | 2012-11-02 | 2015-09-09 | BOE Technology Group Co., Ltd. | Thin film transistor and manufacturing method, array substrate, display device and barrier layer thereof |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101012491B1 (ko) * | 2003-12-04 | 2011-02-08 | 엘지디스플레이 주식회사 | 액정표시장치용 어레이기판과 제조방법 |
KR20080008562A (ko) | 2006-07-20 | 2008-01-24 | 삼성전자주식회사 | 어레이 기판의 제조방법, 어레이 기판 및 이를 갖는표시장치 |
KR20090024383A (ko) * | 2007-09-04 | 2009-03-09 | 삼성전자주식회사 | 박막 트랜지스터 표시판, 이의 제조 방법 및 이를 포함하는표시 장치 |
TWI425639B (zh) * | 2007-10-22 | 2014-02-01 | Au Optronics Corp | 一種薄膜電晶體及其製造方法 |
KR101296654B1 (ko) | 2007-12-26 | 2013-08-14 | 엘지디스플레이 주식회사 | 구리 배선, 이를 이용한 평판 표시 장치, 및 그 구리배선의 형성 방법 |
US8270178B2 (en) * | 2010-03-22 | 2012-09-18 | Au Optronics Corporation | Active device array substrate |
JP2012027159A (ja) * | 2010-07-21 | 2012-02-09 | Kobe Steel Ltd | 表示装置 |
JP5171990B2 (ja) * | 2011-05-13 | 2013-03-27 | 株式会社神戸製鋼所 | Cu合金膜および表示装置 |
WO2013080247A1 (ja) * | 2011-11-29 | 2013-06-06 | パナソニック株式会社 | 薄膜トランジスタおよび薄膜トランジスタの製造方法 |
KR102030227B1 (ko) * | 2015-05-08 | 2019-10-08 | 주식회사 엘지화학 | 박막트랜지스터 기판 및 이를 포함하는 디스플레이 장치 |
US10373732B2 (en) * | 2015-07-16 | 2019-08-06 | Kaneka Corporation | Transparent electrode film, dimming element, and method for manufacturing transparent electrode film |
-
2018
- 2018-05-02 TW TW107114836A patent/TWI671913B/zh active
- 2018-06-12 CN CN201810601974.3A patent/CN108807550B/zh active Active
- 2018-11-01 US US16/177,464 patent/US20190341494A1/en not_active Abandoned
-
2020
- 2020-11-03 US US17/088,525 patent/US11367795B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200727491A (en) * | 2005-11-08 | 2007-07-16 | Samsung Electronics Co Ltd | Thin film transistor substrate for display |
CN103765597A (zh) * | 2012-11-02 | 2014-04-30 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制作方法、阵列基板、显示装置和阻挡层 |
EP2916360A1 (en) * | 2012-11-02 | 2015-09-09 | BOE Technology Group Co., Ltd. | Thin film transistor and manufacturing method, array substrate, display device and barrier layer thereof |
Also Published As
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US20210050454A1 (en) | 2021-02-18 |
TW201947774A (zh) | 2019-12-16 |
CN108807550B (zh) | 2021-04-27 |
US20190341494A1 (en) | 2019-11-07 |
US11367795B2 (en) | 2022-06-21 |
CN108807550A (zh) | 2018-11-13 |
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