TWI647764B - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TWI647764B
TWI647764B TW104121285A TW104121285A TWI647764B TW I647764 B TWI647764 B TW I647764B TW 104121285 A TW104121285 A TW 104121285A TW 104121285 A TW104121285 A TW 104121285A TW I647764 B TWI647764 B TW I647764B
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patterned mask
fin structures
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馮立偉
蔡世鴻
林昭宏
洪世芳
鄭志祥
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聯華電子股份有限公司
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Priority to US14/816,081 priority patent/US9704737B2/en
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Priority to US15/610,574 priority patent/US9859148B2/en
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    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract

本發明揭露一種製作半導體元件的方法。首先提供一基底，該基底上具有一第一區域、一第二區域以及一第三區域，然後形成複數個側壁子於第一區域、該第二區域及第三區域，形成一第一圖案化遮罩覆蓋第一區域及二區域之側壁子，以及去除第三區域之側壁子。

Description

半導體元件及其製作方法
本發明是關於一種製作場效電晶體的方法，尤指一種同時與基底上製作平面型場效電晶體、鰭狀場效電晶體以及靜態隨機存取記憶體的方法。
隨著半導體元件尺寸的縮小，維持小尺寸半導體元件的效能是目前業界的主要目標。然而，隨著場效電晶體(field effect transistors,FETs)元件尺寸持續地縮小，平面式(planar)場效電晶體元件的發展已面臨製程上之極限。非平面(non-planar)式場效電晶體元件，例如鰭狀場效電晶體(fin field effect transistor,Fin FET)元件，具有立體結構可增加與閘極之間接觸面積，進而提升閘極對於通道區域的控制，儼然已取代平面式場效電晶體成為目前的主流發展趨勢。
現有鰭狀場效電晶體的製程是先將鰭狀結構形成於基底上，再將閘極形成於鰭狀結構上。鰭狀結構一般為蝕刻基底所形成的條狀鰭片，但在尺寸微縮的要求下，各鰭片寬度漸窄，而鰭片之間的間距也漸縮小。因此，其製程也面臨許多限制與挑戰，例如現有遮罩及微影蝕刻技術受限於微小尺寸的限制，無法準確定義鰭狀結構的位置而造成鰭片倒塌，或是無法準確控制蝕刻時間而導致過度蝕刻等問題，連帶影響鰭狀結構的作用效能。
本發明較佳實施例揭露一種製作半導體元件的方法。首先提供一基底，該基底上具有一第一區域、一第二區域以及一第三區域，然後形成複數個側壁子於第一區域、該第二區域及第三區域，形成一圖案化遮罩覆蓋第一區域及二區域之側壁子，以及去除第三區域之側壁子。
本發明另一實施例揭露一種半導體元件，包含：一基底具有一第一區域及一第二區域、一第一基座設於第一區域以及一第二基座設於第二區域、複數個第一鰭狀結構設於第一基座上、單一第二鰭狀結構設於第二基座上、一第一淺溝隔離設於第一鰭狀結構及第二鰭狀結構之間以及一第二淺溝隔離設於第二鰭狀結構旁。
12‧‧‧基底
14‧‧‧第一區域
16‧‧‧第二區域
18‧‧‧第三區域
20‧‧‧襯墊氧化層
22‧‧‧襯墊氮化層
24‧‧‧軸心體
26‧‧‧側壁子
28‧‧‧第一圖案化遮罩
30‧‧‧第二圖案化遮罩
32‧‧‧第一鰭狀結構
34‧‧‧第二鰭狀結構
36‧‧‧第三圖案化遮罩
38‧‧‧基座
40‧‧‧基座
42‧‧‧基座
44‧‧‧凹槽
46‧‧‧凹槽
48‧‧‧凹槽
50‧‧‧第四圖案化遮罩
52‧‧‧凹槽
54‧‧‧淺溝隔離
56‧‧‧淺溝隔離
58‧‧‧側壁
60‧‧‧側壁
62‧‧‧側壁
64‧‧‧側壁
72‧‧‧基底
74‧‧‧第一區域
76‧‧‧第二區域
78‧‧‧第三區域
80‧‧‧襯墊氧化層
82‧‧‧襯墊氮化層
84‧‧‧側壁子
86‧‧‧第二圖案化遮罩
88‧‧‧第三圖案化遮罩
90‧‧‧第一鰭狀結構
92‧‧‧第二鰭狀結構
94‧‧‧第四圖案化遮罩
96‧‧‧基座
98‧‧‧基座
100‧‧‧凹槽
102‧‧‧基底
104‧‧‧第一區域
106‧‧‧第二區域
108‧‧‧第三區域
110‧‧‧襯墊氧化層
112‧‧‧襯墊氮化層
114‧‧‧側壁子
116‧‧‧第二圖案化遮罩
118‧‧‧第一鰭狀結構
120‧‧‧第三圖案化遮罩
122‧‧‧第二鰭狀結構
124‧‧‧第四圖案化遮罩
126‧‧‧基座
128‧‧‧基座
130‧‧‧凹槽
第1圖至第7圖為本發明第一實施例製作一半導體元件之方法示意圖。
第8圖至第11圖為本發明第二實施例製作一半導體元件之方法示意圖。
第12圖至第14圖為本發明第三實施例製作一半導體元件之方法示意圖。
請參照第1圖至第7圖，第1圖至第7圖為本發明第一實施例製作一半導體元件之方法示意圖。如第1圖所示，首先提供一基底12，例如一矽基底，且基底12上具有一第一區域14、一第二區域16以及一第三區域18。其中第一區域14、第二區域16與第三區域18較佳於後續製程中依據產品的需求來製作不同型態的半導體元件，例如在本實施例中，第一區域14較佳為邏輯區且用來製作鰭狀結構電晶體，第二區域16較佳為記憶體區且用來製作靜態隨機存取記憶體(SRAM)，第三區域18則用來製作平面型金氧半導體元件。
然後依序形成一襯墊氧化層20、一襯墊氮化層22以及一材料層(圖未示)於基底12上，並利用側壁圖案轉移(sidewall image transfer,SIT)技術形成複數個側壁子於襯墊氮化層22上。舉例來說，可進行一微影暨蝕刻製程，例如先形成一圖案化光阻於材料層上，並以圖案化光阻為遮罩進行一蝕刻製程，去除部分材料層以形成複數個軸心體(mandrels)24於襯墊氮化層22上。接著形成一遮蓋層於軸心體24與襯墊氮化層22上，再利用回蝕刻去除部分遮蓋層，以形成複數個側壁子26於第一區域14、第二區域16及第三區域18。
然後如第2圖所示，先去除所有的軸心體24，再形成一第一圖案化遮罩28覆蓋第一區域14及第二區域16的側壁子26，並利用第一圖案化遮罩28進行一蝕刻製程去除第三區域18的所有側壁子26以暴露出襯墊氮化層22表面。
在去除第一圖案化遮罩28之後，接著如第3圖所示，形成一第二圖案化遮罩30於第三區域18，並利用第二圖案化遮罩30與第一區域14及第二區域16的側壁子26進行一蝕刻製程，去除部分第一區域14與第二區域16的基底12以形成複數個第一鰭狀結構32於第一區域14以及複數個第二鰭狀結構34於第二區域16。
然後如第4圖所示，形成一第三圖案化遮罩36於部分第一鰭狀結構32及部分第二鰭狀結構34上。
如第5圖所示，接著利用第二圖案化遮罩30與第三圖案化遮罩36進行一蝕刻製程，去除部分未被第二圖案化遮罩30與第三圖案化遮罩36所覆蓋的側壁子26、襯墊氮化層22、襯墊氧化層20、第一鰭狀結構32以及第二鰭狀結構34，然後繼續利用第二圖案化遮罩30與第三圖案化遮罩36為遮罩往下蝕刻去除部分基底12，以形成一基座38於第三區域18、一基座40於第一鰭狀結構32下方、複數個基座42於第二鰭狀結構34下方、一凹槽44位於基座38與基座40之間、一凹槽46於基座40與基座42之間以及凹槽48於基座42之間。需注意的是，在此時間點第一區域14的基座40與第二區域16的基座42上仍各設有複數個鰭狀結 構，例如基座40上設有四根第一鰭狀結構32而各基座42上則設有兩根第二鰭狀結構34。
然後如第6圖所示，去除第二圖案化遮罩30與第三圖案化遮罩36並形成一第四圖案化遮罩50覆蓋第三區域18、第一區域14及第二區域16的第二鰭狀結構34，接著利用第四圖案化遮罩50進行一蝕刻製程，去除部分位於第二區域16的基座42，例如將原本基座42劃分為二並同時形成一另一凹槽52於第二鰭狀結構34之間。值得注意的是，在此時間點第一區域14的基座40上仍設有複數個第一鰭狀結構32，但第二區域16的各基座42上則僅設有單一一根第二鰭狀結構34。
隨後去除第四圖案化遮罩50，再如第7圖所示，進行一淺溝隔離製程，例如可沉積一由氧化矽所構成的絕緣層(圖未示)於基底12上並填滿基座38、40、42之間的凹槽44、46、48、52，然後先平坦化部分絕緣層再以回蝕刻去除部分絕緣層以形成複數個淺溝隔離54於第一鰭狀結構32與第二鰭狀結構34之間以及淺溝隔離56於基座42之間的凹槽52內。之後可依據製程需求選擇性去除側壁子26、襯墊氮化層22與襯墊氧化層20，然後形成閘極結構於各鰭狀結構與基座38、40、42上，並進行後續主動元件的製程，以於第一區域14、第二區域16與第三區域18分別形成所需的鰭狀結構電晶體、靜態隨機存取記憶體以及平面型金氧半導體電晶體。至此即完成本發明第一實施例之半導體元件的製作。
又如第7圖所示，本發明另揭露一種半導體元件結構，其主 要包含一基座40設於基底12上的第一區域14、至少一基座42設於第二區域16、一基座38設於第三區域18、複數個第一鰭狀結構32設於基座40上、單一第二鰭狀結構34設於各基座42上、淺溝隔離54設於第一鰭狀結構32與第二鰭狀結構34之間以及淺溝隔離56設於基座42之間。
在本實施例中，基底38、40、42、第一鰭狀結構32及第二鰭狀結構34均包含相同材料，例如均由單晶矽所構成。其次，第三區域18的基座38上表面較佳高於第一區域14的基座40與第二區域16的基座42上表面，第一區域14的基座40上表面則較佳切齊第二區域16的基座42上表面。淺溝隔離54與淺溝隔離56較佳包含不同深度，其中基座40與基座42之間的淺溝隔離54深度約為840埃，設於基座40上方的淺溝隔離54深度約為140埃，基座42之間的淺溝隔離56深度則約為1400埃。
另外從第二區域16的細部來看，各基座42較佳具有側壁58及側壁60且設於其上的第二鰭狀結構34也具有側壁62與側壁64，其中基座42的側壁58較佳與第二鰭狀結構34的側壁62對齊但基座42的另一側壁60則較佳不與第二鰭狀結構34的另一側壁64對齊。
請參照第8圖至第11圖，第8圖至第11圖為本發明第二實施例製作一半導體元件之方法示意圖。如第8圖所示，首先提供一基底72，例如一矽基底，且基底72上具有一第一區域74、一第二區域76以及一第三區域78。其中第一區域74、第二區域76與第三區域78較佳於後續製程中依據產品的需求來製作不同型態的半導體元件，例如在本實施例中，第一區域74較佳為邏輯區且用來製作鰭狀結構電晶體，第二區 域76較佳為記憶體區且用來製作靜態隨機存取記憶體(SRAM)，第三區域78則用來製作平面型金氧半導體元件。
然後依序形成一襯墊氧化層80、一襯墊氮化層82於基底72上，並比照第1圖至第2圖的製程，先利用側壁圖案轉移(sidewall image transfer,SIT)技術形成複數個側壁子84於第一區域74、第二區域76及第三區域78，形成一第一圖案化遮罩(圖未示)覆蓋第一區域74及第二區域76之側壁子84，並利用第一圖案化遮罩進行一蝕刻製程去除第三區域78的所有側壁子84並暴露出襯墊氮化層82表面。接著去除第一圖案化遮罩，形成一第二圖案化遮罩86於第一區域74與第三區域78。
然後如第9圖所示，利用第二圖案化遮罩86進行一蝕刻製程去除第二區域76的部分基底72。
接著先去除第二圖案化遮罩86，然後如第10圖所示，形成一第三圖案化遮罩88於第三區域78，並利用第三圖案化遮罩88進行一蝕刻製程，去除第一區域74與第二區域76的部分基底72以形成複數個第一鰭狀結構90及複數個第二鰭狀結構92。其中第一鰭狀結構90與第二鰭狀結構92的上表面較佳齊平，但第二鰭狀結構92的高度較佳高於第一鰭狀結構90的高度。
如第11圖所示，隨後形成一第四圖案化遮罩94覆蓋第一區域74的部分第一鰭狀結構90與第二區域76的部分第二鰭狀結構92，並進行一道或一道以上的蝕刻製程，去除未被第四圖案化遮罩94所覆蓋的 側壁子84、襯墊氮化層82、襯墊氧化層80、部分第一鰭狀結構90及部分第二鰭狀結構92，接著去除部分基底72以形成一基座96位於第一鰭狀結構90下方、一基座98位於第三區域78以及凹槽100位於第一鰭狀結構90與第二鰭狀結構92之間以及基座96、98之間，其中凹槽100的底部較佳與第二鰭狀結構92的底部齊平。之後可比照前述第7圖進行一淺溝隔離製程，以於凹槽100內以及第一鰭狀結構90與第二鰭狀結構92之間形成所需的淺溝隔離結構，在此不另加贅述。
請參照第12圖至第14圖，第12圖至第14圖為本發明第三實施例製作一半導體元件之方法示意圖。如第12圖所示，首先提供一基底102，例如一矽基底，且基底102上具有一第一區域104、一第二區域106以及一第三區域108。其中第一區域104、第二區域106與第三區域108較佳於後續製程中依據產品的需求來製作不同型態的半導體元件，例如在本實施例中，第一區域104較佳為邏輯區且用來製作鰭狀結構電晶體，第二區域106較佳為記憶體區且用來製作靜態隨機存取記憶體(SRAM)，第三區域108則用來製作平面型金氧半導體元件。
然後依序形成一襯墊氧化層110、一襯墊氮化層112於基底102上，並比照第1圖至第2圖的製程，先利用側壁圖案轉移(sidewall image transfer,SIT)技術形成複數個側壁子114於第一區域104、第二區域106及第三區域108，形成一第一圖案化遮罩(圖未示)覆蓋第一區域104及第二區域106之側壁子，並利用第一圖案化遮罩進行一蝕刻製程去除第三區域108的所有側壁子114並暴露出襯墊氮化層112表面。
接著去除第一圖案化遮罩，形成一第二圖案化遮罩116於第三區域108，並利用第二圖案化遮罩116進行一蝕刻製程去除部分基底102以形成複數個第一鰭狀結構118於第一區域104與第二區域106。
然後如第13圖所示，形成一第三圖案化遮罩120並覆蓋第一區域104的第一鰭狀結構118，然後同時利用第二圖案化遮罩116與第三圖案化遮罩120進行一蝕刻製程，去除第二區域106的部分基底102以形成複數個第二鰭狀結構122。
隨後如第14圖所示，先去除第三圖案化遮罩120，形成一第四圖案化遮罩124覆蓋第一區域104的部分第一鰭狀結構118與第二區域106的部分第二鰭狀結構122。接著利用第二圖案化遮罩116與第四圖案化遮罩124進行一道或一道以上蝕刻製程，去除部分未被第二圖案化遮罩116與第四圖案化遮罩124所覆蓋的側壁子114、襯墊氮化層112、襯墊氧化層110、第一鰭狀結構118及第二鰭狀結構122，然後去除部分基底102以形成一基座126於第一鰭狀結構118下方、一基座128位於第三區域108以及凹槽130位於第一鰭狀結構118與第二鰭狀結構122之間以及基座126、128之間，其中凹槽130的底部較佳與第二鰭狀結構122的底部齊平。之後可比照前述第7圖進行一淺溝隔離製程，以於凹槽130內以及第一鰭狀結構118與第二鰭狀結構122之間形成所需的淺溝隔離結構，在此不另加贅述。
綜上所述，本發明可依據上述製程於基底上的不同區域製作不同型態的半導體元件，例如於第一區域14之邏輯區形成鰭狀結構電 晶體，於第二區域16之記憶體區製作靜態隨機存取記憶體(SRAM)，以及於第三區域18製作平面型金氧半導體元件。以上述第一實施例而言，第一區域的基座上設有複數個鰭狀結構，第二區域的各基座上僅設置單一鰭狀結構，第三區域則僅具有基座但無鰭狀結構，另外第一區域與第二區域之間的淺溝隔離也較佳與第二區域的淺溝隔離之一者具有不同深度。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。

Claims (15)

  1. 一種製作半導體元件的方法，包含：提供一基底，該基底上具有一第一區域、一第二區域以及一第三區域；形成複數個軸心體於該第一區域、該第二區域以及該第三區域上；形成複數個側壁子於該等軸心體旁；去除該等軸心體；於去除該等軸心體後形成一第一圖案化遮罩覆蓋該等第一區域及該第二區域之該等側壁子；以及去除該第三區域之該等側壁子。
  2. 如申請專利範圍第1項所述之方法，另包含：形成一襯墊氧化層於該基底上；形成一襯墊氮化層於該襯墊氧化層上；形成該等軸心體於該襯墊氮化層上；形成一遮蓋層於該等軸心體上；去除部分該遮蓋層；以及去除該等軸心體以形成該等側壁子於該第一區域、該第二區域及該第三區域。
  3. 如申請專利範圍第1項所述之方法，另包含：去除該第一圖案化遮罩；形成一第二圖案化遮罩於該第三區域； 去除部分該基底以形成複數個第一鰭狀結構於該第一區域以及複數個第二鰭狀結構於該第二區域；形成一第三圖案化遮罩於部分該等第一鰭狀結構及部分該等第二鰭狀結構上；去除部分該等第一鰭狀結構及部分該等第二鰭狀結構；以及去除部分該基底以形成一第一基座設於該第一鰭狀結構下方、一第二基座設於該第二鰭狀結構下方以及一第一凹槽於該第一基座與該第二基座之間。
  4. 如申請專利範圍第3項所述之方法，另包含：去除該第二圖案化遮罩及該第三圖案化遮罩；形成一第四圖案化遮罩於該第三區域，該第一區域及該等第二鰭狀結構；以及去除部分位於該第二區域之該第二基座以形成一第二凹槽於該等第二鰭狀結構之間。
  5. 如申請專利範圍第4項所述之方法，其中該第一凹槽及該第二凹槽之深度不同。
  6. 如申請專利範圍第1項所述之方法，另包含：去除該第一圖案化遮罩；形成一第二圖案化遮罩於該第一區域及該第三區域；去除該第二區域之部分該基底；去除該第二圖案化遮罩； 形成一第三圖案化遮罩於該第三區域；去除該第一區域及該第二區域之部分該基底以形成複數個第一鰭狀結構及複數個第二鰭狀結構；形成一第四圖案化遮罩於該第一區域及該第二區域；去除部分該等第一鰭狀結構及部分該等第二鰭狀結構；以及去除部分該基底以形成一基座位於該等第一鰭狀結構下方以及一凹槽位於該等第一鰭狀結構及該等第二鰭狀結構之間。
  7. 如申請專利範圍第6項所述之方法，其中該凹槽之底部與該等第二鰭狀結構之底部齊平。
  8. 如申請專利範圍第1項所述之方法，另包含：去除該第一圖案化遮罩；形成一第二圖案化遮罩於該第三區域；去除部分該基底以形成複數個第一鰭狀結構於該第一區域及該第二區域；形成一第三圖案化遮罩於該第一區域之該等第一鰭狀結構；去除該第二區域之部分該基底以形成複數個第二鰭狀結構；去除該第三圖案化遮罩；形成一第四圖案化遮罩於該第一區域及該第二區域；去除部分該等第一鰭狀結構及部分該等第二鰭狀結構；以及去除部分該基底以形成一基座於該等第一鰭狀結構下方以及一凹槽位於該等第一鰭狀結構及該等第二鰭狀結構之間。
  9. 如申請專利範圍第8項所述之方法，其中該凹槽之底部與該等第二鰭狀結構之底部齊平。
  10. 一種半導體元件，包含：一基底，該基底具有一第一區域、一第二區域以及一第三區域；一第一基座設於該第一區域以及一第二基座設於該第二區域；複數個第一鰭狀結構設於該第一基座上；單一第二鰭狀結構設於該第二基座上；一第一淺溝隔離設於該等第一鰭狀結構及該第二鰭狀結構之間；一第二淺溝隔離設於該第二鰭狀結構旁；以及一第三基座設於該第三區域，其中該第三基座之上表面高於該第一基座及該第二基座之上表面。
  11. 如申請專利範圍第10項所述之半導體元件，其中該基底、該第一基座、該第二基座、該第三基座、該等第一鰭狀結構及該第二鰭狀結構包含相同材料。
  12. 如申請專利範圍第10項所述之半導體元件，其中該第一淺溝隔離與該第二淺溝隔離包含不同深度。
  13. 如申請專利範圍第10項所述之半導體元件，另包含一第三淺溝隔離設於該第一基座及該第三基座之間。
  14. 如申請專利範圍第13項所述之半導體元件，其中該第一淺溝隔離、該第二淺溝隔離及該第三淺溝隔離之上表面齊平。
  15. 如申請專利範圍第10項所述之半導體元件，其中該第二基座之一第一側壁與該第二鰭狀結構之一第二側壁對齊且該第二基座之一第三側壁不與該第二鰭狀結構之一第四側壁對齊。
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