TWI314349B

TWI314349B - Method for forming spacers with different widths

Info

Publication number: TWI314349B
Application number: TW92101177A
Authority: TW
Inventors: Mingta Lei; Yihshung Lin; Aisen Liu; Chengchung Lin; Baw Ching Perng; Chiahui Lin
Original assignee: Taiwan Semiconductor Mfg
Priority date: 2003-01-20
Filing date: 2003-01-20
Publication date: 2009-09-01
Also published as: TW200414403A

Description

1314349 ㈣ ---Ά 92101177_年月日修正 , 五、發明說明（1) 發明所屬之技術領域本發明是有關於一種形成間隙壁之方法，且特別是有關於一種形成多種寬度間隙壁之方法。先前技術間隙壁係半導體製程中不可或缺的一部份，舉例來說，在閘極結構中為了處理短通道效應’便需要形成間隙壁的結構。除了在間極結構，在各種半導體的不同部分亦可常見到間隙壁的蹤影，舉例來說，在溝渠（Trench)亦為了滿足電性或物性而有使用間隙壁的情形。 =隙壁的寬度會影響其產生的性質，而對於曰益精細的半BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of forming a spacer, and more particularly to a method of forming a plurality of width spacers. . Prior Art An integral part of the gap-wall semiconductor process, for example, in order to handle short-channel effects in the gate structure, requires the formation of a spacer structure. In addition to the interpole structure, traces of the spacers are also common in different parts of various semiconductors. For example, in the Trench, there is a case where spacers are used in order to satisfy electrical or physical properties. = the width of the gap will affect the nature of its creation, and for the fine half

，體工業而言，能否製作所需規格的間隙壁因此變非常重要的事。 A IT 隨著電子技術的進步，晶片中能夠存放的電路元件不斷增加。隨著其應用越來越廣泛與多樣化，晶片内路構造也越來越複雜。 ' 舉例來說，在系統整合晶片（soc)或其他曰益常見的應用中’往往需要在不同區域使用不同性質的電路元件，而當這些電路元件又往往需要不同寬度的間隙壁之需求規格: 一種習知的做法’是分區域分別製作間隙壁。然而如此做的問題在於反覆的動作需要多次的光罩數目，同時非作 . 區域往往會有摻雜區域遭到蝕刻污染的問題。、因此’在今日及可見的未來，由於多種寬度的間隙壁的需In the industry, it is very important to be able to make the gaps of the required specifications. A IT With the advancement of electronic technology, the number of circuit components that can be stored in a wafer is increasing. As its applications become more diverse and diverse, the internal structure of the wafer is becoming more complex. For example, in system-integrated wafers (soc) or other common applications, it is often necessary to use circuit components of different nature in different regions, and when these circuit components often require gaps of different widths: A conventional practice is to create gaps in separate regions. However, the problem with this is that the repeated actions require multiple reticle counts, and at the same time, the area tends to have etched contamination of the doped regions. Therefore, in today's and visible future, due to the need for multiple width spacers

1314349 _案號92101177_年月曰修正_ 五、發明說明（2) 求增加的情況下，如果能夠找出一個有效且具有彈性，又能夠保護非作業區域的間隙壁之製作方法，將對日益複雜的半導體工業帶來重大的貢獻。發明内容因此本發明的目的就是在提供一種能夠形成多種寬度的間隙壁之有效方法。依照本發明一較佳實施例包括下列步驟。首先，提供一基材，而此基材上具有多數個需要在其侧面形成間隙壁的結構，這些結構分布在多個區域中。換句話說，需要不同寬度間隙壁的結構位於在不同的作業區域中。接著，將多層蝕刻選擇比不同的介電層，以堆疊式沉積於一基材上，其中相鄰介電層具有不同钱刻選擇比，並且此介電層之物質係用來作為間隙壁的材料。然後，基於不同的間隙壁寬度需要，選擇性的使用一次以上的微影蝕刻作業。此處所謂的微影蝕刻作業包括下列步驟。第一步在介電層上形成圖案化光阻，以曝露若干作業區域。第二步在此曝露出之作業區域中進行選擇性蝕刻，例如利用鄰近介電層不同的蝕刻選擇比，以達成所需的介電層層數。第三步則是將光阻移除，以進行後續的步驟。藉由至少一次的微影蝕刻作業，使得不同作業區域的介電層保留不同的層數或形狀。最後，再透過一次非等向蝕刻，將不必要的介電層物質去除，如此便能使不同作業區域的間隙壁具有不同的寬度。1314349 _ Case No. 92101177_ Year of the month 曰 Amendment _ V. Invention description (2) In the case of an increase, if it is possible to find a method that is effective and flexible and can protect the non-working area, it will become increasingly The complex semiconductor industry has made a significant contribution. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an efficient method of forming a plurality of width gap walls. A preferred embodiment in accordance with the present invention includes the following steps. First, a substrate is provided which has a plurality of structures on the sides thereof which need to form spacers which are distributed in a plurality of regions. In other words, structures requiring different width spacers are located in different work areas. Then, the multilayer etching is selected to be deposited on a substrate in a stacked manner with different dielectric layers, wherein the adjacent dielectric layers have different cost-selection ratios, and the material of the dielectric layer is used as a spacer. material. Then, one or more lithography etching operations are selectively used based on different spacer width requirements. The so-called lithography etching operation herein includes the following steps. The first step is to form a patterned photoresist on the dielectric layer to expose a number of working areas. The second step is to selectively etch in the exposed exposed regions, e.g., using different etch selectivity ratios of adjacent dielectric layers to achieve the desired number of dielectric layers. The third step is to remove the photoresist for the next steps. The dielectric layer of the different work areas retains a different number of layers or shapes by at least one lithography etching operation. Finally, the unnecessary dielectric layer material is removed by an anisotropic etch, so that the spacers of different working areas have different widths.

第9頁 1314349 _案號92101177_年月曰修正_ 五、發明說明（3) 因此，本發明不但提供了一個容易規劃的製作方法，且此製作方法可使用於一整個晶片或晶片的局部區域，具有相當大的彈性。此外，預先形成的介電層亦可作為對基材及其上結構的保護，以避免間隙壁形成過程出現不必要的污染。所以，本發明確實提出有效的方法解決了目前的問題，因此對日趨複雜的半導體製造提出了重大的貢獻。實施方式本發明係提供一種能夠形成多種間隙壁寬度的方法，以下將提供一具體實施例以說明此方法。首先，請參看第1圖，此圖為一個積體電路晶片1 〇的示意圖。晶片1 0由計算模組1卜控制模組1 2、第一記憶體1 3、第二記憶體1 4，以及通訊模組1 5幾個部分組成。此圖為一個系統單晶片（SoC)，在此僅作為例示以說明本發明而非用以限制本發明之範圍。晶片1 0的各模組間電路往往具有不同的特性，舉例來說，即使同樣是CMOS邏輯閘，但因為其作為通訊、記憶體、或計算等不同用途，其所需的間隙壁的寬度將有不同的要求，藉此以達成不同特性的電路元件。因此，在此晶片10製造的過程中，對於不同的區域内電路元件，便產生不同寬度的間隙壁的需求。在此例子中，因為電路元件需要具有不同寬度之間隙壁，我們將晶片1 〇分為計算模組11、控制模組1 2、第一記憶體1 3、第二記憶體Page 9 1314349 _ Case No. 92101177_Yearly Revision _ V. Invention Description (3) Therefore, the present invention not only provides an easy-to-plan fabrication method, but also can be used for a partial area of an entire wafer or wafer. , with considerable flexibility. In addition, the pre-formed dielectric layer can also serve as a protection to the substrate and its structure to avoid unwanted contamination during the formation of the spacers. Therefore, the present invention does provide an effective method to solve the current problem, and thus contributes significantly to the increasingly complex semiconductor manufacturing. Embodiments The present invention provides a method of forming a plurality of spacer widths, and a specific embodiment will be provided below to illustrate the method. First, please refer to Fig. 1, which is a schematic diagram of an integrated circuit chip 1 。. The chip 10 is composed of a computing module 1 , a control module 1 2 , a first memory 1 3 , a second memory 14 , and a communication module 15 . The present invention is a system single-chip (SoC), which is intended to be illustrative only and not to limit the scope of the invention. The inter-module circuits of the chip 10 tend to have different characteristics. For example, even if it is also a CMOS logic gate, the width of the required spacers will be different because of its use as a communication, memory, or calculation. There are different requirements for achieving circuit components of different characteristics. Therefore, during the manufacture of the wafer 10, the need for spacers of different widths is produced for circuit components in different regions. In this example, since the circuit components need to have spacers having different widths, we divide the wafer 1 into a calculation module 11, a control module 1, a first memory 1, and a second memory.

第10頁 1314349Page 10 1314349

五、發明說明 1 4，以及域劃分僅法，在實不同的作以下，請施例。首個結構，分布於超實施例包皇號 92101177 (4) 通訊模組1 5數個作業區域。當為便於說明之用…丄；業、區 =業t，即使是通訊模組内也可能需要多數參看第2圖，此流程圖說明製作間隙壁方法 $，提供一基材（步驟202)，此基材上具有這些結構之側壁需要形成間隙壁，並且這些戶構過兩個以上的作業區域。舉例來說，這些$ ^的括閘極（gate)、溝渠（Trench)等類型。^ 接著，在此基材上形成至少二層以上之介電層（步輝 204)，這些介電層一層一層的堆疊在基材上方。這些介電層提供用來形成間隙壁的材料，而形成這些介電層的方法之例子包括各種半導體製程習知的沉積方式。在這些介電層中相鄰之二者具有不同之蝕刻選擇比，用以作為控制後續的選擇性蝕刻之條件》接著，依據最後要形成的間隙壁構造，選擇（步驟2〇6)微影蝕刻作業（步驟2 0 8 )或是直接對前述的介電層進行選擇性蝕刻（步驟2 1 0 )，此處所述的選擇性蝕刻可依需要選用乾式餘刻、澡式钱刻、等向触刻或非等向触刻，並利用前述介電層鄰接二層的蝕刻選擇比不同，以連成不同間隙壁寬度的需要。此種不利用光阻而利用蝕刻選擇比之不同介電層進行蝕刻者，又稱為自行對準蝕刻（self a 1 igned etching)β 其中，選擇微影蝕刻作業（步驟208)時包括下列步驟。首先，在前述的介電層上形成圖案化光陴（Patterned photoV. Description of invention 1 4, and the domain division method only, in the case of different implementations, please apply. The first structure is distributed in the super-implementation package. Emperor No. 92101177 (4) Communication module 1 5 several working areas. For ease of explanation... 丄; industry, district = industry t, even in the communication module may need most to refer to Figure 2, this flow chart illustrates the method of making spacers, providing a substrate (step 202), The side walls of these substrates having these structures need to form spacers, and these households pass through more than two working areas. For example, these $^ types include gates, trenches, and the like. Next, at least two or more dielectric layers (steps 204) are formed on the substrate, and the dielectric layers are stacked one above another on the substrate. These dielectric layers provide materials for forming the spacers, and examples of the method of forming these dielectric layers include conventional deposition methods of semiconductor processes. Adjacent ones of these dielectric layers have different etching selectivity ratios for use as conditions for controlling subsequent selective etching. Next, according to the final spacer structure to be formed, (step 2〇6) lithography is selected. Etching operation (step 208) or selective etching of the dielectric layer directly (step 2 1 0), the selective etching described herein may be selected as dry, engraved, bath, etc. To the touch or non-isotropic etch, and using the etch selectivity ratio of the dielectric layer adjacent to the two layers to form different gap widths. Such etching without etching using a different dielectric layer by etching is also referred to as self a 1 igned etching β. The selection of the lithography etching operation (step 208) includes the following steps. . First, a patterned aperture is formed on the aforementioned dielectric layer (Patterned photo)

第11頁 1314349 1 號 92101177 Λ.Ά Β 修正五、發明說明（5) 二esist) ’藉以曝露一部份的作業區域（步驟2〇82)。接著’對於曝露出來的作業區域部分，就介電層進行選擇性的蝕刻（步驟2084)，此選擇性蝕刻可依需要選用乾式蝕、濕式蝕刻、等向蝕刻或非等向蝕刻，並利用前述介電層鄰接二層的蝕刻選擇比不同，以達成不同間隙壁寬度的需要1然後:進行光阻的移除（步驟2086)。必須晶出的疋’整個餘刻程序必須包括至少一次之微影飿刻作業2 〇 8 ’至於選擇性蝕刻21 0則可依需要進行一次或多次’與微影钱刻作業208交錯進行。例如，可在形成至少 =介電^ 204後，即進行一次或多次選擇性蝕刻21〇，然後父錯進打至少—次微影蝕刻作業208及一次或多次選擇性蝕刻210’此類方法皆屬於本發明之範圍然的間隙壁皆形成完畢始結束（步驟21 4 )。其中’本發明的特徵至少包括下列幾點。首先需的介電層全部形成完畢。若欲形成N種不預先將所壁，則至少需要形成N層以上的介電層。其次間隙區域間隙壁形成的過程中，至少採取一次以上在作業作業。藉由在不同作業區域進行微影蝕刻作業時=蝕刻的選擇性蝕刻，使得不同作業區域的間隙壁具不同或層數的介電層，也因此達成在不同作業區^ ^形狀有不同的寬度。間隙壁具為了更清楚的說明本發明之概念，以下另外用子來說明本發明之方法。泮細的例首先，請參看第3圖（a)到第3圖（h)，這些圖說明如、何透過Page 11 1314349 No. 1 92101177 Λ.Ά 修正 Amendment 5. Invention Description (5) Two esist) </ br> to expose a part of the work area (steps 2〇82). Then, for the exposed working area portion, the dielectric layer is selectively etched (step 2084), and the selective etching may be performed by dry etching, wet etching, isotropic etching or non-isotropic etching, and utilized. The etching selectivity ratio of the dielectric layer adjacent to the two layers is different to achieve the need of different spacer widths 1 and then: removal of the photoresist is performed (step 2086). The 余整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个整个For example, one or more selective etchings 21 进行 may be performed after forming at least = dielectric 204, and then the parent may enter at least one lithography etching operation 208 and one or more selective etchings 210'. The methods are all within the scope of the present invention, and the formation of the spacers is completed (step 21 4). Wherein the features of the invention include at least the following points. First, all the required dielectric layers are formed. If it is desired to form N kinds of walls, it is necessary to form at least N layers of dielectric layers. In the process of forming the gap in the gap area, at least one more time is taken in the work. By performing the lithography etching operation in different working areas = selective etching of etching, the gap walls of different working areas have different or a plurality of layers of dielectric layers, thereby achieving different widths in different working areas. . Gap Walls In order to more clearly illustrate the concepts of the present invention, the methods of the present invention are further illustrated below. Fine example First, please refer to Figure 3 (a) to Figure 3 (h), which illustrate how and how

案號 92101177 1314349Case No. 92101177 1314349

五、發明說明（6) _____ 先形成介電層’再選擇性地透過微或形狀的間隙壁的例子。攻表蝕刻以達成不同寬度在第3圖（a)中，基材32上的第一作，，而在第二作業區域312具==2有= f ^隙壁，首先在基材32上沉積三層介電層“卜332、 „. 以具有不同蝕刻選擇比，且介電層332與介電層333具有不同的蝕刻選擇比。接在介電層331、332及333上方形成光阻341。然後如第3圖（b)所示，對光阻341所曝露出°之第一作業區域311進行等向或非等向餘刻，以移除介電層333。由於電層333與介電層332具有不同的蝕刻選擇比，因此可順移除介電層333。至於第一作業區域312因為有光阻341保護，因此不受到蝕刻的影響。保然後，對於第一作業區域311的介電層33 2繼續進行非等向姓刻之處理’就可以得到第3圖（c)所示的結構。此時將^ 二作業區域31 2之光阻341移除，並且對於第一作業區域 311藉由圖案化（pattern)程序加上光阻342，如此可得到第3圖（d)的結構。然後，對於光阻342所曝露出的第二作業區域3丨2進行二次非等向蝕刻可依序得到第3圖（e )及第3圖（f )的結構。接著，移除光阻342得到第3圖（g)的結構。並且在最後對所有作業區域進行一次非等向蝕刻，以移除所有非作為間隙壁的介電層的材料，而得到第3圖（h)的結構。在上述的程序後，我們得到第一作業區域311的閘極結構321具有與第二作業區域31 2的閘極結構322不同的間隙壁寬度。此^V. INSTRUCTION OF THE INVENTION (6) _____ An example in which a dielectric layer is formed first and then selectively passed through a micro or shaped spacer. The surface is etched to achieve different widths in the first pattern on the substrate 32 in Fig. 3(a), and in the second working area 312 ==2 has = f^gap, first on the substrate 32. Three dielectric layers are deposited "B, 332." to have different etch selectivity ratios, and dielectric layer 332 and dielectric layer 333 have different etch selectivity ratios. A photoresist 341 is formed over the dielectric layers 331, 332, and 333. Then, as shown in Fig. 3(b), the first working region 311 exposed by the photoresist 341 is subjected to an isotropic or non-isotropic engraving to remove the dielectric layer 333. Since the electrical layer 333 and the dielectric layer 332 have different etching selectivity ratios, the dielectric layer 333 can be removed. As for the first working area 312, since it is protected by the photoresist 341, it is not affected by the etching. Then, the dielectric layer 33 2 of the first work area 311 is continuously subjected to the process of non-isotropic processing, and the structure shown in Fig. 3(c) can be obtained. At this time, the photoresist 341 of the second working area 31 2 is removed, and the photoresist 342 is added to the first working area 311 by a patterning process, so that the structure of the third figure (d) can be obtained. Then, the second non-isotropic etching of the second working region 3丨2 exposed by the photoresist 342 can sequentially obtain the structures of FIGS. 3(e) and 3(f). Next, the photoresist 342 is removed to obtain the structure of Fig. 3(g). Finally, an anisotropic etch is performed on all the working regions at the end to remove all of the dielectric layers which are not the spacer walls, and the structure of Fig. 3(h) is obtained. After the above procedure, we obtain that the gate structure 321 of the first work area 311 has a different spacer width than the gate structure 322 of the second work area 31 2 . This ^

1314349 _案號92101177 _年月日修正 _ 五、發明說明（7) 隙壁寬度的不同係由其組成介電層之材料的層數與厚度來決定。必須指出的是，在整個間隙壁形成的過程中，由於到最後才統一進行非等向蝕刻，以移除不必要的介電層材料，因此基材3 2—直受到介電層3 3 1、3 3 2、3 3 3所保護，使閘極結構3 2 1、3 2 2下方的摻雜區不會受到多次蝕刻的污染。以上是利用三層介電層形成二種作業區域二種寬度形狀間隙壁之例子，當然，習知技藝者當能利用此說明將之拓展為各種二層以上之任何數目介電層，以形成二種以上之任何數目作業區域之二種以上任何寬度形狀之間隙壁。以下再說明如何形成三種寬度的間隙壁的另一例子。關於此例子，請醉合參看第4圖（a)到第4圖（i)的各階段結構圖。在第4圖（a)中，基材42具有第一作業區域411、第二作業區域412，以及第三作業區域413，在此三作業區威上分別有閘極結構421、422與423。首先，在基材42上形成四層介電層431、432、433、434，其中此四層介電唐 431、432、433、43 4之相鄰二層具有不同的蝕刻選擇比。然後，在此四層介電層431、432、433、434上方形成光$ 441，以曝露第一作業區域411，如第4圖（a)所示。接著，對於曝露之第一作業區域411進行兩次非等向蝕刻，以依序得到第4圖（b)、第4圖（c)所示結構。接著’存進行一次等向蝕刻，移除所曝露出之第一作業區域411的介電層434之物質以得到第4圖（d)所示結構。然後，將第二作業區域412、第三作業區域41 3之光阻441 去除，並接著在第一作業區域411上形成光阻442，以曝露1314349 _ Case No. 92101177 _ dd/mm/yyday Revision _ V. INSTRUCTIONS (7) The difference in the width of the gap is determined by the number of layers and the thickness of the material constituting the dielectric layer. It must be pointed out that in the process of forming the entire spacer, since the non-isotropic etching is uniformly performed to remove the unnecessary dielectric layer material, the substrate 32 is directly subjected to the dielectric layer 3 3 1 Protected by 3 3 2, 3 3 3, so that the doped regions under the gate structures 3 2 1 , 3 2 2 are not contaminated by multiple etchings. The above is an example of forming two width-shaped spacers in two working areas by using three dielectric layers. Of course, those skilled in the art can use this description to expand into any number of dielectric layers of two or more layers to form. Two or more spacers of any width shape of any number of two or more working areas. Another example of how to form spacers of three widths will be described below. For this example, please refer to the structural diagrams of each stage in Figures 4(a) to 4(i). In Fig. 4(a), the substrate 42 has a first working area 411, a second working area 412, and a third working area 413, in which the gate structures 421, 422 and 423 are respectively provided. First, four dielectric layers 431, 432, 433, 434 are formed on the substrate 42, wherein the adjacent two layers of the four dielectric layers 431, 432, 433, 43 4 have different etching selectivity ratios. Then, light $441 is formed over the four dielectric layers 431, 432, 433, 434 to expose the first working area 411 as shown in Fig. 4(a). Next, the non-isotropic etching is performed twice on the exposed first working region 411, and the structures shown in Figs. 4(b) and 4(c) are sequentially obtained. Next, an isotropic etching is performed to remove the substance of the dielectric layer 434 of the exposed first working region 411 to obtain the structure shown in Fig. 4(d). Then, the photoresist 441 of the second working area 412 and the third working area 41 3 is removed, and then a photoresist 442 is formed on the first working area 411 to expose

第14頁 1314349Page 14 1314349

曰五、發明說明（8) 第二作業區域4丨2 之第二作業區域彳及第三作業區域413。接著，對曝露出以移除該曝露區域2及第二作業區域41 3進行選擇性姓刻’ 後’我們得到^ ^ ;1電層434之物質。在經由這些步驟修」之第二作業區域41 2及第三作業區域以得到第4圖（f )所示的結構。然接著，進一步對(e)所示的結構 413進行非等向蝕刻後，去除第4圖第二作業區域4 ?中的光阻442,並在第一作業區域411 ,,Q ^ ^上形成光阻443，以曝露第三作業區域 413’並進行一笪&、 tf向或非等向餘刻’以得到第4圖（g)所示的結稱。接^ ’ 走*阻443 ’便得到第4圖（h)的結構。在第4圖 (h)的 '结構中’閘極結構42卜422與423分別覆蓋不同形狀的介電層H ’進行一次非等向蝕刻，把不需要的介電層物質移除’至此’便得到第4圖（i)。在第4圖（i)中，我們可以發現’閘極結構421、422、423具有不同形狀與寬度的間隙壁’因而可滿足閘極結構421、422與423所需要的不同寬度間隙壁特性。接著’請參看第5圖，此圖說明間隙不同的形狀。雖然上述的兩個例子中，皆以類似第5圖中間隙壁51的形狀作為說明之用，然而如果有設計的需要，習知技藝者當可利用上述之技術以形成間隙壁52的形狀》此外，請參看第6圖，此圖說明本發明適用於溝渠 (Trench)的例子。與前述的閘極不同，有時在溝渠形狀的結構也需要間隙壁’此時，我們便能利用本發明所接式的技術在不同作業區域形成不同寬度或形狀之間隙壁。曰 V. Invention Description (8) The second work area 彳 and the third work area 413 of the second work area 4丨2. Next, the material is removed by exposure to remove the exposed area 2 and the second working area 41 3 and then we obtain the material of the electrical layer 434. The second work area 41 2 and the third work area which have been repaired by these steps are used to obtain the structure shown in Fig. 4 (f). Then, after the anisotropic etching of the structure 413 shown in (e) is further performed, the photoresist 442 in the second working region 4? of FIG. 4 is removed and formed on the first working region 411, Q^^. The photoresist 443 is exposed to the third working area 413' and performs a 笪&, tf or non-isotropic reciprocation to obtain the symmetry shown in Fig. 4(g). The structure of Fig. 4 (h) is obtained by connecting ‘ walking* resistance 443’. In the 'structure' gate structure of FIG. 4(h), 422 and 423 respectively cover different shapes of the dielectric layer H' for an anisotropic etching to remove the unnecessary dielectric layer material 'to this' Figure 4 (i) is obtained. In Fig. 4(i), we can find that the gate structures 421, 422, and 423 have spacers of different shapes and widths, thereby satisfying the different width spacer characteristics required for the gate structures 421, 422, and 423. Next, please refer to Figure 5, which illustrates the different shapes of the gap. Although the above two examples are similar to the shape of the spacer 51 in Fig. 5, if there is a need for design, the above-mentioned technique can be utilized to form the shape of the spacer 52. In addition, please refer to Fig. 6, which illustrates an example in which the present invention is applicable to a trench. Unlike the aforementioned gates, sometimes the structure of the trench shape also requires spacers. At this point, we can use the technique of the present invention to form spacers of different widths or shapes in different work areas.

第15頁 1314349 - -案號咖 ”77___主 ^^~ - 五、發明說明（9) 此外’除了上述兩種在閘極以及溝渠的應用’其他需要間隙壁的結構亦可適用本發明之技術。舉例來說’在平坦化製程後需要產生導線或溝渠等需要間隙壁的結構’亦可適用本發明之技術，以在不同作業區域形成不同寬度或形狀的間隙壁。由上述本發明較佳實施例讦知’應用本發明至少具有下列優點。首先，由於在間隙壁製作的過程中’基材受到介電層的保護，因此可避免因為製程，例如蝕刻，所帶來的污染β舉例來說，本方法可避免對於不同作業區域的閘極下方之換雜區產生污染。其次，本發明將作為間隙壁材質的介電層一次先全部沉積形成出來，接著再透過選擇性的微影餘刻，以不同介電層形狀的組合以得到不同的間隙壁形狀，此對電路之設計者而言具有容易規劃的特性，也因此本發明對於日益複雜的電路’亦有重要的之效用。因此，本發明確實提供了一個有效的方法，以在不同作業區域形成不同寬度或形狀的間隙壁，於是本發明對於今後半導體製程需要用到更複雜的電路積集，難謂不具有重要的貢獻。雖然本發明已以一較佳實施例揭露如上，然其並非用以限定本發明’任何熟習此技藝者，在不脫離本發明之精神和範圍内’當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。Page 15 1314349 - - Case No. "77___ 主^^~ - V. Description of the invention (9) In addition to 'the above two applications in the gate and the ditch', other structures requiring a spacer may also be applied to the present invention. Techniques, for example, 'the need to create a structure requiring a spacer after a flattening process, such as wires or trenches' can also be applied to the technique of the present invention to form spacers of different widths or shapes in different work areas. The present invention knows that the application of the present invention has at least the following advantages. First, since the substrate is protected by the dielectric layer during the fabrication of the spacer, it is possible to avoid the contamination β caused by the process, such as etching. In this way, the method can avoid contamination of the replacement region under the gate of different working areas. Secondly, the present invention deposits the dielectric layer as the spacer material all at once, and then transmits selective lithography. In the case of a combination of different dielectric layer shapes to obtain different spacer shapes, this is easy for the designer of the circuit to plan, and therefore The present invention also has important utility for increasingly complex circuits. Accordingly, the present invention does provide an effective method for forming spacers of different widths or shapes in different work areas, and thus the present invention is required for future semiconductor processes. It is difficult to say that there is no significant contribution to the more complicated circuit accumulation. Although the present invention has been disclosed above in a preferred embodiment, it is not intended to limit the invention to anyone skilled in the art without departing from the invention. The spirit and scope of the invention may be varied and modified, and the scope of the invention is defined by the scope of the appended claims.

第16頁 1314349 案號 92101177 曰修正圖式簡單說明圖式簡單說明第1圖例示一積體電路晶片的示意圖；第2圖例示實施例方法之流程圖；第3圖（a)到（h)例示形成二種寬度間隙壁之例子第4圖（a)到（i )例示形成三種寬度間隙壁之例子第5圖例示不同間隙壁形狀之例子；以及第6圖例示另一結構間隙壁應用之例子。圖式之標記說明 1 0晶片 1 2控制模組 1 4第二記憶體 202〜214流程圖步驟 3 11第一作業區域 3 2基材 3 2 1閘極結構 3 3 1介電層 3 3 3介電層 342光阻 4 1 2第二作業區域 4 2 1閘極結構 423閘極結構 11計算模組 1 3第一記憶體 1 5通訊模組 2082〜2086流程圖步驟 312第二作業區域 42基材 3 2 2閘極結構 3 3 2介電層 341光阻 411第一作業區域 413第三作業區域 422閘極結構 43 1介電層Page 16 1314349 Case No. 92101177 曰Revision Diagram Simple Description of the Drawings FIG. 1 illustrates a schematic diagram of an integrated circuit wafer; FIG. 2 illustrates a flow chart of the embodiment method; FIG. 3 (a) to (h) Examples of forming two types of width spacers are shown in Figs. 4(a) to (i) for exemplifying the example of forming three kinds of width spacers. Fig. 5 illustrates an example of different gap wall shapes; and Fig. 6 illustrates another structure spacer application. example. Description of the drawings: 10 chip 1 2 control module 1 4 second memory 202 to 214 flow chart step 3 11 first working area 3 2 substrate 3 2 1 gate structure 3 3 1 dielectric layer 3 3 3 Dielectric layer 342 photoresist 4 1 2 second working area 4 2 1 gate structure 423 gate structure 11 computing module 1 3 first memory 1 5 communication module 2082~2086 flow chart step 312 second working area 42 Substrate 3 2 2 gate structure 3 3 2 dielectric layer 341 photoresist 411 first working region 413 third working region 422 gate structure 43 1 dielectric layer

1314349 案號 92101177 年月曰修正圖式簡單說明 432介電層 434介電層 442光阻 5 1間隙壁 4 3 3介電層 441光阻 443光阻 5 2間隙壁1314349 Case No. 92101177 Issued Correction Schematic description 432 dielectric layer 434 dielectric layer 442 photoresist 5 1 spacer 4 3 3 dielectric layer 441 photoresist 443 photoresist 5 2 spacer

1HH 第18頁1HH第18页

Claims

1314349 _案號92101177_年月日修正_ 六、申請專利範圍 1. 一種形成多種寬度之間隙壁的方法，該方法至少包含：形成一第一介電層於複數結構上，其中該些結構分布於一基材上之至少一第一作業區域與一第二作業區域；形成一第二介電層於該複數結構上，該第二介電層之材質與該第一介電層之材質不同；形成一第一光阻於該第二作業區域上；選擇性地蝕刻位於該第一作業區域上之該第二介電層，以完全移除暴露出之該第二介電層；非等向蝕刻暴露出之該第一介電層，以於該第一作業區域内之複數結構之側壁上形成第一間隙壁；移除該第一光阻；形成一第二光阻於該第一作業區域上；以及依序蝕刻該第二作業區域之該第二介電層與該第一介電層，以於該第二作業區域内之複數結構側壁上形成第二間隙壁，藉此該些第二間隙壁之寬度大於該些第一間隙壁之寬度。 2. 如申請專利範圍第1項所述之方法，其中在形成該第一光阻與該第二光阻的步驟之間，更至少包含一半導體製程。 3. 如申請專利範圍第1項所述之方法，其中該些結構包含閘極結構。1314349 _ Case No. 92101177_年月日日 Revision _ VI. Patent Application Range 1. A method for forming a plurality of width spacers, the method comprising: forming a first dielectric layer on a plurality of structures, wherein the structures are distributed And forming at least a first working area and a second working area on a substrate; forming a second dielectric layer on the plurality of structures, the material of the second dielectric layer is different from the material of the first dielectric layer Forming a first photoresist on the second working region; selectively etching the second dielectric layer on the first working region to completely remove the exposed second dielectric layer; Forming the first dielectric layer on the sidewall of the plurality of structures in the first working region to form a first spacer; removing the first photoresist; forming a second photoresist on the first And etching the second dielectric layer and the first dielectric layer in the second working area to form a second spacer on the sidewall of the plurality of structures in the second working area, thereby The width of the second spacers is large The width of the plurality of first spacers. 2. The method of claim 1, wherein at least one semiconductor process is included between the step of forming the first photoresist and the second photoresist. 3. The method of claim 1, wherein the structures comprise a gate structure.

第19頁 1314349 _案號92101177_年月日_修正 _ 六、申請專利範圍 4. 如申請專利範圍第1項所述之方法，其中該些結構結構包含溝渠結構。 5. 如申請專利範圍第1項所述之方法，其中該些第一間隙壁與該些第二間隙壁之組成之介電層數目不同，使得該些第一間隙壁與該些第二間隙壁之寬度不同。 6. —種形成多種寬度之間隙壁的方法，該方法至少包含：形成一第一介電層於複數結構上，其中該些結構分布於一基材上之至少第一作業區域與至少第二作業區域；形成一第二介電層於該複數結構上，該第二介電層之材質與該第一介電層之材質不同；形成一第三介電層於該複數結構上，該第三介電層之材質與該第二介電層之材質不同；形成一第一光阻於一第二作業區域上；選擇性地蝕刻位於該第一作業區域之第三介電層，以完全移除暴露之該第三介電層；非等向蝕刻暴露出之該第二介電層，以於該第一作業區域内之該些結構上之該第一介電層之侧壁上形成第一間隙壁；移除該第一光阻；形成一第二光阻於該第一作業區域上；Page 19 1314349 _ Case No. 92101177 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 5. The method of claim 1, wherein the first spacers and the second spacers are different in number of dielectric layers, such that the first spacers and the second gaps The width of the wall is different. 6. A method of forming a plurality of width spacers, the method comprising: forming a first dielectric layer on a plurality of structures, wherein the structures are distributed on at least a first work area and at least a second on a substrate a working region; forming a second dielectric layer on the plurality of structures, the material of the second dielectric layer is different from the material of the first dielectric layer; forming a third dielectric layer on the plurality of structures, the first The material of the three dielectric layers is different from the material of the second dielectric layer; forming a first photoresist on a second working region; selectively etching the third dielectric layer in the first working region to completely Removing the exposed third dielectric layer; the second dielectric layer exposed by the non-isotropic etching is formed on the sidewalls of the first dielectric layer on the structures in the first working region a first spacer; removing the first photoresist; forming a second photoresist on the first working area;

第20頁 1314349 _案號92101177_年月日__ 六、申請專利範圍依序蝕刻該第二作業區域之該第三介電層與該第二介電層，以於該第二作業區域内之複數結構侧壁上形成第二間隙壁；移除該第二光阻；以及蝕刻暴露出之該第一介電層，以同時在該第一作業區域之該些結構上之該第一介電層之側壁上與該些第一間隙壁一起形成第三間隙壁，以及在該第二作業區域之該些結構之側壁上與該些第二間隙壁一起形成第四間隙壁，藉此該些第四間隙壁之寬度大於該些第三間隙壁之寬度。 7. 如申請專利範圍第6項所述之方法，其中在形成該第一光阻與該第二光阻的步驟之間，更至少包含一半導體製程。 8. 如申請專利範圍第6項所述之方法，其中該些結構包含閘極結構。 9. 如申請專利範圍第6項所述之方法，其十該些結構包含溝渠結構。 1 0. —種半導體結構，包含：一基材，該基材包含一第一作業區域以及一第二作業區域；複數個電路結構，位於該第一作業區域以及該第二作業區Page 20 1314349 _ Case No. 92101177_年月日日__ Sixth, the patent application scope sequentially etches the third dielectric layer and the second dielectric layer of the second working area, in the second working area Forming a second spacer on the sidewall of the plurality of structures; removing the second photoresist; and etching the exposed first dielectric layer to simultaneously serve the first dielectric on the structures of the first operating region Forming a third spacer on the sidewall of the electrical layer together with the first spacers, and forming a fourth spacer along with the second spacers on sidewalls of the structures of the second working region, thereby The width of the fourth spacers is greater than the width of the third spacers. 7. The method of claim 6, wherein at least one semiconductor process is included between the step of forming the first photoresist and the second photoresist. 8. The method of claim 6, wherein the structures comprise a gate structure. 9. The method of claim 6, wherein the structures comprise a trench structure. A semiconductor structure comprising: a substrate comprising a first work area and a second work area; a plurality of circuit structures located in the first work area and the second work area

第21頁 1314349 _案號92101177_年月曰修正_ 六、申請專利範圍域；一第一介電層，位於該第一作業區域以及該第二作業區域之該些電路結構之側壁；一第二介電層，位於該第二作業區域之該些電路結構之側壁，其中，該第二介電層之材質與該第一介電層之材質不同，該第一作業區域之一第一間隙壁包含該第一介電層，該第二作業區域之一第二間隙壁包含該第一介電層以及該第二介電層，藉以該第二間隙壁之寬度大於該第一間隙壁之寬度。 11.如申請專利範圍第10項所述之半導體結構，更包含一第三介電層，位於該第一作業區域以及該第二作業區域之該些電路結構之側壁，其中，該第一作業區域之該第一間隙壁包含該第一介電層以及該第三介電層，該第二作業區域之該第二間隙壁則包含該第一介電層、該第二介電層以及該第三介電層，藉以使該第二間隙壁之寬度大於該第一間隙壁之寬度。 1 2.如申請專利範圍第1 0項所述之半導體結構，更包含一第三介電層，位於該第二作業區域之該些電路結構之側壁，其中，該第一作業區域之該第一間隙壁包含該第一介電層，該第二作業區域之該第二間隙壁則包含該第一介電層、該第二介電層以及該第三介電層，藉以使該第二間隙Page 21 1314349 _ case number 92101177_Yearly revision _ six, the patent application scope field; a first dielectric layer, located in the first working area and the second working area of the circuit structure side wall; The second dielectric layer is located on the sidewall of the circuit structure of the second working area, wherein the material of the second dielectric layer is different from the material of the first dielectric layer, and the first gap of the first working area is The wall includes the first dielectric layer, and the second spacer of the second working area includes the first dielectric layer and the second dielectric layer, wherein the second spacer has a width greater than the first spacer width. 11. The semiconductor structure of claim 10, further comprising a third dielectric layer located on sidewalls of the circuit structures of the first work area and the second work area, wherein the first operation The first spacer of the region includes the first dielectric layer and the third dielectric layer, and the second spacer of the second working region includes the first dielectric layer, the second dielectric layer, and the The third dielectric layer is such that the width of the second spacer is greater than the width of the first spacer. 1 2. The semiconductor structure of claim 10, further comprising a third dielectric layer on a sidewall of the circuit structures in the second operating region, wherein the first operating region a spacer includes the first dielectric layer, and the second spacer of the second working region includes the first dielectric layer, the second dielectric layer, and the third dielectric layer, thereby enabling the second gap

第22頁 1314349 _案號92101177_年月曰修正_ 六、申請專利範圍壁之寬度大於該第一間隙壁之寬度。 1 3 .如申請專利範圍第1 1或第1 2項所述之半導體結構，其中該第三介電層之材質與該第二介電層之材質不同。 1 4.如申請專利範圍第1 0項所述之半導體結構，其中該些電路結構包含閘極結構。 1 5 .如申請專利範圍第1 0項所述之半導體結構，其中該些電路結構包含溝渠結構。Page 22 1314349 _ Case No. 92101177_年月曰修正 Amendment _ VI. Patent Application Scope The width of the wall is greater than the width of the first spacer. The semiconductor structure of claim 1 or claim 2, wherein the material of the third dielectric layer is different from the material of the second dielectric layer. 1 4. The semiconductor structure of claim 10, wherein the circuit structures comprise a gate structure. The semiconductor structure of claim 10, wherein the circuit structure comprises a trench structure.

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