TWI600123B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

Info

Publication number
TWI600123B
TWI600123B TW103112076A TW103112076A TWI600123B TW I600123 B TWI600123 B TW I600123B TW 103112076 A TW103112076 A TW 103112076A TW 103112076 A TW103112076 A TW 103112076A TW I600123 B TWI600123 B TW I600123B
Authority
TW
Taiwan
Prior art keywords
layer
resin layer
wiring
bonding wires
semiconductor wafer
Prior art date
Application number
TW103112076A
Other languages
English (en)
Other versions
TW201507073A (zh
Inventor
杉山道昭
紺野順平
Original Assignee
瑞薩電子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 瑞薩電子股份有限公司 filed Critical 瑞薩電子股份有限公司
Publication of TW201507073A publication Critical patent/TW201507073A/zh
Application granted granted Critical
Publication of TWI600123B publication Critical patent/TWI600123B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/036—Multilayers with layers of different types
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • H05K3/326—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor the printed circuit having integral resilient or deformable parts, e.g. tabs or parts of flexible circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H01L2224/11472—Profile of the lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H01L2224/17051—Bump connectors having different shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/2732—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2733—Manufacturing methods by local deposition of the material of the layer connector in solid form
    • H01L2224/27334—Manufacturing methods by local deposition of the material of the layer connector in solid form using preformed layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48111—Disposition the wire connector extending above another semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73257—Bump and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3512—Cracking
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0187—Dielectric layers with regions of different dielectrics in the same layer, e.g. in a printed capacitor for locally changing the dielectric properties
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0191—Dielectric layers wherein the thickness of the dielectric plays an important role
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Metallurgy (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

半導體裝置及其製造方法
本發明是有關半導體裝置及其製造技術，例如有關適用在藉由覆晶安裝技術來將半導體晶片安裝於配線基板上的半導體裝置之有效的技術。
在日本特開2004-165311號公報(專利文獻1)中記載半導體晶片經由金屬杆來連接至基板的晶片搭載面的焊墊之構造。
並且，在日本特開2007-329396號公報(專利文獻2)中記載半導體基板經由金屬柱及配置於其前端的突起電極來安裝於安裝基板的構造。
並且，在日本特開2009-289908號公報(專利文獻3)中記載半導體晶片的焊墊與配線基板的接合導線(bonding lead)的電性連接是藉由形成於接合導線上的焊錫與由金所構成的凸塊電極之金-焊錫接合來進行之構造。
[先行技術文獻] [專利文獻]
[專利文獻1]日本特開2004-165311號公報
[專利文獻2]日本特開2007-329396號公報
[專利文獻3]日本特開2009-289908號公報(圖38，圖39)
就覆晶安裝技術而言，例如有像上述專利文獻1，2那樣，經由柱(杆(post)，支柱(pillar))狀的導電性構件來將半導體晶片安裝於配線基板上者，及像上述專利文獻3那樣，經由突起(凸塊)狀的導電性構件來將半導體晶片安裝於配線基板上者。並且，就覆晶安裝技術而言，在安裝半導體晶片時，對於配置在配線基板上的半導體晶片，施加垂直方向(配線基板的厚度方向)的荷重。
在此，為了電性連接形成於配線基板的晶片搭載面之複數的電極(連接接合導線，導電性構件的電極)，半導體晶片及配線基板，而使用之由柱(杆)狀或突起(凸塊)狀所形成的複數的導電性構件，或上述複數的電極及上述複數的導電性構件是產生偏差。
換言之，各電極的各表面(連接導電性構件的面)的高度或各導電性構件的高度(大小)，因加工偏差的影響，不一定成為同高度(面一致)。因此，在將半導體晶片配置於配線基板上時，有時存在不與配線基板的電極接觸 的導電性構件。
此時，支撐配線基板的上述電極的絕緣層(在此是電極接觸的絕緣層)不是聚酯膠片(含玻璃布(glass cloth)的樹脂層)，換言之，以不含玻璃布(亦稱玻璃纖維)的樹脂層所構成時，其硬度(或，剛性，強度)是比聚酯膠片更低。
因此，如圖25所示般，一旦對於半導體晶片50施加荷重，則導電性構件的凸塊52所接觸的配線基板60的接合導線64會沈入。換言之，一旦對不含玻璃布的樹脂層61施加荷重，則此樹脂層61會變形。
藉此，即使各凸塊52或各接合導線64的高度產生偏差，還是可藉由接合導線64沈入來吸收上述偏差，因此可抑制凸塊52與接合導線64的接合不良。
另一方面，如上述般，不含玻璃布的樹脂層61相較於圖26所示含玻璃布65的樹脂層66(聚酯膠片)，其硬度低。因此，不使用聚酯膠片作為支撐含接合導線64的配線層之樹脂層的半導體裝置是在半導體裝置的薄型化的點不利。
然而，如圖26所示般，採用樹脂層(聚酯膠片)作為支撐接合導線64等的電極之絕緣層時，即使對此樹脂層66施加荷重，也會像不含玻璃布的樹脂層61那樣難變形。因此，形成於此樹脂層66上的接合導線64不沈入。換言之，絕緣層的樹脂層66難變形，因此難以對應於各凸塊或各接合導線的高度偏差。
在本案中所揭示的實施形態的目的是在於提供一種可使半導體裝置的可靠度提升之技術。
其他的課題及新穎的特徴是可由本說明書的記述及附圖明確得知。
一實施形態的半導體裝置係包含：配線基板，其係具有第1絕緣層，複數的接合導線，及複數的接端面；及半導體晶片，其係以主面能夠與配線基板對向的方式經由複數的導電性構件來搭載於配線基板上，上述複數的導電性構件係經由複數的焊錫材來與配線基板的複數的接合導線分別連接。
而且，上述半導體裝置係上述第1絕緣層為以具有玻璃纖維的第1樹脂層及不具有玻璃纖維的第2樹脂層所構成，上述複數的接合導線係分別與上述第2樹脂層接觸。
若根據上述一實施形態，則可使半導體裝置的可靠度提升。
1‧‧‧半導體晶片
1a‧‧‧主面(元件形成面)
1b‧‧‧背面
1c‧‧‧焊墊(電極)
1d，1e‧‧‧邊
2‧‧‧配線基板
2a‧‧‧上面(晶片搭載面)
2b‧‧‧下面
2c‧‧‧抗焊劑膜(上面側保護膜)
2ca‧‧‧內側抗焊劑膜(內側絕緣膜)
2d‧‧‧絕緣層(絕緣膜)
2da‧‧‧聚酯膠片(樹脂層)
2db‧‧‧樹脂層(樹脂材)
2e‧‧‧核心層(聚酯膠片)
2f‧‧‧絕緣層(絕緣膜)
2fa‧‧‧聚酯膠片(樹脂層)
2fb‧‧‧樹脂層
2g‧‧‧抗焊劑膜(下面側保護膜)
2h‧‧‧玻璃布(玻璃纖維)
2i，2j‧‧‧配線層
2k‧‧‧開口部
2m‧‧‧接合導線(電極)
2ma‧‧‧外周導線群
2mb‧‧‧內周導線群
2mba，2mbb，2mbc‧‧‧接合導線(電極)
2n‧‧‧接端面(電極)
2p，2q‧‧‧配線層
2r‧‧‧切斷部
2s‧‧‧框部
2t‧‧‧多數個取出基板(矩陣基板)
2u‧‧‧裝置領域
2v‧‧‧接合導線(電極)
2w‧‧‧樹脂層
3‧‧‧焊錫材(連接構件)
4‧‧‧銅支柱(導電性構件，杆)
5‧‧‧焊錫球(導電性構件)
6‧‧‧底部填充膠(密封材)
7‧‧‧BGA(半導體裝置)
8‧‧‧半導體晶片
8a‧‧‧主面(元件形成面)
8b‧‧‧背面
8c‧‧‧焊墊(電極)
9‧‧‧黏晶材
10‧‧‧接線(導電性構件)
11‧‧‧密封體
12‧‧‧BGA(半導體裝置)
50‧‧‧半導體晶片
52‧‧‧凸塊(突起)
60‧‧‧配線基板
61‧‧‧樹脂層
64‧‧‧接合導線(電極)
65‧‧‧玻璃布(玻璃纖維)
66‧‧‧樹脂層
67‧‧‧龜裂
圖1是表示實施形態的半導體裝置的構造的一例平面 圖。
圖2是表示沿著圖1所示的A-A線來切斷後的構造的一例剖面圖。
圖3是表示圖1所示的半導體裝置的背面側的構造的一例背面圖。
圖4是表示被裝入至圖1所示的半導體裝置之配線基板的上面側的構造的一例平面圖。
圖5是表示沿著圖4所示的A-A線來切斷後的構造的一例剖面圖。
圖6是表示圖5所示的B部的構造的一例擴大部分剖面圖。
圖7是表示圖4所示的配線基板的下面側的構造的一例背面圖。
圖8是表示搭載於圖1所示的半導體裝置之半導體晶片的主面側的構造的一例平面圖。
圖9是表示沿著圖8所示的A-A線來切斷後的構造的一例剖面圖。
圖10是表示搭載於圖1所示的半導體裝置之半導體晶片的背面側的構造的一例背面圖。
圖11是表示沿著圖10的A-A線來切斷後的構造的一例剖面圖。
圖12是表示使用在圖1所示的半導體裝置的組裝之配線基板的構造的一例平面圖。
圖13是表示沿著圖12的A-A線來切斷後的構造的 一例剖面圖。
圖14是表示圖12所示的配線基板的1個裝置領域的構造的一例剖面圖。
圖15是表示圖1所示半導體裝置的組裝之焊錫預塗層後的構造的一例剖面圖。
圖16是表示圖1所示的半導體裝置的組裝之底部填充膠塗布後的構造的一例平面圖。
圖17是表示沿著圖16的A-A線來切斷後的構造的一例剖面圖。
圖18是表示圖1所示的半導體裝置的組裝的覆晶安裝工程之晶片搭載後的構造的一例剖面圖。
圖19是表示圖18所示的覆晶安裝工程之晶片壓著後的構造的一例剖面圖。
圖20是表示圖1所示的半導體裝置的組裝之球型安裝後的構造的一例剖面圖。
圖21是表示被裝入至實施形態的變形例1的半導體裝置之配線基板的上面側的導線配列的一例平面圖。
圖22是表示實施形態的變形例2的半導體裝置的構造的一例剖面圖。
圖23是表示被裝入至實施形態的變形例4的半導體裝置的配線基板的構造的一例剖面圖。
圖24是表示實施形態的變形例5的配線基板的一例擴大部分剖面圖。
圖25是表示本案發明者所進行檢討的覆晶安裝之荷 重施加時的第1構造的擴大部分剖面圖。
圖26是表示本案發明者所進行檢討的覆晶安裝之荷重施加時的第2構造的擴大部分剖面圖。
在以下的實施形態中除了特別必要時以外，原則上是不重複同一或同樣的部分的說明。
而且，在以下的實施形態中基於方便起見有其必要時，分割成複數的部分或實施形態來進行說明，但除特別明示的情況，該等不是彼此無關者，一方是處於另一方的一部分或全部的變形例，詳細，補充說明等的關係。
並且，在以下的實施形態中，言及要素的數目等(包含個數，數值，量，範圍等)時，除了特別明示時及原理上明確限於特定的數目時等以外，並不限定於其特定的數目，亦可為特定的數目以上或以下。
而且，在以下的實施形態中，其構成要素(亦包含要素步驟等)除了特別明示時及原理上明確為必須時等以外，當然不一定是必須者。
並且，在以下的實施形態中，有關構成要素等，稱「由A所形成」，「自A形成」，「具有A」，「包含A」時，除了特別明示僅該要素的情況等，當然不是排除除此以外的要素者。同樣，在以下的實施形態中，言及構成要素等的形狀，位置關係等時，除了特別明示時 及原理上明顯非如此時等以外，包含實質近似或類似其形狀等者。這是有關上述數值及範圍也同樣。
以下，根據圖面來詳細說明本發明的實施形態。另外，在用以說明實施形態的全圖中，對於具有同一機能的構件附上同一符號，其重複的說明是省略。並且，為了容易理解圖面，即使是平面圖也有時附上剖面線。
(實施形態) <半導體裝置>
圖1是表示實施形態的半導體裝置的構造的一例平面圖，圖2是表示沿著圖1所示的A-A線來切斷後的構造的一例剖面圖，圖3是表示圖1所示的半導體裝置的背面側的構造的一例背面圖。
說明有關圖1~圖3所示的本實施形態的半導體裝置的構成。如圖2所示般，本實施形態的半導體裝置是具有配線基板2。而且是半導體晶片1會被覆晶安裝於此配線基板2上的構造者。亦即，半導體晶片1是以其主面1a能夠與配線基板2的上面(晶片搭載面)2a對向的方式，經由複數的導電性構件來搭載於配線基板2的上面2a上。
另一方面，在配線基板2的下面2b是設有成為半導體裝置的外部端子的複數的焊錫球5。另外，在本實施形態中，複數的焊錫球5是如圖3所示般，平面視配列成格子狀。
因此，在本實施形態中，舉BGA(Ball Grid Array)7作為上述半導體裝置的一例進行說明。
在本實施形態的BGA7中，設在半導體晶片1的主面(元件形成面)1a之複數的焊墊(電極)1c，及設在配線基板2的上面2a之複數的接合導線(電極)2m是分別經由導電性構件及焊錫材(連接構件)3來電性連接。
另外，在本實施形態的BGA7中，導電性構件是形成於半導體晶片1的焊墊1c。並且，說明在本實施形態的BGA7中，使用銅(Cu)支柱4作為上述導電性構件的情況。銅支柱4是由以銅作為主成分的材料所構成，且為柱(杆)狀的電極。因此，半導體晶片1經由分別形成於其主面1a的複數的焊墊1c的表面之複數的銅支柱4來覆晶連接至配線基板2。此時，複數的銅支柱4是經由分別配置於其各前端面(與接合導線2m對向的面)之複數的焊錫材3來分別與配線基板2的複數的接合導線2m電性連接。
在此，最好焊錫材3是實質上不含鉛(Pb)採用所謂無鉛焊錫，例如錫-銀(Sn-Ag)等。
藉此，亦可對應於環境污染問題。另外，所謂無鉛焊錫是意思鉛(Pb)的含量為0.1wt%以下，此含量是定為RoHS(Restriction of Hazardous Substances)指令的基準。
並且，BGA7是在配線基板2的上面2a側，如圖2所示般，在形成於半導體晶片1與配線基板2之間 的間隙中充填有密封樹脂的底部填充膠(Underfill)6。此底部填充膠6是例如環氧系樹脂，為了確保半導體晶片1與配線基板2的連接可靠度而被充填。
而且，底部填充膠6是連半導體晶片1的側面也覆蓋。藉此，可保護覆晶連接部(銅支柱4與接合導線2m的連接部)。並且，亦可抑制水分從半導體晶片1的外部(周邊)進入至上述覆晶連接部。但，半導體晶片1的背面1b是如圖1及圖2所示般，在朝BGA7的上方之狀態下露出。
並且，配線基板2是如圖2所示般，為具有複數的配線層之多層配線基板。亦即，在核心層2e的表背面形成有配線層2i及配線層2j，而且在圖5所示的最上層的配線層2p形成有覆晶連接用的複數的接合導線2m。另一方面，在最下層的配線層2q是形成有用以連接BGA7的外部端子的焊錫球(導電性構件)5之複數的接端面(land)(電極)2n。
亦即，在配線基板2的上面2a及下面2b的各個表面形成有絕緣膜的抗焊劑膜2c，2g，在上面2a側，複數的接合導線2m會被配置於抗焊劑膜2c的開口部2k，另一方面，在下面2b側，接端面2n會分別配置於抗焊劑膜2g的複數的開口部2k。
並且，本實施形態的配線基板2是在上面2a側，複數的接合導線2m配置於絕緣層2d上。此絕緣層2d是以具有玻璃布(玻璃纖維)2h的聚酯膠片(樹脂層)2da 及不具玻璃布2h的樹脂層2db所構成。詳細是樹脂層2db形成(層疊)於聚酯膠片2da上(半導體晶片1側的面)。
因此，複數的接合導線2m是分別接觸於樹脂層2db，配置在此樹脂層2db上。而且，各接合導線2m是分別經由焊錫材3來連接至銅支柱4，因此樹脂層2db是位於聚酯膠片2da與各銅支柱4之間。
另外，就具有玻璃布2h的聚酯膠片2da及不具有玻璃布2h的樹脂層2db而言，聚酯膠片2da是硬度較大(高)，剛性也大。亦即，具有玻璃布2h的聚酯膠片2da硬，不具有玻璃布2h的樹脂層2db柔軟。
然後，複數的接合導線2m是分別不經由含玻璃布(玻璃纖維)2h的聚酯膠片2da來直接與柔軟的樹脂層2db(不含玻璃布的層)接觸。
就如此BGA7而言，在其配線基板2中，經由柔軟的樹脂層2db，在聚酯膠片2da上設有複數的接合導線2m，因此在覆晶連接等被賦予荷重時，樹脂層2db會變形，接合導線2m會沈入。藉此，即使在銅支柱4的高度產生偏差，全部的銅支柱4還是可與接合導線2m連接。亦即，即使為高度低的銅支柱4，還是可與接合導線2m連接。
並且，如上述般，由於與複數的銅支柱4之中，高度比其他的銅支柱4更高的銅支柱連接的配線基板2的接合導線2m會沈入，因此可抑制在形成有此高度高的銅支柱4之半導體晶片1的焊墊1c正下面的絕緣層形 成龜裂67(參照圖26)。藉此，可使BGA7的可靠度提升。
而且，即使應力作用於BGA7的焊錫球5等時，還是可藉由柔軟的樹脂層2db來使應力緩和，可抑制損傷直接傳至覆晶連接部。
亦即，在連接銅支柱4的接合導線2m的下部配置有柔軟的樹脂層2db，因此即使包含熱應力等的應力作用於焊錫球5時，還是可藉由柔軟的樹脂層2db的變形來緩和上述應力而以損傷不會直接傳至覆晶連接部或半導體晶片1的方式吸收上述應力。
其結果，可抑制覆晶連接部的連接不良的發生。
<配線基板>
圖4是表示被裝入至圖1所示的半導體裝置之配線基板的上面側的構造的一例平面圖，圖5是表示沿著圖4所示的A-A線來切斷後的構造的一例剖面圖，圖6是表示圖5所示的B部的構造的一例擴大部分剖面圖，圖7是表示圖4所示的配線基板的下面側的構造的一例背面圖。
說明有關本實施形態的配線基板2的詳細的構造。
配線基板2是如上述般為多層配線基板，在本實施形態中，舉具有4個配線層的多層配線基板作為一例進行說明，但配線層的數量並非限於4層。
配線基板2是具有：圖4所示的平面形狀為四角形所形成的上面2a，及與此上面2a相反側的安裝面或背面之圖7所示的下面2b。
如圖4所示般，在配線基板2的上面2a，形成於最上層的配線層的覆晶連接用的複數的接合導線2m會在圖5所示的抗焊劑膜2c的開口部2k，以內側列及外側列2列排列配置。另外，以內側列及外側列彼此錯開配置，成為配合晶片側的交錯配列的焊墊配置來對應於多針腳化的配置。
並且，在配置有各接合導線2m的抗焊劑膜2c的開口部2k，支撐各接合導線2m的樹脂層2db也會露出。
另一方面，如圖7所示般，在配線基板2的下面2b，形成於最下層的配線層的焊錫球連接用的複數的接端面2n會分別被配置於圖5所示的抗焊劑膜2g的複數的開口部2k，該等複數的接端面2n是配置成格子狀。
並且，如圖5及圖6所示般，配線基板2是藉由貼合核心層(聚酯膠片)2e，及配置於核心層2e的上下面的配線層2i，2j，及絕緣層(絕緣膜)2d，2f，及最上層與最下層各個的配線層2p，2q來形成者。另外，各構件的貼合是藉由沖壓加工的壓接來進行。例如，以平板狀的鋼板等來夾著核心層2e，配線層2i，2j，絕緣層2d，2f及配線層2p，2q等的各構件，而以高溫.高壓來進行沖壓加工。
因此，依裝置領域2u(參照圖12)的位置，特別是形成於最上層或最下層等的最表層的配線(包含接合導線2m或接端面2n等的電極)的高度產生偏差。
本實施形態的配線基板2的情況，如圖6所示般為具有4層的配線層的構造，在核心層2e的表背面形成有配線層2i及配線層2j，且分別經由絕緣層2d，絕緣層2f，在最上層的配線層2p及最下層的配線層2q形成複數的配線(配線圖案)。另外，形成於上述最上層的配線層2p之複數的配線的各一部分會構成覆晶連接用的複數的接合導線(電極)2m。
因此，形成於最上層(最表層)的配線層2p的電極之複數的接合導線2m，容易因前述的基板的製造方法(壓接)產生高度偏差。
另外，在配線基板2的最下層的配線層(下面2b側)2q形成有用以連接焊錫球5的複數的接端面2n。亦即，形成於上述最下層的配線層2q之複數的配線的各一部分會構成外部端子之焊錫球連接用的複數的接端面(電極)2n。
藉此，在配線基板2中，上面2a側的複數的接合導線2m，及對應於該等複數的接合導線2m之複數的接端面2n會形成於下面2b側，各對應的接合導線2m及接端面2n會經由未圖示的內部配線或通孔配線等來電性連接。
並且，在配線基板2的上面2a及下面2b的 各表面形成有絕緣膜的抗焊劑膜2c，2g，在上面2a側，複數的接合導線2m會被配置於抗焊劑膜2c的開口部2k，另一方面，在下面2b側，接端面2n會分別被配置於抗焊劑膜2g的複數的開口部2k。
亦即，在配線基板2的上面2a側，以能夠露出複數的接合導線2m之方式在絕緣層2d的上面上形成抗焊劑膜(上面側保護膜)2c，另一方面，在配線基板2的下面2b側，以能夠露出複數的接端面2n之方式在絕緣層2f的下面上形成抗焊劑膜(下面側保護膜)2g。
並且，在上面2a側，複數的接合導線2m是被配置於絕緣層2d上，此絕緣層2d是以具有玻璃布(玻璃纖維)2h的聚酯膠片(樹脂層)2da及不具有玻璃布2h的樹脂層2db所構成，在聚酯膠片2da上層疊樹脂層2db。
因此，複數的接合導線2m是分別接觸於樹脂層2db，配置於此樹脂層2db上。換言之，複數的接合導線2m是藉由樹脂層2db來支撐。
並且，在下面2b側也是複數的接端面2n配置於絕緣層2f上，此絕緣層2f是以具有玻璃布(玻璃纖維)2h的聚酯膠片(樹脂層)2fa及不具有玻璃布2h的樹脂層2fb所構成，與上面2a側同樣，在聚酯膠片2fa上層疊樹脂層2fb。亦即，與上面2a側同樣，複數的接端面2n是分別接觸於樹脂層2fb，配置於此樹脂層2fb上。換言之，複數的接端面2n是分別藉由樹脂層2fb來支撐。
在此，樹脂層(樹脂材)2db，2fb是例如由環 氧系樹脂所形成。樹脂層2db，2fb的樹脂是具有複數的填充物，但為不具玻璃布(玻璃纖維)2h的樹脂。
另一方面，聚酯膠片2da，2fa也是例如由環氧系樹脂所構成。聚酯膠片2da，2fa的樹脂是具有複數的填充物，且具有玻璃布(玻璃纖維)2h。
因此，就具有玻璃布2h的聚酯膠片2da，2fa及不具有玻璃布2h的樹脂層2db，2fb而言，聚酯膠片2da，2fa是硬度較大(高)，剛性也大。亦即，具有玻璃布2h的聚酯膠片2da，2fa硬，但不具有玻璃布2h的樹脂層2db，2fb是硬度小(低)，柔軟。
根據以上，複數的接合導線2m是分別直接配置於柔軟的樹脂層2db上，成為在此柔軟的樹脂層2db的下部配置有硬的聚酯膠片2da之構造。
另一方面，下面2b側的複數的接端面2n是分別直接配置於柔軟的樹脂層2fb上，成為在此柔軟的樹脂層2fb的下部(核心層2e側，下面2b側)配置硬的聚酯膠片2fa之構造。
另外，配線基板2的各接合導線2m或各接端面2n，甚至各配線層的配線等是由以銅為主成分的材料所形成者，各接合導線2m或各接端面2n是在表面施以電鍍。
並且，說明有關配線基板2的各層的厚度，樹脂層的聚酯膠片2da，2fa的厚度是例如分別為30μm，聚酯膠片2da，2fa的上層的樹脂層2db，2fb的厚度是例 如分別為5μm。而且，核心層2e是例如為40~60μm，各配線層是例如數10μm。因此，樹脂層2db，2fb的厚度是比聚酯膠片2da，2fa更薄。
另外，樹脂層2db的厚度亦可與聚酯膠片2da的厚度相同，或比聚酯膠片2da的厚度厚。
然而，在考慮配線基板的彎曲或半導體裝置的薄型化時，最好像本實施形態那樣，將樹脂層2db，2fb的厚度形成比聚酯膠片2da，2fa的厚度更薄。
並且，亦可在配線基板2的各自的接合導線2m的表面(接合面)配置焊錫材3。藉由在各銅支柱4與各接合導線2m配置焊錫材3，可在覆晶連接中被施加荷重時，更吸收各構件的高度偏差。
但，在各接合導線2m不配置焊錫材3時(銅無垢的接合導線2m，或在表面施以鍍金的接合導線2m)是不使用焊錫材3，因此可謀求BGA7的低成本化。
<半導體晶片>
圖8是表示搭載於圖1所示的半導體裝置之半導體晶片的主面側的構造的一例平面圖，圖9是表示沿著圖8所示的A-A線來切斷後的構造的一例剖面圖，圖10是表示搭載於圖1所示的半導體裝置之半導體晶片的背面側的構造的一例背面圖，圖11是表示沿著圖10的A-A線來切斷後的構造的一例剖面圖。
如圖8及圖9所示般，在半導體晶片1的主 面1a，複數的焊墊1c會2列排列配置於主面1a的周縁部(外周部)。本實施形態的半導體晶片1是對應於多針腳化，因此複數的焊墊1c會以交錯配列設置。
而且，如圖10及圖11所示般，在各焊墊1c連接導電性構件的銅支柱4。銅支柱4是柱(杆)狀的電極，例如由以銅(Cu)作為主成分的材料所構成。
並且，銅支柱4是例如藉由電解電鍍法所形成。具體而言，將對應於未圖示的半導體晶圓的各晶片形成領域的焊墊配置之形成有複數的圓形的孔的乾薄膜配置於上述半導體晶圓的主面(元件形成面)而藉由電解電鍍法來對各孔由下堆積形成柱狀。
另外，亦可使用突起(凸塊)狀的電極，作為上述導電性構件。突起狀電極是由例如以金(Au)為主成分的材料所形成。但，突起狀電極的情況是藉由利用毛細管(capillary)的打線接合技術所形成，因此在形成此突起狀電極之前，需要先藉由切斷半導體晶圓來取得半導體晶片。
另一方面，柱狀電極的情況是如上述般在半導體晶圓的主面形成乾薄膜(阻劑膜)，例如藉由電解電鍍法(亦可為無電解電鍍法)來形成於各晶片形成領域的複數的焊墊，因此在考量形成導電性構件的工數時，最好像本實施形態那樣採用柱(杆)狀的電極。
<半導體裝置的製造方法>
圖12是表示使用在圖1所示的半導體裝置的組裝之配線基板的構造的一例平面圖，圖13是表示沿著圖12的A-A線來切斷後的構造的一例剖面圖，圖14是表示圖12所示的配線基板的1個裝置領域的構造的一例剖面圖，圖15是表示圖1所示半導體裝置的組裝之焊錫預塗層後的構造的一例剖面圖。又，圖16是表示圖1所示的半導體裝置的組裝之底部填充膠塗布後的構造的一例平面圖，圖17是表示沿著圖16的A-A線來切斷後的構造的一例剖面圖，圖18是表示圖1所示的半導體裝置的組裝的覆晶安裝工程之晶片搭載後的構造的一例剖面圖，圖19是表示圖18所示的覆晶安裝工程之晶片壓著後的構造的一例剖面圖，圖20是表示圖1所示的半導體裝置的組裝之球型安裝後的構造的一例剖面圖。
1.準備配線基板(多數個取出基板)
如圖12及圖13所示般，本實施形態的配線基板是具有複數的裝置領域2u之多數個取出基板(矩陣基板)2t，雖利用多數個取出基板2t來說明組裝半導體裝置的情況，但亦可為利用預先被小片化成1個的裝置領域2u之配線基板來組裝半導體裝置。
並且，在本實施形態的半導體裝置的組裝中，基於方便起見，利用僅顯示1個的裝置領域2u的圖面來進行說明，但實際就使用多數個取出基板2t的組裝而言，在各工程中，當然是對於多數個取出基板2t上的 複數的裝置領域2u進行所望的處理。
首先，準備多數個取出基板2t。多數個取出基板2t是具有上面2a及與上面2a相反側的下面2b。而且，多數個取出基板2t是具備複數的裝置領域2u(在此是2×4=8個的裝置領域2u作為其一例)，及設在複數的裝置領域2u之中彼此相鄰的裝置領域2u之間的切斷部2r，及平面視設在複數的裝置領域2u的周圍之框部2s。另外，切斷部2r亦被稱為除去部，切割部，或切割領域等。
另外，切斷部2r是如圖13所示般形成溝狀。詳細是在上述電鍍膜形成後藉由蝕刻來除去給電線而形成的溝，該給電線是供以用電解電鍍法來形成實施於各配線的表面的電鍍膜。藉由切斷部2r形成溝狀，可減少小片化工程的切割時產生抗焊劑膜2c的切斷屑。而且，對切割用的刀之負荷也可減低，可謀求切斷性的提升。
並且，在圖12所示的框部2s中各切斷部2r的延長上的位置是附有未圖示的切割用的標記，在小片化的切割時可辨識上述標記來導出上述刀的行進線，然後，使旋轉的上述刀行進而以切斷部2r來切斷。
並且，如圖12所示般，複數的裝置領域2u是分別在其中央部附近的抗焊劑膜2c的開口部2k，覆晶連接用的接合導線2m會沿著多數個取出基板2t的各邊，且配置複數列(在此是2列)。另外，按照圖8所示的半導體晶片1的焊墊1c的配列，2列的接合導線2m會交錯狀地配置。但，複數的接合導線2m是亦可配置成單數列(1 列)。
並且，就本實施形態的多數個取出基板2t而言，在各裝置領域2u中，如圖14所示般，複數的接合導線2m是配置於絕緣層2d上，此絕緣層2d是以具有玻璃布(玻璃纖維)2h的聚酯膠片(樹脂層)2da及不具有玻璃布2h的樹脂層2db所構成，在聚酯膠片2da上層疊有樹脂層2db。
藉此，複數的接合導線2m是分別接觸於樹脂層2db，配置於此樹脂層2db上。換言之，複數的接合導線2m是藉由硬度比聚酯膠片2da小柔軟的樹脂層2db所支撐。
並且，在多數個取出基板2t的下面2b是形成有與上面2a的複數的接合導線2m電性連接之複數的接端面2n，而且，以複數的接端面2n會分別露出的方式，在下面2b上形成抗焊劑膜2g。
另外，多數個取出基板2t是分別疊合核心層(聚酯膠片)2e，及核心層2e的上下的配線層2i，2j，及絕緣層(絕緣膜)2d，2f，及構成複數的接合導線2m之配線層2p，及構成複數的接端面2n之配線層2q，藉由沖壓加工的壓接來形成者。例如，以平板狀的鋼板等來夾著核心層2e，配線層2i，2j，絕緣層2d，2f及配線層2p，2q等的各構件，而以高溫.高壓來進行沖壓加工者。
因此，依裝置領域2u的位置，特別是在最上層的配線層2p的複數的接合導線2m等的電極，或最下 層的配線層2q的複數的接端面2n等的電極，電極高度容易產生偏差。
例如，在形成於最上層(最表層)的配線層2p之複數的接合導線2m中，有可能因沖壓加工的壓接而產生電極高度的偏差。
於是，如圖15所示般，在考慮降低上述電極高度的偏差所造成覆晶連接的連接不良時，最好在各接合導線2m的各表面配置焊錫材3。亦即，藉由在各接合導線2m的各表面配置焊錫材3，覆晶連接時，可吸收上述電極高度的偏差，可降低覆晶連接的連接不良。
但，如圖10的半導體晶片1所示般，採用銅支柱4作為進行覆晶連接的導電性構件時，各接合導線2m的各表面的焊錫材3是亦可不一定要配置。此情況，藉由不配置焊錫材3，可謀求基板的成本的減低化。
2.密封材配置(底部填充膠塗布)
如圖16及圖17所示般，在配線基板2的上面2a配置底部填充膠(密封材)6。此時，以能夠覆蓋複數的接合導線2m之方式配置底部填充膠6。底部填充膠6是例如NCF(Non-Conductive Film)，由絕緣性的環氧系樹脂等所形成的薄膜狀的密封材(黏著材)。但，亦可使用糊狀的密封材之NCP(Non-Conductive Paste)。
另外，在此是說明在覆晶連接前在配線基板2上配置底部填充膠6的情況，但亦可為底部填充膠6是在 覆晶連接後注入配線基板2與半導體晶片1之間者。
3.覆晶安裝
如圖18所示般，首先，將半導體晶片1配置於配線基板2的上面2a上。此時，對準圖10所示的半導體晶片1的複數的焊墊1c與配線基板2的複數的接合導線2m的位置。在此，半導體晶片1是如圖10及圖11所示般，具有被形成於各焊墊1c的柱狀(或突起狀)的導電性構件(在本實施形態是複數的銅支柱4)。
另外，如圖18所示般，在複數的銅支柱4的各個前端面(與接合導線2m對向的面)配置有焊錫材3。
因此，以半導體晶片1的主面1a能夠與配線基板2的上面2a對向的方式，經由複數的銅支柱4來將半導體晶片1配置配線基板2的上面2a上，該半導體晶片1是在各前端面配置焊錫材3的複數的銅支柱4會被設於各焊墊1c。
然後，如圖19所示般，進行晶片壓著。此時，藉由對半導體晶片1的背面1b施加配線基板2的厚度方向(垂直方向，從配線基板2的上面2a往下面2b的方向)的荷重(垂直荷重)F及熱，使形成於銅支柱4的前端面的焊錫材3接觸於配線基板2的接合導線2m。而且，藉由對此銅支柱4與接合導線2m的連接部(接合部)加熱，使焊錫材3溶融，經由焊錫材3來電性連接銅支柱4與接合導線2m。
此時，由於本實施形態的配線基板2是支撐複數的接合導線2m的絕緣層2d為不含玻璃布2h的柔軟的樹脂層2db，因此在以覆晶安裝時的荷重來按壓接合導線2m時，樹脂層2db會變形，設在此樹脂層2db上的接合導線2m會沈入。因此，即使複數的接合導線2m或複數的導電性構件(銅支柱4)的高度產生偏差，還是可進行有關高度低的銅支柱4與接合導線2m的連接。又，由於在各接合導線2m的下部(核心層2e側，下面2b側)配置有柔軟的樹脂層2db，因此在覆晶安裝時，即使從銅支柱4賦予接合導線2m荷重時，還是可藉由柔軟的樹脂層2db沈入來吸收因電極的高度偏差所產生的應力，可使施加於半導體晶片1的應力減低化。
藉此，可降低加在半導體晶片1的損傷，可抑制在半導體晶片1形成龜裂，或表面保護膜剝離的不良情況的發生。亦即，可減低或防止覆晶安裝的半導體晶片1的損傷。
其結果，可使半導體裝置(BGA7)的可靠度提升。
而且，在覆晶安裝時被施加荷重時，支撐複數的接合導線2m之樹脂層2db會沈入，而可吸收複數的銅支柱4或複數的接合導線2m的高度偏差，因此可謀求覆晶安裝之半導體晶片1的連接不良的減低化，可使半導體晶片1的連接可靠度提升。
其結果，可使半導體裝置(BGA7)的可靠度提 升。
並且，在配線基板2中，使聚酯膠片2da的厚度形成比樹脂層2db的厚度厚，藉此因為聚酯膠片2da的硬度比樹脂層2db高，所以可謀求基板的彎曲的減低化。而且，藉由將絕緣層2d的聚酯膠片2da增厚，可將核心層2e的厚度形成薄，因此可使配線基板2的全體的厚度形成薄，可謀求半導體裝置(BGA7)的薄形化。
另外，在各銅支柱4的前端面配置有焊錫材3，藉此因為被賦予熱的焊錫材3會溶融，所以可吸收因在複數的銅支柱4或接合導線2m產生高度偏差而於塞入複數的銅支柱4時所形成的銅支柱4與接合導線2m之間的間隙。
並且，除了各銅支柱4以外，連在各接合導線2m的表面也配置焊錫材3時，可更吸收在複數的銅支柱4或接合導線2m產生的高度偏差，可更謀求覆晶安裝的半導體晶片1的連接不良的減低化。
並且，藉由採用銅支柱4作為導電性構件，可在晶圓段階一起將銅支柱4連接至焊墊1c上，可有效率地將導電性構件連接至複數的焊墊1c。
並且，銅支柱4是柱狀的導電性構件，因此可確保覆晶安裝的電極高度(半導體晶片1與配線基板2的距離)。
另外，在被賦予荷重F時，底部填充膠6也會從上方藉由半導體晶片1來擠碎，因此底部填充膠6會 被充填至覆晶連接部，而且被擠碎的底部填充膠6會溢出至半導體晶片1的周圍而繞進半導體晶片1的各側面，其結果，半導體晶片1的各側面也會被底部填充膠6所覆蓋。
藉由以上的工程，完成覆晶安裝。
4.外部端子形成(球型安裝)
在外部端子形成工程中，如圖20所示般，在配線基板2的下面2b的複數的接端面2n分別形成或連接複數的焊錫球5。另外，焊錫球5也被稱為外部端子或球狀電極等。
另外，連接至複數的接端面2n的外部端子是不限於球狀的焊錫材，亦可為在接端面2n的表面塗層焊錫材者，或在接端面2n的表面形成電鍍膜(電鍍層)者，該情況，半導體裝置是LGA(Land Grid Array)。
並且，使用在焊錫球5的焊錫材也與上述的焊錫材3同樣，實質上不含鉛(Pb)，由所謂無鉛焊錫所構成，例如僅錫(Sn)，或錫-銅-銀(Sn-Cu-Ag)等。
5.小片化
在小片化工程中，利用旋轉的切斷刃之切割用的刀(未圖示)來進行小片化。例如，從圖12所示那樣的多數個取出基板2t的上方，對於切斷部2r，使上述刀進入.旋轉而進行切割，小片化成各BGA7。
另外，小片化是不限於利用上述刀的切割之切斷，亦可進行金屬模具之切斷。
藉此，圖1~圖3所示的BGA7的組裝完了。
<變形例>
以上，根據發明的實施形態具體說明本發明者的發明，但本發明並不限於前述發明的實施形態，當然可在不脫離其要旨的範圍實施各種的變更。
(變形例1)
圖21是表示裝入實施形態的變形例1的半導體裝置之配線基板的上面側的導線配列的一例平面圖。
圖21所示的構造是表示謀求多針腳化的覆晶安裝型的半導體裝置的配線基板2之複數的接合導線2m的配置形態的變形例。
在謀求多針腳化的半導體裝置中，像圖8所示的半導體晶片1那樣，其焊墊1c的配列大多是形成交錯配列的情況，以能夠對應於此的方式，設在圖21所示的配線基板側的抗焊劑膜2c的開口部2k之複數的接合導線2m的配列也以外周導線群2ma及內周導線群2mb來配置成2列。
而且，在配線基板2中，內周導線群2mb是平面視具有：複數的接合導線2mba，其係延伸於與半導體晶片1 的邊1d交叉(大致正交)的方向；複數的接合導線2mbb，其係延伸於與半導體晶片1的邊1e交叉(大致正交)的方向；及複數的接合導線2mbc，其係延伸於不與邊1d及邊1e正交的方向。
亦即，露出於抗焊劑膜2c的框狀的開口部2k之內周導線群2mb的複數的接合導線2m是依其延伸方向來分成上述3種類(接合導線2mba，2mbb，2mbc)。此3種類的接合導線2m之中，延伸於與半導體晶片1的邊1d及邊1e皆不正交的方向之複數的接合導線2mbc是配置在框狀的開口部2k的角部附近。
亦即，內周導線群2mb的接合導線2m之中，配置於開口部2k的角部附近之接合導線2mbc是形成和位於與配置有此接合導線2mbc的導線列大致正交的其他導線列的端部(角部)之接合導線2mbc容易接觸的配置。因此，對於配列的中央部附近的接合導線2m傾斜配置。此時，若僅傾斜配置端部的位置的接合導線2mbc，則與此接合導線2mbc同列相鄰的接合導線2mbc和導線的內側端部彼此間會干擾，因此各角部附近的複數(在圖21是自端部起4條)的接合導線2mbc是成為從配線基板2的中央部往外方形成放射狀那樣的傾斜配置。
因此，對於半導體晶片1的哪個邊1d，1e，各接合導線2mbc的延伸方向皆不會有正交的情形。
藉此，可防止與相鄰的接合導線2m的短路。 其結果，可使對應於半導體裝置的多針腳化。
並且，內周導線群2mb的各接合導線2m是沿著與覆蓋各接合導線2m的一部分之絕緣膜的一部分的內側抗焊劑膜(內側絕緣膜)2ca的端部交叉(大致正交)的方向而延伸。
亦即，內周導線群2mb的各接合導線2m是全部在大略四角形的內側抗焊劑膜2ca的各邊，配置成與該邊(端部)正交。藉此，內周導線群2mb的各接合導線2m之從內側抗焊劑膜2ca的露出長度可設為彼此大致同長度。此情形是有關外周導線群2ma的各接合導線2m也同樣，配置於開口部2k的各接合導線2m之從抗焊劑膜2c的露出部分會被配置成大致同長度。
藉此，即使是在接合導線2m上形成焊錫預塗層時，還是在各導線間預塗層大致同量的焊錫，可大致同高度地形成焊錫預塗層。
其結果，可謀求覆晶安裝時的焊錫浸潤性的均一化。
(變形例2)
圖22是表示實施形態的變形例2的半導體裝置的構造的一例剖面圖。
本變形例2的半導體裝置是晶片層疊型的半導體裝置，是在被覆晶安裝於配線基板2的半導體晶片1上搭載有別的半導體晶片8，上段側的半導體晶片8會以 接線連接來電性連接至配線基板2之半導體裝置。
並且，在配線基板2的下面2b側是配置有複數的焊錫球5，作為外部端子，因此，圖22所示的半導體裝置亦為BGA12。
另外，就BGA12而言，例如下段側的半導體晶片1是控制器晶片，上段側的半導體晶片8是記憶體晶片。因此，上段側的半導體晶片8亦為藉由下段側的半導體晶片1來控制的SIP(System In Package)型的半導體裝置。但，半導體晶片1及半導體晶片8是亦可為具備上述以外的機能的半導體晶片。
並且，上段側的半導體晶片8是在下段側的半導體晶片1的背面1b上，將主面8a朝上的狀態下經由黏晶材9來接著。因此，下段側的半導體晶片1的背面1b與上段側的半導體晶片8的背面8b是藉由黏晶材9來接合。
並且，半導體晶片8的主面8a的焊墊8c與配線基板2的上面2a的接合導線2v是藉由接線(導電性構件)10來電性連接。接線10是金線或銅線。
並且，下段側的半導體晶片1是與實施形態的BGA7同樣，經由複數的銅支柱4等的導電性構件來覆晶連接至配線基板2的複數的接合導線2m。而且，覆晶連接部是藉由底部填充膠6來保護，半導體晶片1的背面1b，及半導體晶片8或複數的接線10是藉由密封用樹脂所形成的密封體11來密封。形成密封體11的密封用樹脂 是例如環氧系的熱硬化性樹脂等。
另外，在本變形例2的BGA12中，其配線基板2也與實施形態的BGA7的配線基板2同樣，複數的接合導線2m是配置於絕緣層2d上，此絕緣層2d是以具有玻璃布(玻璃纖維)2h的聚酯膠片(樹脂層)2da，及形成(層疊)於聚酯膠片2da上之不具有玻璃布2h的樹脂層2db所構成。
因此，複數的接合導線2m是分別接觸於樹脂層2db，配置於此樹脂層2db上。亦即，複數的接合導線2m是藉由硬度比聚酯膠片2da小之柔軟的樹脂層2db所支撐。
藉此，因為在各接合導線2m的下部配置有柔軟的樹脂層2db，所以與實施形態的BGA7同樣，在覆晶安裝時，即使從銅支柱4賦予接合導線2m荷重時，還是可藉由柔軟的樹脂層2db沈入來吸收因電極的高度偏差所產生的應力，可使施加於半導體晶片1的應力減低化。
其結果，可減低加在半導體晶片1的損傷，可抑制在半導體晶片1形成龜裂，或表面保護膜剝離的不良情況的的發生。亦即，可減低或防止覆晶安裝之半導體晶片1的損傷。藉此，可使半導體裝置(BGA12)的可靠度提升。
另外，有關藉由BGA12及其組裝而取得的其他效果是與實施形態的BGA7同樣，因此其重複說明省略。
(變形例3)
並且，在上述實施形態中是說明有關使用例如以銅(Cu)為主成分的材料，作為電性連接半導體晶片1與配線基板2的柱狀或突起狀的導電性構件，但並非限於此。亦即，亦可使用例如以金(Au)為主成分的材料，作為比銅(Cu)更柔軟的材料。
另外，金(Au)是一旦施加荷重，則相較於銅(Cu)，導電性構件的本身會容易變形(容易崩潰)。因此，作為支撐配線基板2的電極(接合導線2m)的絕緣層，並非一定要像上述實施形態那樣，藉由2層構造的絕緣層來支撐配線基板2的電極(接合導線2m)。換言之，可採用比不含玻璃布(玻璃纖維)2h的樹脂層更硬的材料(例如，聚酯膠片)作為支撐配線基板2的電極(接合導線2m)的絕緣層。
然而，當導電性構件或電極(接合導線)的高度的偏差量大時，導電性構件的變形量(崩潰量)變大。因此，不想要使導電性構件極度地變形時，即使是藉由以金(Au)為主成分的材料來形成導電性構件時，也最好是使用具有上述實施形態那樣的構成的絕緣層之配線基板2。
(變形例4)
圖23是表示被裝入至實施形態的變形例4的半導體裝置的配線基板的構造的一例剖面圖。
本變形例4是表示搭載於半導體裝置的配線基板的變形例。圖23所示的配線基板2是具有2層的配線層，所謂2層基板，在核心層(聚酯膠片)2e的表面側形成有配線層2p，另一方面，在核心層2e的背面側形成有配線層2q。
在圖23的配線基板2中也是在形成於配線層2p的複數的接合導線(電極)2m的下部配置有硬度比具有玻璃布2h的核心層2e小的樹脂層2db。並且，在下面2b側也是在形成有複數的接端面(電極)2n的配線層2q與核心層2e之間配置有硬度比核心層2e小的樹脂層2w。
因此，就本變形例4的配線基板2而言，絕緣層2d是藉由樹脂層2db，核心層2e及樹脂層2w所構成。而且，複數的接合導線2m是藉由柔軟的樹脂層(不含有玻璃布的層)2db所支撐，另一方面，複數的接端面2n是藉由柔軟的樹脂層(不含有玻璃布的層)2w所支撐。
在本變形例4的2層配線構造的配線基板2中也是在複數的接合導線2m的下部配置有柔軟的樹脂層2db。因此，與實施形態的BGA7同樣，一旦在覆晶安裝時經由接合導線2m來賦予樹脂層2db荷重，則樹脂層2db會變形，接合導線2m會沈入。此結果，即使在圖2所示的銅支柱4的高度產生偏差，全部的銅支柱4還是可與接合導線2m連接。亦即，即使為高度低的銅支柱4，還是可與接合導線2m連接。
並且，如上述般，由於與複數的銅支柱4之 中，高度比其他的銅支柱4更高的銅支柱連接的配線基板2的接合導線2m會沈入，因此可抑制在形成有此高度高的銅支柱4之半導體晶片1的焊墊1c正下面的絕緣層形成龜裂67(參照圖26)。藉此，可使BGA7的可靠度提升。
而且，即使應力作用於半導體裝置(BGA7)的焊錫球5等時，還是可藉由柔軟的樹脂層2db來使應力緩和，可抑制損傷直接傳至覆晶連接部。
亦即，在連接上述銅支柱4的接合導線2m的下部配置有柔軟的樹脂層2db，因此即使含熱應力等的應力作用於焊錫球5時，還是可藉由柔軟的樹脂層2db的變形來緩和上述應力而以損傷不會直接傳至覆晶連接部或半導體晶片1的方式吸收上述應力。
其結果，可抑制覆晶連接部的連接不良的發生。
另外，有關藉由上述半導體裝置及其組裝而取得的其他效果是與實施形態的BGA7同樣，因此其重複說明省略。
(變形例5)
有關不含玻璃布的樹脂層2db，2fb與含玻璃布2h的樹脂層(聚酯膠片2da，2fa)的位置關係是不限於上述實施形態那樣的層疊構造。亦即，如圖24所示般，不含玻璃布的樹脂層2db，2fb是亦可只設在連接柱狀(或突起狀)的 導電性構件(銅支柱4)的電極(接合導線2m)的正下面。
然而，若考慮配線基板2的製造效率(工程數)，則像上述的本實施形態那樣，最好將各層疊層(樹脂層)2da，2db，2fa，2fb形成層疊構造。
(變形例6)
在上述實施形態中，半導體裝置是以BGA的情況為例進行說明，但上述半導體裝置是不限於BGA，亦可為在接端面的表面形成有導電性構件的LGA(Land Grid Array)。
(變形例7)
而且，可在不脫離上述實施形態說明的技術思想主旨的範圍內，將變形例彼此間組合而適用。
2‧‧‧配線基板
2a‧‧‧上面(晶片搭載面)
2b‧‧‧下面
2c‧‧‧抗焊劑膜(上面側保護膜)
2d‧‧‧絕緣層(絕緣膜)
2da‧‧‧聚酯膠片(樹脂層)
2db‧‧‧樹脂層(樹脂材)
2e‧‧‧核心層(聚酯膠片)
2f‧‧‧絕緣層(絕緣膜)
2fa‧‧‧聚酯膠片(樹脂層)
2fb‧‧‧樹脂層
2g‧‧‧抗焊劑膜(下面側保護膜)
2h‧‧‧玻璃布(玻璃纖維)
2i，2j‧‧‧配線層
2k‧‧‧開口部
2m‧‧‧接合導線(電極)
2n‧‧‧接端面(電極)
2p，2q‧‧‧配線層

Claims (6)

  1. 一種半導體裝置的製造方法，其特徵係包含以下的工程：(a)準備配線基板的工程，該配線基板係具有：第1絕緣層，第2絕緣層，第1配線層及第2配線層，在此，前述第1絕緣層係以具有玻璃纖維的第1樹脂層及不具有玻璃纖維的第2樹脂層所構成，前述第2樹脂層係以在前述第1樹脂層與前述第2樹脂層之間不具有配線層的方式被層疊於前述第1樹脂層上，前述第2絕緣層係以具有玻璃纖維的第3樹脂層所構成，具有複數的第1配線圖案之前述第1配線層係被配置於前述第1絕緣層的前述第1樹脂層與前述第2絕緣層的前述第3樹脂層之間，被形成於前述第2配線層的複數的接合導線係分別被形成於前述第2樹脂層上；(b)前述(a)工程之後，以半導體晶片的前述主面能夠與前述配線基板的前述第2樹脂層的表面對向的方式，經由複數的導電性構件來將半導體晶片配置於前述配線基板的前述第2樹脂層的前述表面上的工程，該半導體晶片係具有：主面，形成於前述主面的複數的焊墊，及與前述主面相反側的背面；(c)前述(b)工程之後，對前述半導體晶片的前述背面 施加前述配線基板的厚度方向的荷重，藉此經由前述複數的導電性構件來分別電性連接前述複數的焊墊與前述複數的接合導線的工程。
  2. 如申請專利範圍第1項之半導體裝置的製造方法，其中，前述第2樹脂層的厚度係比前述第1樹脂層的厚度更薄。
  3. 如申請專利範圍第2項之半導體裝置的製造方法，其中，前述複數的導電性構件係分別由以銅為主成分的材料所形成。
  4. 如申請專利範圍第3項之半導體裝置的製造方法，其中，前述(c)工程之前，在前述複數的導電性構件的各個的前端面配置有焊錫材，在前述配線基板的前述複數的接合導線的各個的表面未配置有焊錫材。
  5. 如申請專利範圍第4項之半導體裝置的製造方法，其中，前述配線基板係分別疊合前述第1絕緣層，前述第2絕緣層，前述第1配線層及構成前述複數的接合導線之前述第2配線層，及構成前述複數的接端面之第3配線層，更在壓接下被形成。
  6. 如申請專利範圍第5項之半導體裝置的製造方法，其中，前述複數的導電性構件係分別為柱狀。
TW103112076A 2013-04-17 2014-04-01 半導體裝置及其製造方法 TWI600123B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013086899A JP6161380B2 (ja) 2013-04-17 2013-04-17 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW201507073A TW201507073A (zh) 2015-02-16
TWI600123B true TWI600123B (zh) 2017-09-21

Family

ID=51709455

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103112076A TWI600123B (zh) 2013-04-17 2014-04-01 半導體裝置及其製造方法

Country Status (6)

Country Link
US (1) US20140312498A1 (zh)
JP (1) JP6161380B2 (zh)
KR (1) KR20140124725A (zh)
CN (1) CN104112715B (zh)
HK (1) HK1201990A1 (zh)
TW (1) TWI600123B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140019173A (ko) * 2012-08-06 2014-02-14 삼성전기주식회사 솔더 코팅볼을 이용한 패키징 방법 및 이에 따라 제조된 패키지
TWI489176B (zh) * 2012-12-14 2015-06-21 Elan Microelectronics Corp 行動電子裝置的螢幕控制模組及其控制器
US20150279775A1 (en) * 2012-12-14 2015-10-01 Elan Microelectronics Corporation Screen control module of a mobile electronic device and controller thereof
JP2015222741A (ja) * 2014-05-22 2015-12-10 京セラサーキットソリューションズ株式会社 多数個取り配線基板およびその製造方法
KR102609199B1 (ko) * 2015-09-25 2023-12-05 세키스이가가쿠 고교가부시키가이샤 접속 구조체의 제조 방법, 도전성 입자, 도전 필름 및 접속 구조체
CN107205310B (zh) * 2017-06-29 2019-12-24 惠科股份有限公司 一种电路板和显示装置

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07336002A (ja) * 1994-06-08 1995-12-22 Hitachi Chem Co Ltd 配線板及びその製造法
US5834849A (en) * 1996-02-13 1998-11-10 Altera Corporation High density integrated circuit pad structures
TW383435B (en) * 1996-11-01 2000-03-01 Hitachi Chemical Co Ltd Electronic device
SG76530A1 (en) * 1997-03-03 2000-11-21 Hitachi Chemical Co Ltd Circuit boards using heat resistant resin for adhesive layers
EP2086299A1 (en) * 1999-06-02 2009-08-05 Ibiden Co., Ltd. Multi-layer printed circuit board and method of manufacturing multi-layer printed circuit board
DE10020374A1 (de) * 1999-07-02 2001-01-25 Fujitsu Ltd Kopfbaugruppe einer Plattenvorrichtung mit einem Kopf-IC-Chip, der durch Ultraschallbonden an eine Aufhängung montiert ist
US6965160B2 (en) * 2002-08-15 2005-11-15 Micron Technology, Inc. Semiconductor dice packages employing at least one redistribution layer
JP2004179545A (ja) * 2002-11-28 2004-06-24 Kyocera Corp 配線基板
CN1792126A (zh) * 2003-05-19 2006-06-21 大日本印刷株式会社 双面布线基板和双面布线基板的制造方法以及多层布线基板
KR100834591B1 (ko) * 2003-05-19 2008-06-02 다이니폰 인사츠 가부시키가이샤 양면 배선기판과, 양면 배선기판 제조방법 및 다층배선기판
US7144759B1 (en) * 2004-04-02 2006-12-05 Celerity Research Pte. Ltd. Technology partitioning for advanced flip-chip packaging
JP2006202969A (ja) * 2005-01-20 2006-08-03 Taiyo Yuden Co Ltd 半導体装置およびその実装体
US20070230150A1 (en) * 2005-11-29 2007-10-04 International Business Machines Corporation Power supply structure for high power circuit packages
WO2007063960A1 (ja) * 2005-12-01 2007-06-07 Sumitomo Bakelite Company Limited プリプレグ、プリプレグの製造方法、基板および半導体装置
JP4929784B2 (ja) * 2006-03-27 2012-05-09 富士通株式会社 多層配線基板、半導体装置およびソルダレジスト
CN102176808B (zh) * 2007-01-29 2014-04-09 住友电木株式会社 层叠体、基板的制造方法、基板及半导体装置
JP2008198747A (ja) * 2007-02-09 2008-08-28 U-Ai Electronics Corp プリント基板及びプリント基板の製造方法
US7893527B2 (en) * 2007-07-24 2011-02-22 Samsung Electro-Mechanics Co., Ltd. Semiconductor plastic package and fabricating method thereof
US7642135B2 (en) * 2007-12-17 2010-01-05 Skyworks Solutions, Inc. Thermal mechanical flip chip die bonding
US8030752B2 (en) * 2007-12-18 2011-10-04 Samsung Electro-Mechanics Co., Ltd. Method of manufacturing semiconductor package and semiconductor plastic package using the same
JP5001903B2 (ja) * 2008-05-28 2012-08-15 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US8563397B2 (en) * 2008-07-09 2013-10-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
JP5479233B2 (ja) * 2010-06-04 2014-04-23 新光電気工業株式会社 配線基板及びその製造方法
JP5587123B2 (ja) * 2010-09-30 2014-09-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP5715835B2 (ja) * 2011-01-25 2015-05-13 新光電気工業株式会社 半導体パッケージ及びその製造方法
KR101562486B1 (ko) * 2012-04-26 2015-10-21 니혼도꾸슈도교 가부시키가이샤 다층배선기판 및 그 제조방법
TWI488273B (zh) * 2012-07-18 2015-06-11 Chipbond Technology Corp 半導體製程及其半導體結構
JP5990421B2 (ja) * 2012-07-20 2016-09-14 新光電気工業株式会社 配線基板及びその製造方法、半導体パッケージ

Also Published As

Publication number Publication date
HK1201990A1 (zh) 2015-09-11
JP6161380B2 (ja) 2017-07-12
TW201507073A (zh) 2015-02-16
JP2014212174A (ja) 2014-11-13
KR20140124725A (ko) 2014-10-27
CN104112715A (zh) 2014-10-22
US20140312498A1 (en) 2014-10-23
CN104112715B (zh) 2018-04-10

Similar Documents

Publication Publication Date Title
KR100868419B1 (ko) 반도체장치 및 그 제조방법
TWI600123B (zh) 半導體裝置及其製造方法
JP5579402B2 (ja) 半導体装置及びその製造方法並びに電子装置
US10879203B2 (en) Stud bump structure for semiconductor package assemblies
US9418968B2 (en) Semiconductor device including semiconductor chips mounted over both surfaces of substrate
US10121736B2 (en) Method of fabricating packaging layer of fan-out chip package
KR20130076899A (ko) 상부 ic 패키지와 결합하여 패키지-온-패키지 (pop) 어셈블리를 형성하는 하부 ic 패키지 구조체 및 그러한 하부 ic 패키지 구조체를 포함하는 pop 어셈블리
TWI587415B (zh) 半導體裝置之製造方法
JP2015005637A (ja) 半導体装置
JP2014007228A (ja) 半導体装置及びその製造方法
KR20150060758A (ko) 반도체 장치 및 그 제조방법
JP2016063013A (ja) 半導体装置
CN111883506B (zh) 电子封装件及其承载基板与制法
JP5547703B2 (ja) 半導体装置の製造方法
US20170025386A1 (en) Semiconductor device
KR101494411B1 (ko) 반도체패키지 및 이의 제조방법
JP2010251547A (ja) 半導体装置及びその製造方法
JP2009283835A (ja) 半導体装置及びその製造方法
WO2017043480A1 (ja) 半導体パッケージ
TW201507097A (zh) 半導體晶片及具有半導體晶片之半導體裝置
JP2013157433A (ja) 半導体装置
US20230420336A1 (en) Fan-out type semiconductor package and method of manufacturing the same
JP2014212356A (ja) 半導体装置およびその製造方法
JP5297445B2 (ja) 半導体装置
JP2015076539A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees