TWI593024B - 薄膜電晶體的製造方法 - Google Patents

薄膜電晶體的製造方法 Download PDF

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TWI593024B
TWI593024B TW104124039A TW104124039A TWI593024B TW I593024 B TWI593024 B TW I593024B TW 104124039 A TW104124039 A TW 104124039A TW 104124039 A TW104124039 A TW 104124039A TW I593024 B TWI593024 B TW I593024B
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thin film
film transistor
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葉家宏
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友達光電股份有限公司
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Priority to CN201510587300.9A priority patent/CN105280716B/zh
Priority to US14/938,818 priority patent/US9577111B2/en
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Description

薄膜電晶體的製造方法
本發明是關於一種主動元件的製造方法，且特別是關於一種薄膜電晶體的製造方法。
近來環保意識抬頭，具有低消耗功率、空間利用效率佳、無輻射、高畫質等優越特性的平面顯示面板(flat display panels)已成為市場主流。常見的平面顯示器包括液晶顯示器(liquid crystal displays)、電漿顯示器(plasma displays)、有機電激發光顯示器(electroluminescent displays)等。
以目前最普及的液晶顯示器為例，液晶顯示器主要是由畫素陣列基板、彩色濾光基板以及夾設於二者之間的液晶層所構成。在習知的畫素陣列基板上，多採用薄膜電晶體作為各個畫素結構的切換元件，而切換元件的性能多取決於薄膜電晶體之主動層的品質好壞。薄膜電晶體的主動層(例如：金屬氧化物半導體)容易在圖案化源極與汲極的過程中或被外界水氣損傷，而不利於 薄膜電晶體的品質。為改善此問題，在習知的薄膜電晶體製造方法中，先在薄膜電晶體的主動層上形成蝕刻阻擋層，之後再圖案化蝕刻阻擋層上方的金屬層，以形成薄膜電晶體的源極與汲極。藉此，無論是利用溼式或乾式蝕刻程序圖案化出源極與汲極，溼式蝕刻的蝕刻液或乾式蝕刻的電漿都不易損傷薄膜電晶體的主動層。此外，由於蝕刻阻擋層覆蓋至少部份之主動層的面積，因此水氣接觸主動層的機率降低，進而減少了非晶態的主動層因水氣影響而劣化成導體的機率。然而，蝕刻阻擋層的設置卻造成畫素陣列基板的開口率下降、薄膜電晶體的製造成本提高等問題。
本發明提供一種薄膜電晶體，具高品質且成本低。
本發明的薄膜電晶體的製造方法，包括下列步驟：在基板上依序形成半導體層、金屬層以及輔助層；在金屬層以及輔助層位於半導體層上方的情況下，對半導體層進行一結晶程序，以形成主動層；於形成主動層後，圖案化金屬層，以形成源極與汲極；形成閘極；以及形成閘極絕緣層，其中閘極絕緣層位於閘極以及源極與汲極之間。
基於上述，在本發明一實施例的薄膜電晶體製造方法中，在圖案化金屬層以形成源極與汲極之前，利用一結晶程序形成具有結晶成份的主動層。利用所述結晶成份的抗蝕刻特性，主動層在圖案化金屬層的過程中不易受到蝕刻液的損傷，進而能夠 製造出高品質且低成本的薄膜電晶體。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10‧‧‧基板
110‧‧‧半導體層
110a‧‧‧頂面
110b‧‧‧側壁
120‧‧‧金屬層
130‧‧‧輔助層
CH‧‧‧主動層
D‧‧‧汲極
G‧‧‧閘極
GI‧‧‧閘極絕緣層
L‧‧‧準分子雷射
MCH、M1、M2‧‧‧主要分佈
S110~S150‧‧‧步驟
S210~S230‧‧‧曲線
S‧‧‧源極
圖1為本發明一實施例之薄膜電晶體製造方法的流程示意圖。
圖2A~圖2E為本發明一實施例之薄膜電晶體製造方法的剖面示意圖。
圖3示出本發明一實施例之主動層的X射線繞射(X-ray Diffraction；XRD)圖譜。
圖4A~圖4D為本發明另一實施例之薄膜電晶體製造方法的剖面示意圖。
圖1為本發明一實施例之薄膜電晶體製造方法的流程示意圖。請參照圖1，薄膜電晶體的製造方法至少包括下列步驟：在基板上依序形成半導體層、金屬層以及輔助層(步驟S110)；在金屬層以及輔助層位於半導體層上方的情況下，對半導體層進行結晶程序，以形成主動層(步驟S120)；於形成主動層後，圖案化金屬層，以形成源極與汲極(步驟S130)；形成閘極絕緣層(S140)； 以及，形成閘極(步驟S150)。需說明的是，上述步驟S110~S150的順序並不限於圖1所示之步驟S110、S120、S130、S140、S150。上述步驟S110~S150的順序可做適當的更動。舉例而言，上述步驟S110~S150的順序亦可依序為步驟S150、S140、S110、S120、S130。
以下將搭配圖2A~圖2E、圖4A~圖4D對所述之薄膜電晶體的製造方法進行詳細的說明。
圖2A~圖2E為本發明一實施例之薄膜電晶體製造方法的剖面示意圖。請參照圖2A，在本實施例中，可先在基板10上依序形成半導體層110、金屬層120以及輔助層130。半導體層110可為一區塊，而金屬層120與輔助層130可為一整面性膜層且覆蓋半導體層110的頂面110a與側壁110b。基板10可為透光基板、或不透光/反光基板。透光基板的材質可為玻璃、石英、有機聚合物或其它可適用的材料。不透光/反光基板的材質可為導電材料、晶圓、陶瓷或其它可適用的材料。
在本實施例中，半導體層110例如為金屬氧化物半導體層。更進一步地說，金屬氧化物半導體的材料可為包含銦(In)之金屬氧化物半導體材料{例如：氧化銦鎵鋅(Indium-Gallium-Zinc Oxide；IGZO)、氧化銦鋅(Indium-Zinc Oxide；IZO)、氧化銦錫(Indium-Tin Oxide；ITO)或是其他適當材料}、含鋅(Zn)之金屬氧化物半導體材料{例如：氧化鋅(ZnO)、氧化鎵鋅(Gallium-Zinc Oxide；GZO)、氧化鋅錫(Zinc-Tin Oxide；ZTO)或是其他適當 材料}、含鎵(Ga)之金屬氧化物半導體材{例如：氧化銦鎵鋅(Indium-Gallium-Zinc Oxide；IGZO)或是其他適當材料}。然而，本發明並不限制半導體層110的材料一定要是金屬氧化物半導體，在其他實施例中，半導體層110的材料亦可為非晶矽、多晶矽、微晶矽、單晶矽、有機半導體材料、或其它適當的材料。金屬層120的材質可為鉬(Mo)、鋁(Al)、鎢化鉬(MoW)、鎢化銅(CuW)、其他適當材料、或上述至少二者的組合。輔助層130的材質可為非晶矽、多晶矽、單晶、其他適當材料、或上述至少二者的組合。
請參照圖2A，接著，在本實施例中，可選擇性地利用快速熱退火製程(Rapid Thermal Processing；RTP)(未繪示)對輔助層130或/及金屬層120進行一去氫處理程序，以降低氫爆的機率。然而，本發明不限於此，在其他實施例中，亦可利用其他方法進行去氫處理程序，或省略去氫處理的步驟。
請參照圖2B，接著，在金屬層120以及輔助層130位於半導體層110上方的情況下，對半導體層110進行結晶程序，以使半導體層110轉變為主動層CH。舉例而言，在本實施例中，可利用準分子雷射結晶(Excimer Laser Crystallization；ELC)程序，使半導體層110轉變為主動層CH。詳言之，可令準分子雷射L照射輔助層130，準分子雷射L的光線波長與輔助層130的吸光波長匹配，因此輔助層130會吸收準分子雷射L而產生熱能，所述熱能則透過金屬層120傳遞至半導體層110，進而使得半導體層 110結晶，以形成主動層CH。金屬層120除了扮演傳遞熱能的角色外，還可降低半導體層110於轉變成主動層CH的過程發生剝落(peeling)的機率。在本實施例中，準分子雷射L的能量例如是大於70微焦耳(mJ)，且可選擇性地在攝氏0度至25度下進行準分子雷射結晶程序。然而，本發明不限於此，在其他實施例中，亦可利用其他適當方法(例如：以紅外飛秒雷射、綠光雷射進行結晶程序)，使半導體層110結晶，以形成主動層CH。
利用結晶程序形成之主動層CH具有結晶成份，以下以圖3為例並佐證之。圖3示出本發明一實施例之主動層的X射線繞射(X-ray Diffraction；XRD)圖譜。請參照圖3，曲線S210代表利用結晶程序形成之主動層CH(例如：IGZO)的X射線繞射圖譜，曲線S220代表InGaZnO4的X射線繞射圖譜，而曲線S230代表InGaO(ZnO)15的X射線繞射圖譜。比對主動層CH的X射線繞射圖譜(即曲線S210)與InGaZnO4的X射線繞射圖譜(即曲線S220)及InGaO(ZnO)15的X射線繞射圖譜(即曲線S230)可發現，主動層CH之X射線繞射圖譜(即曲線S210)的主要分佈MCH與InGaZnO4之X射線繞射圖譜(即曲線S220)的主要分佈M1以及InGaO(ZnO)15之X射線繞射圖譜(即曲線S230)的主要分佈M2重疊。由此可知，主動層CH具有例如是InGaZnO4以及InGaO(ZnO)15的結晶成份，但本發明不以此為限。
請參照圖2C，接著，在本實施例中，可選擇性地在圖案化金屬層120之前，移除輔助層130。舉例而言，在本實施例中， 可利用溼式蝕刻程序去除輔助層130，但本發明不以此為限。此外，需說明的是，本發明並不限制一定要在圖案化金屬層120之前移除輔助層130。在本發明另一實施例中，亦可同時圖案化金屬層120與輔助層130，然後，再將與圖案化金屬層120(即源極S與汲極D)切齊的圖案化輔助層(未繪示)移除。
請參照圖2D，接著，圖案化金屬層120，以形成源極S與汲極D。源極S與汲極D彼此分離，且分別與主動層CH的二端電性連接。舉例而言，在本實施例中，可利用溼式蝕刻程序(wet etching process)圖案化金屬層120，以形成源極S與汲極D。值得一提的是，由於主動層CH是利用結晶程序形成的，因此主動層CH具有結晶成份。利用溼式蝕刻程序圖案化金屬層120以形成源極S、汲極D時，主動層CH的結晶成份可抵抗溼式蝕刻程序中所使用之蝕刻液的侵蝕，而使主動層CH不易受損。如此一來，便可利用製程時間短、成本低之溼式蝕刻程序圖案化金屬層120以形成源極S與汲極D，並兼顧最終形成之主動層CH的品質，進而製作出品質佳且成本低的薄膜電晶體。
請參照圖2E，接著，可形成閘極絕緣層GI。閘極絕緣層GI覆蓋源極S、汲極D以及被源極S與汲極D暴露出的部份主動層CH。接著，可於閘極絕緣層GI上形成閘極G。閘極絕緣層GI位於閘極G以及源極S與汲極D之間。閘極G利用閘極絕緣層GI與源極S、汲極D隔開，且閘極G與主動層CH重疊。於此便完成了本實施例之薄膜電晶體。
如圖2E所示，在本實施例中，閘極G位於主動層CH上方，意即，本實施例的薄膜電晶體可為一頂部閘極型薄膜電晶體(top gate TFT)。然而，本發明的薄膜電晶體製造方法並不限於僅能用以製造頂部閘極型薄膜電晶體，本發明的薄膜電晶體製造方法亦可用於製造其他型式的薄膜電晶體，以下以圖4A~圖4D為例說明之。
圖4A~圖4D為本發明另一實施例之薄膜電晶體製造方法的剖面示意圖。圖4A~圖4D的薄膜電晶體製造方法與圖2A~圖2E的薄膜電晶體製造方法類似，因此相同或相對應的元件以相同或相對應的標號表示。圖4A~圖4D之薄膜電晶體製造方法與圖2A~圖2E之薄膜電晶體製造方法的差異在於：二者形成閘極G與閘極絕緣層GI的時間點不同。以下主要就此差異處做說明，二者相同之處還請依照圖4A~圖4D中的標號對應地參照前述說明，於此便不再重述。
請參照圖4A，在本實施例中，可先在基板10上形成閘極G，然後，於閘極G上形成閘極絕緣層GI。接著，在閘極絕緣層GI上依序形成圖案化半導體層110、金屬層120以及輔助層130，其中半導體層110與閘極G重疊。請參照圖4B，接著，在金屬層120以及輔助層130位於半導體層110上方的情況下，對半導體層110進行一結晶程序，以形成主動層CH。請參照圖4C，接著，移除輔助層130。請參照圖4D，接著，圖案化金屬層120，以形成源極S以及汲極D，於此便完成了薄膜電晶體。
如圖4D所示，在本實施例中，閘極G位於主動層CH下方，意即，本實施例的薄膜電晶體可為一底部閘極型薄膜電晶體(bottom gate TFT)。然而，需說明的是，本發明的薄膜電晶體製造方法並不限於僅能用以製造前述的頂部閘極型及底部閘極型薄膜電晶體，本發明的薄膜電晶體製造方法亦可用於製造其他型式的薄膜電晶體(例如：雙閘極薄膜電晶體等)。本領域具有通常知識者根據前述說明應能夠利用本發明的薄膜電晶體製造方法實現其他型式的薄膜電晶體，故於此便不再逐一詳述。
綜上所述，在本發明一實施例的薄膜電晶體製造方法中，在圖案化金屬層以形成源極與汲極之前，便利用一結晶程序形成具有結晶成份的主動層。利用所述結晶成份的抗蝕刻特性，主動層在圖案化金屬層的過程中不易受到蝕刻液的損傷，進而能夠製造出高品質且低成本的薄膜電晶體。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
S110~S150‧‧‧步驟

Claims (11)

  1. 一種薄膜電晶體的製造方法，包括：在一基板上依序形成一半導體層、一金屬層以及一輔助層；在該金屬層以及該輔助層位於該半導體層上方的情況下，對該半導體層進行一結晶程序，以形成一主動層；於進行該結晶程序而形成該主動層後，圖案化該金屬層，以形成一源極與一汲極；形成一閘極；以及形成一閘極絕緣層，其中該閘極絕緣層位於該閘極以及該源極與該汲極之間。
  2. 如申請專利範圍第1項所述的薄膜電晶體的製造方法，其中於形成該輔助層之後，更包括對該輔助層或該金屬層進行一去氫處理程序。
  3. 如申請專利範圍第1項所述的薄膜電晶體的製造方法，其中該輔助層包括非晶矽、多晶矽或單晶。
  4. 如申請專利範圍第1項所述的薄膜電晶體的製造方法，其中該結晶程序包括以準分子雷射、紅外飛秒雷射、綠光雷射進行結晶程序。
  5. 如申請專利範圍第4項所述的薄膜電晶體的製造方法，其中該準分子雷射結晶程序所使用之準分子雷射的能量大於70微焦耳(mJ)。
  6. 如申請專利範圍第1項所述的薄膜電晶體的製造方法，其中該金屬層包括鉬、鋁、鎢化鉬或鎢化銅。
  7. 如申請專利範圍第1項所述的薄膜電晶體的製造方法，其中該結晶程序於攝氏0度至25度下進行。
  8. 如申請專利範圍第1項所述的薄膜電晶體的製造方法，其中該半導體層包括含銦(In)之金屬氧化物半導體材料、含鋅(Zn)之金屬氧化物半導體材料、或是含鎵(Ga)之金屬氧化物半導體材料。
  9. 如申請專利範圍第1項所述的薄膜電晶體的製造方法，更包括：移除該輔助層。
  10. 如申請專利範圍第1項所述的薄膜電晶體的製造方法，其中該形成該閘極以及形成該閘極絕緣層之步驟係先於形成該半導體層、該金屬層以及該輔助層之步驟。
  11. 如申請專利範圍第1項所述的薄膜電晶體的製造方法，其中形成該閘極以及形成該閘極絕緣層之步驟係後於形成該半導體層、該金屬層以及該輔助層之步驟，且形成該閘極之步驟係後於形成該閘極絕緣層之步驟。
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