TWI592067B - Built-in component substrate and manufacturing method thereof - Google Patents

Built-in component substrate and manufacturing method thereof Download PDF

Info

Publication number
TWI592067B
TWI592067B TW102142005A TW102142005A TWI592067B TW I592067 B TWI592067 B TW I592067B TW 102142005 A TW102142005 A TW 102142005A TW 102142005 A TW102142005 A TW 102142005A TW I592067 B TWI592067 B TW I592067B
Authority
TW
Taiwan
Prior art keywords
hole
insulator
component
large diameter
diameter portion
Prior art date
Application number
TW102142005A
Other languages
English (en)
Other versions
TW201448686A (zh
Inventor
Yasuaki Seki
Tomoyuki Nagata
Mitsuaki Toda
Original Assignee
Meiko Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meiko Electronics Co Ltd filed Critical Meiko Electronics Co Ltd
Publication of TW201448686A publication Critical patent/TW201448686A/zh
Application granted granted Critical
Publication of TWI592067B publication Critical patent/TWI592067B/zh

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H01L2224/251—Disposition
    • H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/82005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82009—Pre-treatment of the connector or the bonding area
    • H01L2224/8203—Reshaping, e.g. forming vias
    • H01L2224/82035—Reshaping, e.g. forming vias by heating means
    • H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/83005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H05K1/0222—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09827—Tapered, e.g. tapered hole, via or groove
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1461—Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305—Affixing by adhesive
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Description

內建零件基板及其製造方法
本發明有關於一種內建零件基板及其製造方法。
在專利文獻1中記載了內建零件基板。如專利文獻1所記載的那樣，在應成為導體圖案的導電層上搭載電氣或電子的零件，並將其埋設於預浸材料(Prepreg)等的絕緣層中，藉此而形成內建零件基板。在埋設零件時，使零件通過將該零件部分挖空了的開孔預浸材料與開孔芯材的孔，並在其上部積層按壓未形成有孔的蓋預浸材料(cover Prepreg)。積層後，形成通孔(via)(此通孔為到達零件具有的電極端子的孔)並鍍敷其內部、或者不使用通孔而藉由焊料來謀求端子與導體圖案之間的導通。
此通孔的形成通常是CO2雷射加工的方法。在雷射加工中，根據其狀況而設定功率或脈衝寬度、照射次數等。
另一方面，在想要謀求對於零件的兩面(上下面)都導通的情況下，進一步對於相反側的面形成到達零件端子的通孔。然後，對此通孔施予鍍敷處理來謀求零件端子與導體圖案之間的導通。
【先前技術文獻】 【專利文獻】
【專利文獻1】日本專利第4874305號公報
然而，在零件的上側為蓋預浸材料，此蓋預浸材料從如上所述那樣的積層皺褶或平坦性、或者強度的點來看，未形成用於使零件通過的孔。因此，在形成通孔時，必須貫通蓋預浸材料內具有的玻璃布。在積層時，由於在蓋預浸材料與零件正面之間設置有間隔(space)，在此部分中蓋預浸材料會下垂，伴隨於此，玻璃布也會變得靠近零件正面。在為了貫通此玻璃布的雷射加工中，其控制會有困難，玻璃布與零件之間的距離近，就可能會傷害到零件本身。
在考慮了前述的現有技術，本發明的目的在於提供一種內建零件基板及其製造方法，即使在形成貫通玻璃布的通孔的情況下，在通孔形成加工時，也不會傷害到零件。
為了達成前述目的，本發明提供一種內建零件基板，具備有：含有絕緣樹脂材料的絕緣層、埋設於該絕緣層中的電氣或電子的零件、成為該零件具有的電極的端子、形成於前述絕緣層的表面的導體圖案、電連接該導體圖案與前述端子的導通介層窗，其特徵在於：前述導通介層窗從前述導體圖案朝向前述端子形成有直徑大的大徑部與比此大徑部的直徑小的小徑部，前述大徑部與前述小徑部之間形成有階梯部，前述大徑部貫通前述絕緣層內所配置的片狀的玻璃布而形成。
而且本發明提供一種內建零件基板的製造方法，包括：於具有剛性的支持板上貼附金屬膜，於前述金屬膜上搭載電氣或電子的零件的搭載步驟；使前述零件通過預先形成有讓前述零件貫通的貫通孔的開孔絕緣體的前述貫通孔，並於塞住前述貫通孔的位置上配置內藏片狀的玻璃布的無孔絕緣體的鋪疊(lay-up)步驟；藉由相互按壓並加熱前述開孔絕緣體及前述無孔絕緣體而形成絕緣層，並於前述絕緣層內埋設前述零件的積層步驟；形成從前述絕緣層的外側到達前述零件所具有的端子的通孔的通孔形成步驟；於前述絕緣層的表面形成導體圖案，且在前述通孔內填充用於電連接前述導體圖案與前述端子的導電體而形成導通介層窗的圖案形成步驟，其特徵在於：在前述鋪疊步驟中，前述開孔絕緣體由具有流動性的流動體及具有剛性的剛性體形成，前述流動體的厚度相對於前述開孔絕緣體的厚度為30%~90%，在前述通孔形成步驟中，在形成貫通前述玻璃布的直徑大的大徑通孔後，形成相對於前述大徑通孔的階梯部並且形成到達前述端子且比前述大徑通孔的直徑小的小徑通孔。
較佳的，於前述通孔形成步驟中，以玻璃蝕刻處理去除突出於前述通孔內的前述玻璃布。
較佳的、於前述鋪疊步驟中，使用的前述無孔絕緣體的熔融開始溫度等於或高於前述開孔絕緣體的熔融開始溫度。
較佳的，將前述玻璃布的位置控制在相對於前述開孔絕緣體及前述無孔絕緣體的厚度的40%~90%之間。
較佳的，在前述圖案形成步驟之後，更包括進行外側積層步驟，從前述導體圖案的外側按壓並積層由絕緣樹脂材料構成的外側絕緣體而形成多層基板，在前述外側積層步驟中，施加於每一個由前述大徑部及前述小徑部構成的前述導通介層窗的壓力為50gf以下。
較佳的，在前述圖案形成步驟之後，更包括進行外側積層步驟，從前述導體圖案的外側按壓並積層由絕緣樹脂材料構成的外側絕緣體而形成多層基板，前述大徑部及前述小徑部的厚度相對於前述多層基板的厚度為15%以下。
較佳的，在前述圖案形成步驟之後，更包括進行外側積層步驟，從前述導體圖案的外側按壓並積層由絕緣樹脂材料構成的外側絕緣體而形成多層基板，前述小徑部到達的前述端子的厚度為12μm以上。
根據本發明，在導通介層窗設置大徑部與小徑部，大徑部貫通玻璃布。這樣的大徑部與小徑部，在通孔形成時形成了大徑通孔及小徑通孔。而且，分別可以最佳條件來進行用於貫通玻璃布的開孔加工以及用於到達端子的開孔加工。在這些大徑通孔與小徑通孔之間設置有階梯部，藉此可以防止玻璃布突出於通孔內(特別是小徑通孔內)。因此，在成為導通介層窗時而進行了鍍敷處理時，可以確實地使鍍敷附著在通孔內壁整個表面上。
另一方面，若流動體的厚度相對於開孔絕緣體的厚度為30%~90%的話，在積層步驟中，由於先使流動體進入 貫通孔內，因此可以防止無孔絕緣體下垂至貫通孔內。因此，在積層步驟中，可以防止玻璃布靠近零件，並可以在從零件離開的位置進行貫通玻璃布的加工。於是，在通孔形成加工時，可以防止損傷零件。
而且，以玻璃蝕刻處理去除通孔內突出的玻璃布，藉此可以更確實地使鍍敷附著至通孔內。
而且，使用的無孔絕緣體的熔融開始溫度等於或高於開孔絕緣體的熔融開始溫度，藉此在積層步驟中，可以確實地使開孔絕緣體在最初的貫通孔內流動。因此，可以防止無孔絕緣體下垂。
1‧‧‧支持板
2‧‧‧金屬膜
3‧‧‧接著劑
4‧‧‧電氣或電子的零件
5‧‧‧端子
6‧‧‧開孔絕緣體
7‧‧‧流動體
8‧‧‧剛性體
9‧‧‧貫通孔
10‧‧‧無孔絕緣體
11‧‧‧玻璃布
12‧‧‧絕緣層
13‧‧‧金屬膜
14‧‧‧通孔
14a‧‧‧大徑通孔
14b‧‧‧小徑通孔
15‧‧‧端子
16‧‧‧通孔
17‧‧‧階梯部
18‧‧‧導體圖案
19‧‧‧導電體
20‧‧‧內建零件基板
21‧‧‧導通介層窗
21a‧‧‧大徑部
21b‧‧‧小徑部
22‧‧‧外側絕緣體
23‧‧‧通孔
24‧‧‧導體圖案
25‧‧‧多層基板
26‧‧‧導通介層窗
第1圖為依序說明關於本發明的內建零件基板的製造方法的概略圖。
第2圖為依序說明關於本發明的內建零件基板的製造方法的概略圖。
第3圖為依序說明關於本發明的內建零件基板的製造方法的概略圖。
第4圖為依序說明關於本發明的內建零件基板的製造方法的概略圖。
第5圖為依序說明關於本發明的內建零件基板的製造方法的概略圖。
第6圖為依序說明關於本發明的內建零件基板的製造方法的概略圖。
第7圖為說明通孔形成步驟的詳細圖。
第8圖為說明通孔形成步驟的詳細圖。
第9圖為多層基板的例子的概略圖。
首先，說明關於本發明的內建零件基板的製造方法。
如第1圖及第2圖所示，進行搭載步驟。首先，如第1圖所示，在具有剛性的支持板1上貼附金屬膜2。金屬膜2為在未來能成為導電圖案者。支持板1使用具有依照製程條件所需要程度的剛性者。例如，支持板1由具有剛性的SUS(不鏽鋼)板或鋁板等所形成。若支持板1為SUS板，則金屬膜2可以使銅鍍敷析出而形成；若支持板1為鋁板，則金屬膜2可以貼附銅箔而形成。然後，如第2圖所示，在金屬膜2上以例如分配器(Dispenser)或印刷等來塗佈由絕緣材料構成的接著劑3。在此接著劑3上搭載電氣或電子的零件4。而且，零件4的搭載也可以使用焊料而在金屬膜2上進行。在本例子中，成為零件4中的電極之端子5、端子15形成在兩面。
接著，如第3圖所示，進行鋪疊步驟。首先，準備開孔絕緣體6。此開孔絕緣體6由具有流動性的流動體7及具有剛性的剛性體8重疊而形成。流動體7為預浸材料。剛性體8為所謂的芯材(非包層(UNCLAD)材)，剛性體8是在多層印刷配線板的內部裝入作為芯的金屬板或者形成有圖案的積層板而形成。在這些流動體7、剛性體8中形成讓零件4插通的貫通孔9。此貫通孔9使用鑽頭或起槽機(router)、模 具等來形成。在第3圖中繪示了在2片的流動體7中夾著一片的剛性體8而重疊成的開孔絕緣體6。此開孔絕緣體6的貫通孔9中插通有零件4。然後，以塞住此貫通孔9的方式，進一步在開孔絕緣體6上重疊無孔絕緣體10。此無孔絕緣體10也是預浸材料。由於是預浸材料，在無孔絕緣體10中內藏有片狀的玻璃布11。玻璃布11是以玻璃纖維的絲所織成的布。而且，在無孔絕緣體10的與零件4為相反側的面上配置有另一個金屬膜13。此金屬膜13也為在未來能成為導電圖案者。而且，流動體7的厚度設定成相對於開孔絕緣體6的厚度為30%~90%。
接著，如第4圖所示，進行積層步驟。此積層步驟為藉由相互按壓並加熱開孔絕緣體6及無孔絕緣體10而形成絕緣層12，並於絕緣層12內埋設零件4的步驟。藉由加熱使由預浸材料構成的無孔絕緣體10與流動體7一邊流動一邊形成為一體，而進入貫通孔9內。此時，藉由剛性體8的存在，而可以在按壓時適當的埋設零件4。而且，在上述的鋪疊步驟中，若使用的無孔絕緣體10的熔融開始溫度高於開孔絕緣體6(特別是流動體7)的熔融開始溫度的話，可以確實地使流動體7先在貫通孔9內流動而防止無孔絕緣體10的下垂。支持板1在之後被移除。此時，將玻璃布11的位置控制在相對於開孔絕緣體6及無孔絕緣體10的厚度的40%~90%之間。
在積層步驟結束之後，在無孔絕緣體10內所配置玻璃布11仍然保持平行於金屬膜2或剛性體8。亦即，即使經過加熱熔融，玻璃布11也不會下垂於貫通孔9內。這是因為 在上述鋪疊步驟中，流動體7的厚度相對於開孔絕緣體6的厚度為30%~90%。而且，流動體7的厚度的上限為90%，是因為考慮到剛性體8的厚度至少相對於無孔絕緣體10為10%以上。藉由這樣的設定，在積層步驟中，先使流動體7進入貫通孔9內。藉由進入此貫通孔9內的流動體7來支持無孔絕緣體10，而可以防止含有玻璃布11的無孔絕緣體10下垂。因此，在積層步驟中，可以防止玻璃布11靠近零件4。藉此，在下個通孔形成步驟中，在形成貫通玻璃布11的大徑通孔14a時，變得可以在從零件4離開的位置進行該開孔加工。而且，可以在通孔形成加工時，防止損傷零件。較佳的，玻璃布11只要從零件4離開30μm~70μm以上即可。本發明者在實驗中確認了使流動體7的厚度相對於開孔絕緣體6的厚度為未滿30%時，無孔絕緣體10會下垂，進而玻璃布11會下垂。
接著，如第5圖所示，進行通孔形成步驟。此步驟為形成從絕緣層12的外側到達零件4具有的端子5、端子15的通孔14、通孔16的步驟。到達至接著劑3側的端子5的通孔16是藉由一般的雷射加工來形成。到達與接著劑3為相反側的端子15間的通孔14是由以下方式來形成。首先，如第7圖所示，形成貫通玻璃布11且沒有到達零件4之直徑大的大徑通孔14a。此大徑通孔14a因為不需要那麼好的加工深度的精度，所以可以使用CO2雷射，或者也可以使用UV-YAG或準分子等高頻率雷射。舉例來說，在使用UV-YAG的情況下，其是以光束模式為高斯分布、功率為2.6W、照射次數為3照射的條件下進行。大徑通孔14a的深度例如是50μm~100μm。
在形成大徑通孔14a之後，在大徑通孔14a內突出有玻璃布11的情況下，較佳是藉由玻璃蝕刻處理將其去除。藉此，在後續步驟中於通孔14內進行鍍敷處理時，可以確實地使鍍敷附著至通孔14內。
接著，如第8圖所示，形成比大徑通孔14a直徑小的小徑通孔14b。在此小徑通孔14b形成時，為了不損傷零件4較佳是使用精度高的高頻率雷射來進行。舉例來說，在使用UV-YAG來進行的情況下，其是以光束模式為頂帽(Top hat)型、功率為0.1W~0.4W、照射次數為5照射~10照射的條件下進行。此外，在大徑通孔14a與小徑通孔14b之間的內壁***形成有階梯部17。藉由在這樣的大徑通孔14a與小徑通孔14b之間設置階梯部17，例如即使形成大徑通孔14a而使玻璃布11在階梯部17的面上，也可以防止玻璃布11突出通孔14內(特別是小徑通孔14b內)。因此，在後續步驟中對通孔14內進行鍍敷處理時，可以確實地使鍍敷附著在通孔14的內壁整個表面上。大徑通孔14a的孔徑例如是80μm~150μm；小徑通孔14b的孔徑在小於大徑通孔14a的孔徑的範圍內，其例如是50μm~100μm。
在這樣的本發明中，在企圖對與零件4的搭載側之面的相反側之面進行導通的情況下，此時因為通孔14是以***有階梯部17的大徑通孔14a與小徑通孔14b來形成。因此，用於貫通玻璃布11的開孔加工(大徑通孔14a的開孔加工)以及用於到達端子15的開孔加工(小徑通孔14b的開孔加工)能夠分別以最適當的條件來形成。
接著，如第6圖所示，進行圖案形成步驟。此步驟是在通孔14、通孔16內填充導電體19，並在絕緣層12的表面形成導體圖案18，而藉由導電體19來電連接端子5、端子15與導體圖案18的步驟。具體而言，對應需要對通孔14、通孔16施行去膠渣(Desmear)或半蝕刻(half etching)處理、並施行化學鍍銅或電鍍銅等的鍍敷處理，而在通孔14、通孔16內使鍍敷析出並填充導電體19。然後，藉由對配置於絕緣層12的兩面的金屬膜2、13施行蝕刻處理，而形成導體圖案18。
如以上方式所製造的內建零件基板20具備有絕緣層12、零件4、導體圖案18、導通介層窗21。絕緣層12包含作為絕緣樹脂材料的預浸材料(開孔絕緣體6內的流動體、無孔絕緣體10)。零件4為電氣或電子的零件，並埋設於絕緣層12。而且，零件4並不侷限於被動零件、主動零件。在此零件4中形成有成為電極的端子5、端子15。導體圖案18作為電路圖案而形成在絕緣層12的表面。導通介層窗21電連接導體圖案18與端子5、端子15。特別是，與零件4的搭載面側的相反側的端子15連接的導通介層窗21由導體圖案18朝向端子15形成有直徑大的大徑部21a與比大徑部21a的直徑小的小徑部21b。大徑部21a貫通絕緣層12內所配置的片狀的玻璃布11而形成。而且，在大徑部21a與小徑部21b之間形成有階梯部17。
如第9圖所示，圖案形成步驟之後，更進一步進行從外側積層外側絕緣體22的外側積層步驟，而能夠形成所 謂的多層基板25。在此種情況下，在積層了外側絕緣體22之後，形成通孔23來謀求與外側絕緣體22的表面上所形成的導體圖案24之間的導通。導通可藉由對在導體圖案18與導體圖案24之間所形成的通孔23施行鍍敷處理，而形成導通介層窗26來實現。此導通的實施方法與前述的例子相同。外側絕緣體22使用與前述的無孔絕緣體10相同的預浸材料。
在此，在外側積層步驟中，施加於每一個由大徑部21a與小徑部21b構成的導通介層窗21的壓力較佳為50gf以下。而且，大徑部21a及小徑部21b的厚度相對於多層基板25的厚度較佳為15%以下。而且，小徑通孔14b到達的端子15的厚度較佳為12μm以上(多層基板的厚度400μm)。
藉由如此設定，在成為多層基板25時的外側積層步驟中，可以防止在端子15產生裂痕(crack)。本發明者確認了：藉由縮小施加於由大徑部21a及小徑部21b構成的導通介層窗21的壓力可以防止此種裂痕。因此，考慮了降低積層時的壓力、提高通孔密度、增大通孔直徑、緩和未填充有導電體19的通孔的應力。而且，也考慮了縮小通孔14的厚度來謀求應力的分散。此外，也考慮了增厚端子15的電極厚度來分散應力。
3‧‧‧接著劑
4‧‧‧電氣或電子的零件
5‧‧‧端子
11‧‧‧玻璃布
12‧‧‧絕緣層
15‧‧‧端子
17‧‧‧階梯部
18‧‧‧導體圖案
19‧‧‧導電體
20‧‧‧內建零件基板
21‧‧‧導通介層窗
21a‧‧‧大徑部
21b‧‧‧小徑部

Claims (8)

  1. 一種內建零件基板，包括：絕緣層，包含絕緣樹脂材料；電氣或電子的零件，埋設於前述絕緣層中；端子，成為前述零件具有的電極；導體圖案，形成於前述絕緣層的表面；以及導通介層窗，電連接前述導體圖案與前述端子，其特徵在於：前述導通介層窗從前述導體圖案朝向前述端子形成有直徑大的大徑部與比前述大徑部的直徑小的小徑部，在前述大徑部與前述小徑部之間形成有階梯部，前述大徑部貫通前述絕緣層內所配置的片狀的玻璃布而形成，其中前述玻璃布與前述零件的距離等於或大於前述階梯部與前述零件的距離。
  2. 一種內建零件基板的製造方法，包括：搭載步驟，於具有剛性的支持板上貼附金屬膜，於前述金屬膜上搭載電氣或電子的零件；鋪疊(lay-up)步驟，使前述零件通過預先形成有讓前述零件貫通的貫通孔的開孔絕緣體的前述貫通孔，並於塞住前述貫通孔的位置上配置內藏片狀的玻璃布的無孔絕緣體；積層步驟，藉由相互按壓並加熱前述開孔絕緣體及前述無孔絕緣體而形成絕緣層，並於前述絕緣層內埋設前述零件；通孔形成步驟，形成從前述絕緣層的外側到達前述零件所 具有的端子的通孔；圖案形成步驟，於前述絕緣層的表面形成導體圖案，且在前述通孔內填充用於電連接前述導體圖案與前述端子的導電體而形成由大徑部及小徑部構成的導通介層窗，其特徵在於：在前述鋪疊步驟中，前述開孔絕緣體由具有流動性的流動體及具有剛性的剛性體形成，前述流動體的厚度相對於前述開孔絕緣體的厚度為30%~90%，在前述通孔形成步驟中，在形成貫通前述玻璃布的直徑大的大徑通孔後，形成相對於前述大徑通孔的階梯部並且形成到達前述端子且比前述大徑通孔的直徑小的小徑通孔。
  3. 如申請專利範圍第2項所述的內建零件基板的製造方法，其中於前述通孔形成步驟中，以玻璃蝕刻處理去除前述通孔內突出的前述玻璃布。
  4. 如申請專利範圍第2項所述的內建零件基板的製造方法，其中於前述鋪疊步驟中，使用的前述無孔絕緣體的熔融開始溫度等於或高於前述開孔絕緣體的熔融開始溫度。
  5. 如申請專利範圍第2項所述的內建零件基板的製造方法，其中將前述玻璃布的位置控制在相對於前述開孔絕緣體及前述無孔絕緣體的厚度的40%~90%之間。
  6. 如申請專利範圍第2項所述的內建零件基板的製造方法，其中在前述圖案形成步驟之後，更包括進行外側積層步驟，從前述導體圖案的外側按壓並積層由絕緣樹脂材料構成的外側絕緣體而形成多層基板， 在前述外側積層步驟中，施加於每一個由前述大徑部及前述小徑部構成的前述導通介層窗的壓力為50gf以下。
  7. 如申請專利範圍第2項所述的內建零件基板的製造方法，其中在前述圖案形成步驟之後，更包括進行外側積層步驟，從前述導體圖案的外側按壓並積層由絕緣樹脂材料構成的外側絕緣體而形成多層基板，前述大徑部及前述小徑部的厚度相對於前述多層基板的厚度為15%以下。
  8. 如申請專利範圍第2項所述的內建零件基板的製造方法，其中在前述圖案形成步驟之後，更包括進行外側積層步驟，從前述導體圖案的外側按壓並積層由絕緣樹脂材料構成的外側絕緣體而形成多層基板，前述小徑部到達的前述端子的厚度為12μm以上。
TW102142005A 2013-01-18 2013-11-19 Built-in component substrate and manufacturing method thereof TWI592067B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2013/050984 WO2014112108A1 (ja) 2013-01-18 2013-01-18 部品内蔵基板及びその製造方法

Publications (2)

Publication Number Publication Date
TW201448686A TW201448686A (zh) 2014-12-16
TWI592067B true TWI592067B (zh) 2017-07-11

Family

ID=51209228

Family Applications (1)

Application Number Title Priority Date Filing Date
TW102142005A TWI592067B (zh) 2013-01-18 2013-11-19 Built-in component substrate and manufacturing method thereof

Country Status (7)

Country Link
US (1) US9756732B2 (zh)
EP (1) EP2947975A4 (zh)
JP (1) JP6262153B2 (zh)
KR (1) KR101995276B1 (zh)
CN (1) CN104938040B (zh)
TW (1) TWI592067B (zh)
WO (1) WO2014112108A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150366081A1 (en) * 2014-06-15 2015-12-17 Unimicron Technology Corp. Manufacturing method for circuit structure embedded with electronic device
KR102268388B1 (ko) * 2014-08-11 2021-06-23 삼성전기주식회사 인쇄회로기판 및 그 제조방법
JP2016058472A (ja) * 2014-09-08 2016-04-21 イビデン株式会社 電子部品内蔵配線板及びその製造方法
CN107295746B (zh) 2016-03-31 2021-06-15 奥特斯(中国)有限公司 器件载体及其制造方法
EP3481162B1 (en) * 2017-11-06 2023-09-06 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Component carrier with two component carrier portions and a component being embedded in a blind opening of one of the component carrier portions
TWI706705B (zh) * 2019-06-21 2020-10-01 唐虞企業股份有限公司 電路板及其製造方法
WO2021146894A1 (zh) * 2020-01-21 2021-07-29 鹏鼎控股(深圳)股份有限公司 内埋电子元件的电路板及制作方法
US20240251507A1 (en) * 2023-01-24 2024-07-25 Simmonds Precision Products, Inc. Electrical circuit board assemblies

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5435121B2 (zh) 1971-12-29 1979-10-31
JP2006196840A (ja) 2005-01-17 2006-07-27 Denso Corp 配線基板およびその製造方法
JP2007088009A (ja) 2005-09-20 2007-04-05 Cmk Corp 電子部品の埋め込み方法及び電子部品内蔵プリント配線板
JP4826248B2 (ja) * 2005-12-19 2011-11-30 Ｔｄｋ株式会社 Ｉｃ内蔵基板の製造方法
KR20140033245A (ko) 2006-05-24 2014-03-17 다이니폰 인사츠 가부시키가이샤 부품 내장 배선판, 부품 내장 배선판의 제조 방법
CN101442887B (zh) * 2007-11-22 2013-03-20 味之素株式会社 多层印刷线路板的制造方法及多层印刷线路板
US8024858B2 (en) * 2008-02-14 2011-09-27 Ibiden Co., Ltd. Method of manufacturing printed wiring board with built-in electronic component
JP5284147B2 (ja) 2008-03-13 2013-09-11 日本特殊陶業株式会社 多層配線基板
JP4874305B2 (ja) 2008-07-22 2012-02-15 株式会社メイコー 電気・電子部品内蔵回路基板とその製造方法
WO2010010911A1 (ja) * 2008-07-23 2010-01-28 日本電気株式会社 半導体装置及びその製造方法
JPWO2010024233A1 (ja) * 2008-08-27 2012-01-26 日本電気株式会社 機能素子を内蔵可能な配線基板及びその製造方法
JP2010128934A (ja) 2008-11-28 2010-06-10 Kyoei Sangyo Kk Ｒｆｉｄインレット、ｒｆｉｄタグ、ｒｆｉｄタグを製造する方法、ｒｆｉｄタグを含むプリント基板、および、プリント基板にｒｆｉｄタグを埋め込む方法
TWI392425B (zh) 2009-08-25 2013-04-01 Unimicron Technology Corp 內埋式線路板及其製造方法
EP2624672A4 (en) 2010-10-01 2014-11-26 Meiko Electronics Co Ltd METHOD FOR PRODUCING A SUBSTRATE WITH INTEGRATED COMPONENT AND SUBSTRATE PRODUCED BY THIS PROCESS WITH INTEGRATED COMPONENT
JP5855905B2 (ja) 2010-12-16 2016-02-09 日本特殊陶業株式会社 多層配線基板及びその製造方法
KR101181048B1 (ko) 2010-12-27 2012-09-07 엘지이노텍 주식회사 인쇄회로기판의 제조 방법
JP2012209340A (ja) 2011-03-29 2012-10-25 Nec Corp 多層基板及び多層基板の製造方法

Also Published As

Publication number Publication date
US9756732B2 (en) 2017-09-05
KR101995276B1 (ko) 2019-07-02
WO2014112108A1 (ja) 2014-07-24
KR20150110522A (ko) 2015-10-02
JPWO2014112108A1 (ja) 2017-01-19
EP2947975A4 (en) 2016-08-24
TW201448686A (zh) 2014-12-16
CN104938040B (zh) 2017-10-24
CN104938040A (zh) 2015-09-23
JP6262153B2 (ja) 2018-01-17
EP2947975A1 (en) 2015-11-25
US20150327369A1 (en) 2015-11-12

Similar Documents

Publication Publication Date Title
TWI592067B (zh) Built-in component substrate and manufacturing method thereof
JP5161617B2 (ja) フレキシブル回路基板、及びその製造方法
CN104717839B (zh) 厚铜电路板及其制作方法
JP5698377B2 (ja) 部品内蔵基板の製造方法及びこの方法を用いて製造した部品内蔵基板
US20140166355A1 (en) Method of manufacturing printed circuit board
JP2010232249A (ja) 多層プリント配線板とその製造方法
KR102488164B1 (ko) 프로파일된 도전성 층을 갖는 인쇄 회로 기판 및 그 제조 방법
TW201340806A (zh) 電路板的製作方法
CN100594758C (zh) 多层电路板及其制造方法
CN103582321A (zh) 多层线路板及其制作方法
JP6058321B2 (ja) 配線基板の製造方法
RU2396738C1 (ru) Способ изготовления печатных плат
JP2014068047A (ja) 多層プリント配線板の製造方法
KR20070000644A (ko) 소자 내장 인쇄회로기판 및 그 제조방법
JP2010028028A (ja) 多層プリント配線板とその製造方法
JP4541187B2 (ja) 膜素子内蔵プリント配線板の製造方法、膜素子内蔵プリント配線板
JP7057792B2 (ja) 積層体及びその製造方法
US20240196542A1 (en) Electrical interconnect structure with circuit bearing dielectric layers and resultant dielectric spacing control and circuit pitch reduction
JP5303532B2 (ja) プリント配線板、その製造方法、多層プリント配線板、及びその製造方法
KR20160139829A (ko) 다층 ｆｐｃｂ 및 그 제조 방법
JP3593957B2 (ja) 多層配線板およびその製造方法
KR20130104507A (ko) 연성인쇄회로기판 및 그의 제조 방법
JP6320788B2 (ja) フレキシブルプリント基板の製造方法およびフレキシブルプリント基板の製造に用いられる中間生成物
KR20140014867A (ko) 인쇄회로기판의 제조 방법
WO2014041628A1 (ja) 部品内蔵基板及びその製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees