JP5284147B2 - 多層配線基板 - Google Patents
多層配線基板 Download PDFInfo
- Publication number
- JP5284147B2 JP5284147B2 JP2009059006A JP2009059006A JP5284147B2 JP 5284147 B2 JP5284147 B2 JP 5284147B2 JP 2009059006 A JP2009059006 A JP 2009059006A JP 2009059006 A JP2009059006 A JP 2009059006A JP 5284147 B2 JP5284147 B2 JP 5284147B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- insulating layer
- multilayer wiring
- conductor
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
- H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/421—Blind plated via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09563—Metal filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0147—Carriers and holders
- H05K2203/0152—Temporary metallic carrier, e.g. for transferring material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本発明は上記の課題に鑑みてなされたものであり、その目的は、ビアの密着強度を高めることができ、製品歩留まりを向上することができる多層配線基板を提供することにある。
なお、本発明のコアを有さない多層配線基板とは、「主に同一の層間絶縁層を主体として構成されている多層配線基板」や「同一方向に拡径したビアのみにより各導体層を接続している多層配線基板」を挙げることができる。
図1に示されるように、コアレス配線基板10は、コア基板を有さず、エポキシ樹脂からなる4層の樹脂絶縁層(層間絶縁層)21,22,23,24と銅からなる導体層26とを交互に積層して多層化した配線積層部20(積層構造体)を有している。コアレス配線基板10において、第4層の樹脂絶縁層24の表面(上面)には端子パッド27が設けられている。なお、図1は、コアレス配線基板10の一部を示す断面図であり、コアレス配線基板10の上面には、複数の端子パッド27が例えばアレイ状に配置されている(図2参照)。
20…積層構造体としての配線積層部
21〜24…層間絶縁層としての樹脂絶縁層
25…素子搭載領域
26…導体層
32…ビア穴
32A…ビア穴の内壁面
33…フィルドビア導体
35…高分子材料としてのエポキシ樹脂
36…繊維材(無機繊維)としてのガラスクロス
36A…ガラスクロスの突出端
39…段差
64…ビア底面
θ1,θ2…傾斜角度
Claims (5)
- コア基板を有さず、導体層及び層間絶縁層を交互に積層して多層化した積層構造体を有し、その主面上に半導体集積回路素子を搭載するための素子搭載領域が設定された多層配線基板において、
前記層間絶縁層には逆円錐台形状であってその内壁面に段差を有しかつ同一方向に拡径した複数のビア穴が貫通形成され、
前記複数のビア穴内には前記導体層間を電気的に接続するフィルドビア導体がそれぞれ形成され、
複数の前記フィルドビア導体は、積層構造体の積層方向に、前記導体層を介して積み重なった状態でそれぞれ形成され、
最外層の絶縁層は、積み重なった状態の複数の前記フィルドビア導体を覆っている
ことを特徴とする多層配線基板。 - 前記層間絶縁層は高分子材料中に繊維材を含むものであることを特徴とする請求項1に記載の多層配線基板。
- 前記段差は、前記層間絶縁層において前記繊維材が存在する深さ位置に対応して形成されていることを特徴とする請求項2に記載の多層配線基板。
- 前記最外層の絶縁層には、前記フィルドビア導体が形成された位置から平面視でずれた位置に導体層の一部を露出してパッドとする開口部が形成されていることを特徴とする請求項1乃至3のいずれか1項に記載の多層配線基板。
- 前記段差は、前記繊維材の突出端が存在する深さ位置に対応して形成されるとともに、前記段差を境界として前記内壁面をビア開口側領域とビア底部側領域とに区分した場合において、ビア底面を基準とした前記ビア開口側領域の傾斜角度のほうが、ビア底面を基準とした前記ビア底部側領域の傾斜角度よりも小さいことを特徴とする請求項2に記載の多層配線基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009059006A JP5284147B2 (ja) | 2008-03-13 | 2009-03-12 | 多層配線基板 |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008064987 | 2008-03-13 | ||
JP2008064987 | 2008-03-13 | ||
JP2009059006A JP5284147B2 (ja) | 2008-03-13 | 2009-03-12 | 多層配線基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009246358A JP2009246358A (ja) | 2009-10-22 |
JP5284147B2 true JP5284147B2 (ja) | 2013-09-11 |
Family
ID=41061772
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009059006A Expired - Fee Related JP5284147B2 (ja) | 2008-03-13 | 2009-03-12 | 多層配線基板 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8093503B2 (ja) |
JP (1) | JP5284147B2 (ja) |
TW (1) | TWI415541B (ja) |
Families Citing this family (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9991311B2 (en) | 2008-12-02 | 2018-06-05 | Arizona Board Of Regents On Behalf Of Arizona State University | Dual active layer semiconductor device and method of manufacturing the same |
US9721825B2 (en) | 2008-12-02 | 2017-08-01 | Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Method of providing a flexible semiconductor device and flexible semiconductor device thereof |
US9601530B2 (en) | 2008-12-02 | 2017-03-21 | Arizona Board Of Regents, A Body Corporated Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Dual active layer semiconductor device and method of manufacturing the same |
WO2010138811A2 (en) | 2009-05-29 | 2010-12-02 | Arizona Board Of Regents, For And On Behalf Of Arizona State University | Method of providing a flexible semiconductor device at high temperatures and flexible semiconductor device thereof |
TWI400025B (zh) * | 2009-12-29 | 2013-06-21 | Subtron Technology Co Ltd | 線路基板及其製作方法 |
JP5638269B2 (ja) * | 2010-03-26 | 2014-12-10 | 日本特殊陶業株式会社 | 多層配線基板 |
WO2012021196A2 (en) * | 2010-05-21 | 2012-02-16 | Arizona Board Of Regents, For And On Behalf Of Arizona State University | Method for manufacturing electronic devices and electronic devices thereof |
WO2012021197A2 (en) * | 2010-05-21 | 2012-02-16 | Arizona Board Of Regents, For And On Behalf Of Arizona State University | Method of manufacturing electronic devices on both sides of a carrier substrate and electronic devices thereof |
EP2479337B1 (en) * | 2011-01-24 | 2013-08-07 | Electrolux Home Products Corporation N.V. | Household appliance for drying objects |
JP5865771B2 (ja) * | 2012-04-26 | 2016-02-17 | 日本特殊陶業株式会社 | 多層配線基板 |
JP2013229526A (ja) * | 2012-04-26 | 2013-11-07 | Ngk Spark Plug Co Ltd | 多層配線基板及びその製造方法 |
CN104938040B (zh) * | 2013-01-18 | 2017-10-24 | 名幸电子有限公司 | 内置有零件的基板及其制造方法 |
JP2015115335A (ja) * | 2013-12-09 | 2015-06-22 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
WO2017034644A2 (en) | 2015-06-09 | 2017-03-02 | ARIZONA BOARD OF REGENTS a body corporate for THE STATE OF ARIZONA for and on behalf of ARIZONA STATE UNIVERSITY | Method of providing an electronic device and electronic device thereof |
US10381224B2 (en) | 2014-01-23 | 2019-08-13 | Arizona Board Of Regents On Behalf Of Arizona State University | Method of providing an electronic device and electronic device thereof |
WO2015156891A2 (en) | 2014-01-23 | 2015-10-15 | Arizona Board Of Regents, Acting For And On Behalf Of Arizona State University | Method of providing a flexible semiconductor device and flexible semiconductor device thereof |
CN106663640B (zh) | 2014-05-13 | 2020-01-07 | 代表亚利桑那大学的亚利桑那校董会 | 提供电子器件的方法及其电子器件 |
JP2016072320A (ja) * | 2014-09-29 | 2016-05-09 | 株式会社 大昌電子 | プリント配線板およびその製造方法 |
US9741742B2 (en) | 2014-12-22 | 2017-08-22 | Arizona Board Of Regents, A Body Corporate Of The State Of Arizona, Acting For And On Behalf Of Arizona State University | Deformable electronic device and methods of providing and using deformable electronic device |
US10446582B2 (en) | 2014-12-22 | 2019-10-15 | Arizona Board Of Regents On Behalf Of Arizona State University | Method of providing an imaging system and imaging system thereof |
KR102412612B1 (ko) * | 2015-08-28 | 2022-06-23 | 삼성전자주식회사 | 패키지 기판 및 프리프레그 |
US9899239B2 (en) * | 2015-11-06 | 2018-02-20 | Apple Inc. | Carrier ultra thin substrate |
CN108172542B (zh) * | 2017-12-28 | 2019-11-08 | 广州兴森快捷电路科技有限公司 | 无芯板制作方法及其制造构件、支撑载体及其制作方法 |
JP7221601B2 (ja) * | 2018-06-11 | 2023-02-14 | 新光電気工業株式会社 | 配線基板、配線基板の製造方法 |
JP7397718B2 (ja) | 2020-02-28 | 2023-12-13 | 京セラ株式会社 | 印刷配線板及び印刷配線板の製造方法 |
US11785707B2 (en) * | 2021-01-21 | 2023-10-10 | Unimicron Technology Corp. | Circuit board and manufacturing method thereof and electronic device |
Family Cites Families (11)
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JP2805242B2 (ja) * | 1990-06-02 | 1998-09-30 | 日立精工株式会社 | プリント基板の穴明け加工方法 |
US5837427A (en) * | 1996-04-30 | 1998-11-17 | Samsung Electro-Mechanics Co Co., Ltd. | Method for manufacturing build-up multi-layer printed circuit board |
JP3635219B2 (ja) * | 1999-03-11 | 2005-04-06 | 新光電気工業株式会社 | 半導体装置用多層基板及びその製造方法 |
JP2001257474A (ja) * | 2000-03-10 | 2001-09-21 | Ngk Spark Plug Co Ltd | 配線基板の製造方法 |
JP2002361791A (ja) * | 2001-06-13 | 2002-12-18 | Hitachi Metals Ltd | 積層箔及び配線板、並びに配線板の製造方法 |
JP3699383B2 (ja) * | 2001-10-29 | 2005-09-28 | 日本特殊陶業株式会社 | 配線基板の製造方法 |
US20040089470A1 (en) | 2002-11-12 | 2004-05-13 | Nec Corporation | Printed circuit board, semiconductor package, base insulating film, and manufacturing method for interconnect substrate |
JP3841079B2 (ja) * | 2002-11-12 | 2006-11-01 | 日本電気株式会社 | 配線基板、半導体パッケージ、基体絶縁膜及び配線基板の製造方法 |
TWI347151B (en) * | 2004-03-19 | 2011-08-11 | Panasonic Corp | Flexible substrate having interlaminar junctions, and process for producing the same |
JP2006294725A (ja) * | 2005-04-07 | 2006-10-26 | Fujikura Ltd | 配線基板、多層配線基板およびそれらの製造方法 |
JP2007201030A (ja) * | 2006-01-25 | 2007-08-09 | Fujitsu Ltd | 電子デバイス |
-
2009
- 2009-03-12 JP JP2009059006A patent/JP5284147B2/ja not_active Expired - Fee Related
- 2009-03-13 TW TW098108182A patent/TWI415541B/zh not_active IP Right Cessation
- 2009-03-13 US US12/403,525 patent/US8093503B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
TW200945985A (en) | 2009-11-01 |
TWI415541B (zh) | 2013-11-11 |
JP2009246358A (ja) | 2009-10-22 |
US8093503B2 (en) | 2012-01-10 |
US20090229874A1 (en) | 2009-09-17 |
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