TWI591780B - 使用微影圖案化聚合物基板之無載體矽中介層 - Google Patents

使用微影圖案化聚合物基板之無載體矽中介層 Download PDF

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TWI591780B
TWI591780B TW103141147A TW103141147A TWI591780B TW I591780 B TWI591780 B TW I591780B TW 103141147 A TW103141147 A TW 103141147A TW 103141147 A TW103141147 A TW 103141147A TW I591780 B TWI591780 B TW I591780B
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component
conductive
insulating structures
openings
insulating
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TW103141147A
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TW201530721A (zh
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安德烈 曹
麥可 紐曼
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英凡薩斯公司
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Description

使用微影圖案化聚合物基板之無載體矽中介層
本發明係關於一種微電子裝置的封裝，特別是一種半導體裝置的封裝。
微電子裝置通常包含半導體材料之薄板，例如矽或砷化鎵，通常被稱為晶粒或半導體晶片。半導體晶片通常被提供作為個別的預封裝單元。在一些單元的設計中，半導體晶片係安裝到基板或晶片載體上，接著再安裝到電路板上，例如印刷電路板。
主動電路係設置在半導體晶片之第一表面(例如前表面)上。在相同的表面上，提供具有複數個連接墊的晶片以電性連接主動電路。連接墊係通常圍繞晶粒之複數個邊緣或針對許多記憶體裝置在晶粒中心上以規則的排列方式設置。連接墊通常係由導電金屬製造，例如銅或鋁，而其厚度大約為0.5微米(μm)。連接墊可包含單層或多層金屬。複數個連接墊之大小將隨著裝置類型而改變，但在一側面上所量測到的大小通常介於10微 米到100微米之間。
在複數個微電子元件之間，例如與另一半導體晶片相連接的至少一未封裝或封裝的半導體晶片，或在至少一未封裝或封裝的半導體晶片以及其他複數個裝置之間，例如其上具有複數個被動電路元件的整合被動元件晶片(“IPOC”)、離散被動裝置(例如但不限制電容器、電阻器、電感器或其相同的組合物)，中介層可用以提供複數個電子連接處。中介層可耦接此類晶片或具有其他結構(例如電路板)的複數個晶片。
在晶片的任何實體配置上，大小係為重要的考量。隨著可攜式電子裝置的快速發展，對於晶片的更緊密的實體排列有更強烈的需求。僅以舉例的方式，通常被稱為“智慧型手機”的裝置與高解析度裝置以及相關的影像處理晶片一起，將蜂窩式電話之功能與強大的資料處理器、記憶體以及輔助裝置進行整合，例如全球定位系統接收器、電子照相機以及區域網路連接器。此類裝置可提供的功能，例如完整的網路連接、包含完整解析度視頻、導航、電子銀行以及更多口袋大小的裝置的娛樂。複雜可攜式裝置需要將複數個晶片組裝到一個小空間內。此外，一些晶片具有許多輸入以及輸出連接處，通常被稱為“I/O”。這些“I/O”必須與其他晶片之“I/O”互連。此互連應為短的以及應具有低阻抗以最小化訊號傳播延遲。形成互連的裝置不應大幅度增加組件的尺寸。相似的需求亦出現在其他的應用中，例如通常使用於網路搜尋引擎的資料伺服器。例如，在複雜晶片之間，提供複數個短、低阻抗互連的結構可增加搜尋引擎之頻寬以及減少其功率消耗。
儘管中介層結構以及構造物有上述優點，但針對中介層以 及可能從製程產生的結構，仍可對製程做更進一步的改善。
本案為一種具有對立之第一側面以及第二側面的裝置，其包含第一元件以及第二元件。第一元件係具有與裝置之第一側面重合或相鄰的第一表面以及與第一表面相反的一第二表面。第一元件包含具有低於10ppm/℃的熱膨脹係數的第一材料。
第二元件係耦接到第一元件之第二表面，並具有與此裝置之第二側面重合或相鄰的一表面。第二元件包含由不同於第一材料的至少一第二材料所組成的複數個電絕緣結構。每一電絕緣結構係至少部分地藉由從第二元件之表面朝向該第一元件進行延伸的至少一間隙與另一電絕緣結構相分離。此裝置更包含位於第一側面上的複數個導電元件以及位於第二側面上的複數個端部。複數個端部可用以與此裝置外部的另一裝置的複數個相對應的接觸部相連接。導電結構係將複數個導電元件電性耦接複數個端部，此導電結構包含穿過至少一絕緣結構朝向第一元件進行延伸的至少一導電互連線。
如上所述，在一種製造裝置之方法中，複數個端部以及導電結構可穿過複數個絕緣結構進行延伸而形成。
至少一間隙可用以降低在第二元件之複數個端部以及與其相連接之另一裝置之間的連接處的應力。在一具體示例中，複數個絕緣結構可定義複數個間隙，複數個間隙係定義藉由複數個間隙與另一島狀物完全分離的複數個島狀物，每一島狀物包含至少一絕緣結構。通常，複數個 間隙係填充絕緣材料，有些情況下，其可以為可撓性材料、彈性物、矽、旋塗玻璃材料，或在一具體示例中，其可以為矽膠類材料(PDMS)。
在一具體示例中，此裝置可更包含複數個連接器元件，其包含第二材料。複數個連接器元件可將複數個絕緣結構與另一絕緣結構鄰接，連接器元件係在複數個絕緣結構之複數個相鄰的絕緣結構之複數個邊緣之間進行延伸，並具有不同於複數個相鄰的絕緣結構的截面積。
如上所述，至少一島狀物在第一方向上具有一實質上方形截面。在圖式中，複數個島狀物或複數個間隙係設置在柵格圖案內。
如上所述，至少二個別的截面具有與在裝置之表面上的另一截面共面的複數個表面。
如上所述，第二元件包含一連續部分，其包含複數個與連續部分整合一體的複數個絕緣結構，絕緣結構以及間隙係一起定義一棋盤圖案。
100‧‧‧裝置
102‧‧‧端部
104‧‧‧接合元件
106‧‧‧基板
110‧‧‧微電子元件
112‧‧‧第二微電子元件
114‧‧‧導電元件
124‧‧‧接觸點
125‧‧‧組件
134‧‧‧接觸部
140‧‧‧第一側面
142‧‧‧第二側面
148‧‧‧低CTE元件
149‧‧‧表面
150‧‧‧第一元件
151‧‧‧低CTE層
152‧‧‧第一表面
153‧‧‧配線層
154‧‧‧第二表面
155‧‧‧介電層
156‧‧‧厚度
160‧‧‧第二元件
161‧‧‧厚度
162‧‧‧表面
163‧‧‧開孔
164‧‧‧開孔
165‧‧‧孔隙
166‧‧‧導電互連線
168‧‧‧介電材料
170‧‧‧孔洞
172‧‧‧導電墊
180‧‧‧第一方向
202‧‧‧表面
300‧‧‧系統
301‧‧‧殼體
302‧‧‧電路板
304‧‧‧導線
306‧‧‧結構
308‧‧‧裝置
310‧‧‧螢幕
311‧‧‧透鏡
404‧‧‧接合元件
460‧‧‧第二元件
470‧‧‧孔洞
480‧‧‧絕緣結構
481‧‧‧邊緣
482‧‧‧連接器元件
490‧‧‧間隙
491‧‧‧絕緣材料
492‧‧‧第二方向
494‧‧‧第一方向
560‧‧‧第二元件
580‧‧‧絕緣結構
590‧‧‧間隙
H1‧‧‧高
H2‧‧‧中點
W1‧‧‧尺寸
W2‧‧‧尺寸
本發明之上述及其他特徵及優勢將藉由參照附圖詳細說明其例示性實施例而變得更顯而易知，其中：第1圖為本案較佳實施例之裝置剖面圖；第2A圖為本案較佳實施例之包含一裝置的微電子組件之剖面圖；第2B圖為本案較佳實施例之至少一態樣之第二元件之剖面圖；第2C圖為本案較佳實施例之至少一態樣之第二元件之底面圖；第3A圖為本案較佳實施例之定義在裝置內的穿導孔以及開孔之深寬 比的相對高度以及寬度之剖面圖；第3B圖為第3A圖之3B-3B線，在橫向於穿導孔以及開孔的長度的垂直方向的水平方向上的穿導孔或開孔的最低尺寸之平面圖；第3C圖為本案較佳實施例之在穿導孔以及開孔的長度H1的中點H1/2上所決定的穿導孔以及開孔的一尺寸之另一剖面圖；第4圖為本案較佳實施例之第一實施例之製造方法中的一階段；第5圖為本案較佳實施例之第一實施例之製造方法中的一階段；第6圖為本案較佳實施例之第一實施例之製造方法中的一階段；第7圖為本案較佳實施例之第一實施例之製造方法中的一階段；第8圖為本案較佳實施例之第一實施例之製造方法中的一階段；第9圖為本案較佳實施例之第一實施例之製造方法中的一階段；第10圖為本案較佳實施例之第二實施例之製造方法中的一階段；第11圖為本案較佳實施例之第二實施例之製造方法中的一階段；第12圖為本案較佳實施例之第二實施例之製造方法中的一階段；第13圖為本案較佳實施例之第二實施例之製造方法中的一階段；第14圖為本案較佳實施例之第二實施例之製造方法中的一階段；第15圖為本案較佳實施例之第二實施例之製造方法中的一階段；第16圖為本案較佳實施例之第二實施例之製造方法中的一階段；第17圖為本案較佳實施例之第二實施例之製造方法中的一階段；第18圖為本案較佳實施例之第二實施例之製造方法中的一階段；第19圖為本案較佳實施例之實施例之系統。
本文中，詞彙“與/或”包含一或多個相關條列項目之任何或所有組合。當“至少其一”之敘述前置於一元件清單前時，係修飾整個清單元件而非修飾清單中之個別元件。
第1A圖、第2A圖至第2C圖以及第3A至第3C圖為本案較佳實施例之裝置100。如第1圖所示，裝置100可以為中介層(interposer)。如圖所示，裝置或中介層可包含複數個主動、被動電路元件或這兩種型態組合的電路元件，有些情況下，此兩種型態的電路元件包含裝置之複數個主動半導體區域所組成的部分。半導體元件，例如電晶體、二極體及/或其他各種類型的元件皆可提供於裝置內。具體地，裝置可包含第一元件150，其具有複數個主動半導體裝置區域、複數個介電區域以及其複數個配線圖案，而複數個主動或被動電路元件可設於第一元件150內。如第2A圖所示，中介層100係組裝以及電性連接於第一微電子元件110。在一具體示例中，中介層100也可電性連接第二微電子元件112，甚至能電性連接更多的微電子元件(未顯示於圖中)。如第2圖所示，中介層具有對立之一第一側面140以及一第二側面142，以及在中介層之第一側面140上的一組導電元件114。如在本公開內容內所揭露的裝置，例如中介層、微電子元件、電路板、基板等，其中導電元件係在裝置之表面"上"的描述係意指當裝置沒有與其他任何元件組裝時，導電元件可用於與在垂直於裝置之表面的方向上從裝置外朝向裝置之表面移動的理論點相接觸。因此，在基板的表面上的端部或其他導電元件可突出於此表面；可與此表面齊平；或在基板上的孔洞或坑洞中相對於此表面凹陷。
複數個導電元件114可包含在第一側面140之一表面上的複數個接觸點，此複數個接觸點與複數個相對應的接觸點124面對面接合，例如透過導電結合材料之複數個凸塊，導電結合材料例如錫、銦、焊料、共晶或導電基體材料。如圖所示，與中介層100電性互連的每一至少二微電子元件110與112也可透過中介層100上所提供的配線互連另一微電子元件。儘管未顯示於圖中，在此裝置以及至少一微電子元件110與112之間的電性連接處不受限於僅有上述的覆晶安裝結構。例如但不限制於，電性連接可包含有線接合、金屬對金屬接合，或是突出於裝置之第一側面140或突出於微電子元件之相對應的表面的微柱狀物(導電柱或金屬柱)的連接，此微電子元件係與第一側面140面對面設置。
更進一步，如第2A圖所示，微電子元件110或112可以為封裝或未封裝的半導體晶片。每一微電子元件可包含單一半導體晶片，例如微電子元件110，或可包含已組裝且電性連接另一微電子元件的複數個半導體晶片，例如在微電子元件112內所顯示的複數個堆疊式晶片的配置。
更進一步，如第2A圖所示，中介層100可具有在中介層100之第二側面142上的複數個端部102。如圖所示，複數個端部102可具有附加於其上的複數個接合元件104。如圖所示，複數個接合元件可包含導電結合材料，例如為接合金屬，像是錫、銦、焊料、共晶或包含導電顆粒的導電膠。複數個端部102可以為與中介層100外的第二元件的複數個相對應的接觸部面對面接合的設置型態。例如，如第2A圖中的組件125所示，複數個端部102可與相對應的接觸部134面對面設置於與複數個端部102相接合的電路板120或其他裝置上。F例如，如第2A圖中的組裝所示，每 一端部102可透過接合元件104與相對應的接觸部134面對面接合。如圖所示，具有接觸部134之複數個端部102可藉由將組件加熱到一溫度以進行接合，其中接合元件104之一金屬於此溫度下與複數個接觸部134熔接，接著，此接觸部134在中介層之複數個端部102以及電路板之複數個相對應的接觸部134之間產生複數個接合部。
請再次參閱第1圖，此裝置或中介層100包含第一元件150，此第一元件150包含一較低的熱膨脹係數(以下簡稱為“CTE”)材料，亦即材料所具有的熱膨脹係數在攝氏溫度的每度變化低於百萬分之十(以下簡稱為“ppm/℃”)。第一元件可具有與裝置之第一側140重合或相鄰的第一表面152以及與第一表面相反的一第二表面，亦即面向遠離第一表面的反方向。在有些情況下，第一元件可由半導體材料、玻璃或液晶聚合物製造。
如圖所示，第一元件可包含半導體材料，例如半導體層的形成，其中第一元件之第二表面係為半導體材料或半導體層的表面，第一元件具有覆蓋半導體層的介電材料。如圖所示，第一元件150可具有低CTE區域的化合物結構，例如半導體、玻璃、陶瓷或液晶聚合物以及除前述之外的層，更可具有在第一元件之第一表面以及低CTE區域之表面之間的至少一介電層。如圖所示，第一元件可具有存在於與第一表面相反的第一元件之第二表面以及低CTE區域之表面之間的至少一介電層。此外，至少一配線層可藉由至少一介電層與低CTE區域之半導體區域絕緣。第一元件在垂直於中介層之第一側面140的垂直方向上可具有在其第一表面152以及第二表面154之間的最大厚度156，在一些圖示中，此中介層可為100微米或少於100微米。在一具體示例中，最大厚度156可少於10微米，而有些 情況下，則可少於5微米。
更進一步，如第1圖所示，第二元件160係耦接到第一元件150之第二表面154，第二元件具有與裝置之第二側面142重合或相鄰的表面162。在圖式中，第二元件包含相異於第一材料的第二材料。例如，第一元件可包含第一材料之層以及導電結構，第一材料例如具有覆蓋第一材料之層的至少一介電層的半導體材料或玻璃，導電結構例如金屬配線以及提供穿過至少一介電層以及第一材料之層的複數個導電路徑的複數個孔。
如圖所示，在第一方向180上，從第一元件150之第一表面152到第一元件之第二表面154的第一元件之最大厚度156可少於從第一元件之第二表面到中介層之第二側面142的第二元件160之最小厚度161。
請參閱第1圖以及第2B圖，第二元件160包含複數個絕緣結構480，複數個絕緣結構480係至少部分地藉由至少一間隙490與另一複數個絕緣結構480相分離，至少一間隙490係從第二元件之表面162朝向第一元件150進行延伸，或具體地，朝向第一元件150之第二表面154進行延伸。複數個間隙490係通常填充可以為撓性材料的電絕緣材料491。在多個具體示例中，絕緣材料491可以為彈性體，例如矽樹脂、旋塗玻璃、正型光阻，或是特定類型的矽樹脂，例如矽膠類材料(PDMS)。
例如，可將金屬襯墊或填充金屬提供於延伸穿過複數個絕緣結構的開孔164內，藉此可形成複數個導電互連線166。此複數個互連線可以為導電結構之部分，此導電結構係將複數個端點102電性連接複數個導電元件114或其他導電元件的複數個導電孔170。在多個圖示中，複數個 導電互連線可藉由在複數個開孔164內沉積金屬或其他導電材料中的至少一種而形成，沉積方法可例如氣相沉積法、化學鍍法或電鍍法中的至少一種或壓印法，例如藉由噴墨印刷或網版印刷或模版印刷將未經固化的導電組成物直接壓印到複數個開孔內的至少一區域上。在一些示例中，除了原有的導電層外，為了提高附著力，導電互連線166可包含在複數個開孔164內所形成的至少一金屬層以作為導電晶種層，或在一些情況中，作為複數個離子的擴散阻障。當存在此類型的至少一層時，此至少一層可例如藉由氣相或水溶性沉積法中的至少一種而形成，例如化學鍍法或電鍍法、或壓印法。
複數個導電互連線166可連線複數個開孔164，或可部分或完全地填充複數個開孔164。在多個圖式中，複數個導電互連線166僅連線複數個開孔164或不完全填充複數個開孔，介電材料168可覆蓋在複數個開孔164內的複數個導電互連線166。在一些圖式中，介電材料168可有助於將複數個導電互連線與其他此類的導電互連線絕緣、提供濕氣阻障或裝置的更快或更高效率的製造。導電結構可包含在低CTE元件之厚度方向上進行延伸的複數個金屬化孔170，此複數個金屬化孔170可被更進一步描述如下。在一些情況中，複數個金屬化孔170可穿過至少一配線層153與複數個導電元件114相連接，此至少一配線層153形成於第一元件之至少一介電層內或上面，此第一元件位於上述的低CTE區域之表面的上方。儘管在所提供的各種剖視圖內僅顯示孔洞170連接到每一導電互連線166，但應當理解的是，每一導電互連線可連接到複數個導電孔170，進而與至少一配線層153相連接。此外，一些導電互連線166可不與任何的孔170相連 接，因此，可不與至少一配線層153相連接。此外，一些孔170可不與任何的導電互連線相連接，因此，可不與此裝置之任何的端部102相連接。
在多個具體實施例中，複數個孔170可包含至少一金屬，例如銅、鎳、鋁、鎢、鈦、鈀或此類金屬的合金等。在一具體實施例中，複數個導電墊172可設於第一元件之第二表面上，此複數個導電墊172係電性連接或直接接觸複數個金屬化孔170。複數個導電墊172可由與形成金屬化孔170的金屬相同的一金屬或複數個金屬形成，或是可由與形成金屬化孔170的金屬相異的一金屬形成。在一圖式中，裝置100可具有複數個孔170以及複數個導電墊172所形成的結構，此結構係在形成或組成在第一元件150之第二表面154上方的第二元件160之前而形成。在一具體示例中，複數個金屬化孔170可根據“先孔洞“或“中間孔洞”處理過程而形成，更進一步的描述如下。在此示例中，在第二元件中，至少有一導電墊些可與至少一開孔164或與至少一間隙對準，或可與至少一間隙以及與至少一開孔對準，導電互連線166可包含在複數個開孔164內沉積到複數個導電墊172上的導電材料，例如藉由氣相沉積法、水溶性沉積法或壓印法以及除前述之外的方法中的至少一種。在一圖式中，結構、導電互連線166可包含導電材料(例如焊料、導電膠或導電基體材料)，其例如在至少一開孔或至少一間隙中的至少一種內流動，此至少一間隙在複數個導電墊上或在先前在複數個導電墊上沉積的一導電層上。製造裝置或中介層的製程被更進一步地描述如下。
在另一圖式中，裝置100可具有在複數個導電互連線166形成之後由複數個孔洞170所形成的結構，此複數個導電互連線166係在 第二元件之複數個開孔164內進行延伸而形成。在圖式中，例如當複數個孔洞僅在其他結構形成於第一元件150上之後而形成時，複數個孔洞可被稱為“後孔洞”結構，此其他結構例如複數個主動或被動電路元件(或此兩種型態的電路元件)。在任一情況中，複數個導電墊172有些情況下可被省略，其將被描述於所提供的製造裝置或中介層的製程的描述中。根據此示例，在第一元件內進行延伸的複數個孔洞170可形成用以與複數個開孔164內存在的導電材料相接觸，可例如用以與在形成複數個孔洞170之前形成的存在的複數個導電互連線166相接觸。在此情況下，複數個孔洞170在遠離現存的導電互連線166的第一元件之第一方向180上進行延伸。
在圖式中，第二元件可以為可藉由成型封裝材料(例如密封膠)而形成於第一元件之第二表面上的外模層。在圖式中，第二元件可以為形成於第一元件之第二表面上的封裝的其他組成物。在圖式中，第二元件可以為粒子複合層，此粒子複合層包含高分子基體以及裝載於高分子基體內的粒子。此複合層可例如藉由沉積具有裝載顆粒材料的未經固化的高分子材料以形成於第一元件之第二表面154上，此裝載顆粒材料選擇性地為具有低熱膨脹係數(“CTE”)的介電材料。在圖式中，第二元件可以為包含與第一元件堆疊的介電材料的結構。例如，此結構可以為包含至少高分子介電材料層的增層結構，此增層結構可包含或可不包含額外的補強結構，例如玻璃網及/或填充材料，例如玻璃或陶瓷介電填充物或半導體填充物等。在一具體示例中，此結構可包含至少一陶瓷介電材料層。在圖式中，第二元件可包含光顯像材料，例如苯並環丁烷(BCB)，在圖式中，複數個開孔164可藉由微影圖案而形成。
根據一實施例，第二元件460可具有如第2B圖的結構。在此示例中，第二元件460具有從第二元件之表面162朝向第一元件之第二表面154進行延伸的複數個間隙490。複數個間隙490係至少部分地將第二元件之複數個個別的絕緣結構480與在平行於第二表面154的至少一第一方向494上的另一絕緣結構相分離。在第2B圖內所示的具體實施例中，複數個間隙490將在第一方向494上與每一間隙相鄰的第二元件之複數個個別的區域彼此分離。複數個間隙490也將在第二方向492上與每一間隙相鄰的第二元件之複數個個別的區域彼此分離，第二方向492平行於第二表面154以及橫向於第一方向494進行延伸。更進一步，如第2B圖所示，複數個接合元件404適用於裝置到另一裝置的複數個接合端部102(第1圖)，例如電路板。這些端部係與複數個接合元件404相接合，並可針對複數個端部102(第1圖)以上述的方式與第一元件電性互連。
如圖所示，複數個間隙可在組件內提供優良的熱效能，例如，在第2A圖中的裝置100之複數個端部102係穿過複數個接合元件104與基板106之複數個接觸部134相連接，此基板106可以為電路板或各種裝置中的一種裝置。具體地，如第2B圖所示，在第二元件之複數個個別的絕緣結構480之間的複數個間隙490可降低在複數個端部102以及基板106之間的複數個連接處的機械應力量，例如微差熱膨脹所產生的機械應力。因此，如本文所述，複數個間隙在絕緣元件(例如“第二元件”)之複數個端部以及基板之間提供複數個連接處的“降低應力”的描述，係意旨在包含裝置100以及與其相連接的基板106的組件的作業程序中，例如穿過複數個接合元件104(如第2A圖所示)，複數個連接處相對於不具有所述的複數 個間隙的絕緣元件受到明顯降低的機械應力，而複數個連接處的機械應力係由在基板以及裝置之間或在基板以及至少一晶片110與112之間的微差熱膨脹所造成。
在一實施例中，施加到複數個連接處的應力，例如由在基板106以及至少一裝置100之間或在基板106以及至少一晶片110與112之間的微差熱膨脹所造成的應力，可降低50%以上。在多個具體示例中，應力可降低三分之一以上，或在一些情況中，則可降低十分之一以上。
如第2B圖所示，在圖式中，複數個個別的絕緣結構480可分別配置為複數個島狀物，每一島狀物係藉由至少一間隙490與其他每一島狀物完全分離。因此，複數個相鄰的島狀物彼此可不直接相接觸。在圖式中，複數個島狀物可具有在第一方向494上看來為實質上方形的截面。更進一步，如第2B圖所示，在第二元件之表面162上的複數個個別分離的絕緣結構480之複數個表面可為共面。在第1圖中，從裝置之表面162朝向基板106以面向下方的這些表面可具有長方形、正方形、多邊形、圓形、橢圓形或其它形狀。
至少一些間隙490可具有與其對準的孔洞470。複數個孔洞470可在第二元件460以及另一個元件之間提供一連接處，另一個元件可例如為一BEOL元件。在一些示例中，複數個孔洞470可交替設置以使複數個間隙490(不具有孔洞470)與具有孔洞470的間隙490相鄰。在其他示例中，複數個孔洞470可形成任何數量或配置的複數個間隙490。
在圖式中，如第2C圖所示，第二元件560之至少一部分可包含具有複數個絕緣結構580的連續部分，此複數個絕緣結構580係藉由 複數個間隙590彼此相分離，但仍然與連續部分整合一體，複數個絕緣結構580與複數個間隙一起定義棋盤圖案。在圖式中，棋盤圖案可包含連續的蜂窩圖案，其中複數個間隙可六邊形形狀，第二元件之複數個個別的絕緣結構在第一以及第二方向上環繞複數個間隙。在另一個示例中，棋盤圖案可以為柵格圖，其中複數個間隙係佔據在複數個交叉柵格線之間的複數個空間，此複數個交叉柵格線在第一方向494以及在第二方向492內進行延伸。
在另一示例中，第二元件560之複數個絕緣結構580可配置成彼此相連接。如第2C圖所示，相鄰的絕緣結構580可至少部分地圍住至少一間隙590。例如，複數個相鄰的絕緣結構580可形成與至少部分封閉的間隙590相關的幾何形狀。如第2C圖所示，複數個相鄰的絕緣結構580可形成蜂窩圖案。在其他示例中，複數個相鄰的區域可形成其他形狀，例如柵格狀(例如晶格狀)。
在一實施例中，複數個個別的絕緣結構480與580可至少部分地由負型光阻或其他光顯像材料形成。例如，通常被稱為“SU8”的負型光阻可施加於第一元件之第二表面154上，並接著對複數個區域做微影曝光，在此些區域中個別的絕緣結構480係留在最後的組件中。接著，如第2B圖所示，對光阻影像進行進行顯影，以產生未被光蝕刻微影光源曝光且待移除的的複數個區域，留下複數個個別的絕緣結構480以及複數個間隙490之圖案。此外，可藉由在第二表面154曝光顯影的負型光阻材料而形成光阻影像，並藉以形成可以為第2C圖所述的棋盤圖案的連續圖案。
在圖式中，在第二元件內的複數個開孔之深寬比可不同於， 例如大於，在第一元件內的複數個金屬化孔之深寬比。例如，如第3A圖、第3B圖以及第3C圖所示，開孔164在第一垂直方向(見第1圖的第一元件之厚度之方向180)的高H1相對於在第二水平方向上的高H1之中點H2處的最小尺寸W1，係定義導電互連線延伸穿過開孔164之第一最大深寬比。同樣地，孔洞170在第二元件之第一垂直方向(厚度方向)上的高H2相對於孔洞170在垂直於第一方向的第二水平方向上的高的中點處的最小尺寸W2的比值，係定義孔洞之深寬比。在一具體實施例中，如上述所定義的這些結構之深寬比，在第二元件內的開孔164的深寬比可大於在第一元件內的孔洞170的深寬比。
如第2B圖所示，相鄰的絕緣結構可藉由連接器元件482使彼此相連接，此連接器元件482在複數個相鄰的絕緣結構480之複數個邊緣481之間進行延伸。在此實施例中，連接器元件482可具有不同於、通常小於彼此相鄰以及相連接的複數個絕緣結構之截面積的截面積。
請參閱第4圖，將根據一實施例描述一種製造裝置100之方法。將根據第一實施例描述一種製造中介層之方法，其中複數個孔洞(未顯示於圖中)係在複數個導電互連線(未顯示於圖中)形成之後形成。接著，將描述一種形成中介層之方法，其中複數個孔洞係在複數個導電互連線之前形成。
如第4圖所示，第一元件150在圖中所顯示的是其初始狀態，其可由低CTE材料形成，亦即具有少於10ppm/℃的CTE的材料，例如半導體、玻璃、陶瓷或液晶聚合物材料中的至少一種。第二元件160可與第一元件150形成或組成，使得第二元件覆蓋第一元件之第二表面154。 在一具體實施例中，第二元件160可藉由將封裝層成型於第二表面154之上而形成。在一具體實施例中，封裝層成型步驟可包含形成可與複數個開孔164(請參閱第1圖)相同或相異的至少一凹孔163，其中複數個導電互連線166(請參閱第1圖)如上所述進行延伸。例如，用以形成第二元件的模具可包含相對應的結構，此結構係定義複數個凹孔163的位置、形狀以及大小(亦即在第一方向180上的高以及在平行於第二表面的多個方向上的寬及長)。在一具體示例中，複數個模具成型的凹孔可以為複數個開孔164或複數個開孔之複數個部分。在另一示例中，複數個模具成型的凹孔可以為上述的複數個間隙490或複數個間隙490之一部分。在又一個示例中，複數個模具成型的凹孔可以為複數個開孔以及複數個凹孔兩者。有些情況下，複數個模具成型的凹孔163可不延伸到第一元件之第二表面154上，因此可能需要進行後處理，以更進一步地在朝向第一元件的方向上延伸複數個開孔，例如在第一元件上暴露複數個導電墊，如下更進一步的描述。
第5圖示意複數個孔，例如複數個開孔164、複數個間隙490或其組合，可穿過第二元件進行延伸的製程階段。複數個間隙可如在上面的第2B圖或第2C圖中所述。複數個孔可部分或完全地藉由如上所述的成型製程定義。在另一示例中，在結構中，可形成覆蓋第一元件之第二表面的加工絕緣元件，接著，複數個開孔164、複數個間隙或其組合可在形成第二元件之後形成，例如藉由蝕刻、沖壓、機械或雷射消熔、銑削、指向研磨材料或其顆粒流(其可被稱為“濕式研磨”或“細砂研磨”)或是其他的清除技術。
然後，如第6圖所示，在複數個開孔164內形成的複數個 導電互連線166可包含第二元件160之表面上的複數個端部102的形成。複數個導電互連線的形成可例如在上面的第1圖至第2圖中所述。
此時，介電材料168可進行沉積以覆蓋複數個導電互連線166，也可覆蓋複數個端部102。在圖式中，此介電材料可與最終裝置之介電材料相同，此介電材料隨後回蝕刻或部分地移除到保留在終裝內的介電材料168(請參閱第12圖)之複數個區域。在圖式中，如第6圖所示，複數個孔隙165可存在於複數個開孔或介電材料168內，此複數個孔隙係為真空的或充滿氣體的空間，此空間在複數個開孔的容置空間內係為一封閉空間，在一些情況中，此複數個孔隙在介電材料168內可以為封閉的空間。在圖式中，此複數個孔隙可有助於降低介電材料168之有效介電常數K。
然後，如第7圖所示，第一元件150可從與表面154相對的表面進行研磨，此表面154係與第二元件160相鄰。此製程將第一元件之厚度從初始厚度降低成較低厚度。在一些示例中，此減低的厚度可少於100微米，有些情況下，則可少於10微米，或另一個示例中，可少於5微米。例如，第一元件的研磨可藉由，例如研光、研磨或拋光中的任何至少一種製程執行。
更進一步，如第8圖所示，導電結構可形成於第一元件內或上面，此導電結構包含複數個孔洞170以及電性連接複數個導電互連線166的複數個導電元件114。第9圖為放大圖，顯示複數個孔洞170穿過第一元件之低CTE層151進行延伸以及電性連接導電元件114，例如複數個導電元件114穿過至少一金屬層(例如配線層153)，設置於覆蓋低CTE層的至少一介電層內，此低CTE層在中介層之第一側面140以及第二元件160 之間。複數個孔洞可延伸穿過低CTE層到設置於複數個開孔164內的複數個導電互連線166之複數個部分而形成。在一具體示例中，當低CTE層係由半導體材料形成時，形成複數個孔洞170的製程可包含蝕刻延伸穿過低CTE層的複數個開孔，接著，例如藉由將介電材料沉積於複數個開孔之壁上以及底部上以在複數個開孔上形成介電材料層，並接著，例如藉由蝕刻以移除複數個開孔之底部上的介電材料，以允許形成與複數個導電互連線166相接觸的複數個孔洞。然後，可執行更進一步的製程，在複數個介電層上或內部形成至少一介電層以及配線層，以在電性連接複數個孔洞170的第一元件150之表面上形成複數個導電元件114。
接下來，根據上述的方法的變化型，描述一種製造裝置(例如中介層)的方法。在此變化型中，根據一方法描述製造裝置，此方法係為在將第一元件與第二元件160組成或組裝之前，將複數個孔洞170(第11圖)以及複數個導電墊172提供於第一元件150上。
在圖式中，複數個孔洞170可以為複數個“先孔洞”結構，其中複數個孔洞170係在執行複數個主動、被動電路元件或其兩種型態組合的電路元件形成第一元件之複數個主動半導體區域的製程之前形成。在此示例中，複數個孔洞通常係由能夠承受高溫的材料所形成(溫度範圍通常在850°以上，且時常更高)，其中複數個半導體裝置在此高溫下可形成第一元件之半導體區域。例如，能夠承受高溫的複數個孔洞可由多種金屬形成，例如鈦、鎢、鈦鎢、鈦鎢鉭導電化合物或其任何組合。此外，複數個孔洞可由經摻雜的多晶半導體材料形成，例如多晶矽、至少一前述的導電材料或其組合。
在另一示例中，複數個孔洞170可以為“中間孔洞”結構。此變動中，複數個孔洞170的形成係在形成複數個主動或被動電路元件於第一元件內之後，但在執行下述的更進一步的製程之前。在此變化型中，複數個金屬化孔洞170係被稱為“中孔洞”結構，因為它們將在執行形成複數個主動或被動電路元件所需的多個高溫製程步驟之後形成。在此變化型中，複數個孔洞170可由金屬形成，例如銅、鎳、鋁或鈀。
因此，起始於低CTE元件148，例如上面第10圖中所描述，以下係描述一種製造裝置之方法。如第11圖所示，複數個導電墊172以及與複數個孔洞相連接的複數個導電孔洞170可從第一元件之第二表面154朝向表面149向內進行延伸而形成。在圖式中，複數個導電墊172、複數個孔洞170或其組合可藉由沉積金屬而形成，例如銅、鋁、鎳、鈀或其他金屬或在第一元件上的多個金屬的組合，例如藉由氣相沉積法、化學鍍或電鍍或其組合。
在一適當情況下，導電材料(例如導電基體材料)可用以形成複數個導電墊、複數個孔洞或其組合。通常，複數個導電墊172以及複數個孔洞170係藉由包含沉積或化學鍍導電晶種層以及將另一金屬電鍍於其上的多個步驟，形成於第一元件之介電絕緣材料之上。在一具體示例中，複數個導電墊可覆蓋阻障金屬，例如化學鍍鈀或化鎳鈀合金、其他可能的塗料等。在圖式中，如第15圖所示，當複數個導電互連線166在第二元件之複數個開孔164內進行延伸時，阻障金屬可用以限制或避免在複數個導電墊以及焊料或其他導電金屬之底層金屬之間的交互作用，此其他導電金屬隨後可與複數個導電墊172相接觸。
如第12圖所示，複數個導電墊172可藉由覆蓋第一元件之第二表面154的介電層155使彼此絕緣，複數個孔洞170可穿過介電層155進行延伸，並可藉由在複數個孔洞170上的介電層與第一元件所圍繞的低CTE材料絕緣，特別是低CTE材料係為半導體區域時。此外，當第一元件係由介電材料或其他在複數個相鄰的導電孔以及複數個相鄰的導電墊172之間的絕緣材料形成時，介電層155以及複數個孔洞170上的介電層可省略不用。
接著，如第13圖、第14圖以及第15圖所示，能以上面第4圖、第5圖以及第6圖所述的方式執行製程，不同之處在於，當複數個開孔164完整形成時，複數個導電墊172(請參閱第14圖)係至少部分地與複數個開孔164對準，並可具有至少部分地在複數個開孔內曝光的複數個表面，複數個導電互連線166(請參閱第15圖)係藉由導電材料耦接到複數個導電墊，例如沉積於在複數個開孔內曝露的複數個導電墊之複數個表面之至少一部分上的金屬。在圖式中，如第13圖所示，複數個開孔163可選擇性地在部分延伸穿過第二元件160進行的成型製程中形成。複數個開孔163可接著藉由隨後的製程進行延伸，以形成穿過至少部分暴露的複數個導電墊172之表面的複數個開孔164(請參閱第14圖)。複數個導電互連線166可藉由在複數個開孔內電鍍或沉積導電材料而形成，此複數個開孔與複數個導電墊172之複數個表面之至少一部分相接觸。然後，如第6圖所示，介電材料168(請參閱第15圖)可進行沉積以至少部分地覆蓋複數個導電互連線166。
請參閱第16圖，如上所述，製程可接著繼續執行第一元件 150之研磨以降低其厚度。在一具體示例中，第一元件150可被減少厚度直到複數個孔洞170幾乎皆在研磨表面202上暴露，接著，隨後的製程，例如可執行蝕刻以露出複數個孔洞170上的介電材料以及金屬所形成的複數個孔洞，可例如銅、鎳、鋁、鎢、鈦、鈀中的至少一種或這些金屬的合金等。
然後，請參閱第17圖以及第18圖，製程可持續執行以在複數個介電層以及複數個導電元件114內形成至少一介電層以及至少一配線層153，例如在上面的第8圖以及第9圖中所描述的中介層之複數個導電墊。如第18圖所示，介電材料168可移除以暴露複數個端部102，並可將複數個接合元件104(例如複數個銲料球體)選擇性地施加或接合到複數個端部。
上述的複數個結構係提供特殊的三維互連能力。這些能力可適用於任何的類型的晶片。僅以舉例的方式，下文中的複數個晶片之結合可含於上述的複數個結構內：(i)處理器以及處理器所用的記憶體；(ii)相同的類型之複數個記憶體晶片；(iii)相異型態之複數個記憶體晶片，例如DRAM以及SRAM；(iv)影像感測器以及用以處理來自感測器的影像的影像處理器；(v)特殊應用積體電路(“ASIC”)以及記憶體。上述的複數個結構可使用於多樣的電子系統之架構。例如，根據發明之另一實施例，系統300包含一結構306，如上所述，此結構306與其他的電子裝置308以及310相接合。在示意圖式中，裝置308係為半導體晶片，而裝置310係為顯示螢幕，但實施上可使用任何其他的裝置。當然，第19圖儘管僅有兩個額外的裝置，系統仍可包含任何數量的裝置。上述的結構306可如第1圖或第2 圖中所述的微電子組件。結構306以及裝置308與310係皆安裝於使用虛線示意的共用殼體301內，並且彼此電性互連以形成所期望的電路。在所實施例的系統中，系統包含電路板302，例如可撓性印刷電路板，此電路板包含彼此互連的複數個導線304，其中僅有一個導線示於第19圖中。然而，其僅為示例性；實施上，可使用產生電性連接處的任何適當結構。殼體301可作為攜帶類型的殼體，例如在行動電話或個人數位助理內，而螢幕310露出於殼體之表面上。結構306包含光感測元件，例如影像晶片、透鏡311，或其他也可提供用以將光導到結構上的光學裝置。再次，在第19圖簡化的系統係僅為示意，其他系統包含普遍被稱為固定結構的複數個系統，例如桌上型電腦、路由器以及其相似物，可使用上述的複數個結構製造。
在較佳實施例之詳細說明中所提出之具體實施例僅用以方便說明本發明之技術內容，而非將本發明狹義地限制於上述實施例，在不超出本發明之精神及以下申請專利範圍之情況，所做之種種變化實施，皆屬於本發明之範圍。
100‧‧‧裝置
102‧‧‧端部
104‧‧‧接合元件
106‧‧‧基板
110‧‧‧微電子元件
112‧‧‧第二微電子元件
114‧‧‧導電元件
124‧‧‧接觸點
125‧‧‧組件
134‧‧‧接觸部
140‧‧‧第一側面
148‧‧‧低CTE元件
160‧‧‧第二元件

Claims (18)

  1. 一種具有對立之第一側面及第二側面的裝置，包含：一第一元件，係具有一第一表面重合或相鄰該裝置之該第一側面，及一第二表面對立於該第一表面，該第一元件包含具有一低於10ppm/℃的熱膨脹係數的一第一材料；一第二元件，係耦接到該第一元件之該第二表面，並具有一表面重合或相鄰該裝置之該第二側面，該第二元件包含由不同於該第一材料的至少一第二材料所組成的複數個電絕緣結構，每一該複數個電絕緣結構至少部分地藉由從該第二元件之該表面朝向該第一元件進行延伸的至少一間隙與另一電絕緣結構相分離；複數個導電元件，係位於該第一側面上；複數個端部，係位於該第二側面上，且用以與該裝置外的一另一裝置的複數個相對應的接觸部相連接；以及導電結構，係利用該複數個導電元件電性耦接於該複數個端部，該導電結構包含延伸於開孔內的導電互連線，每一開孔穿過該絕緣結構之一者朝向該第一元件延伸；其中該導電結構包含一導電材料，係延伸於各別之該開孔之內；及金屬化孔，係各自延伸於該第一元件內之複數相對應獨立之開孔之一者內，該第一元件利用該絕緣結構之一者之內之一各別的開孔對齊；一導電墊位於該第一元件之該第二表面，至少部分與該各別之開孔對齊，而且每一金屬化孔與該導電墊及該導電材料接觸，該導電墊與該各別之開 孔對齊；其中該第二元件至少部分由一負型光阻形成。
  2. 如申請專利範圍第1項所述之裝置，其中該至少一間隙係用以降低在該第二元件之複數個端部以及與其相連接之該另一裝置之間的連接處的應力。
  3. 如申請專利範圍第1項所述之裝置，其中該複數個絕緣結構係定義複數個該間隙，該複數個間隙定義之複數個島狀物，係藉由該複數個間隙與另一島狀物完全分離，每一島狀物包含至少一絕緣結構。
  4. 如申請專利範圍第3項所述之裝置，其中該複數個間隙係填充一絕緣材料。
  5. 如申請專利範圍第1項所述之裝置，更包含複數個連接器元件，該複數個連接器元件包含該第二材料，該複數個連接器元件係將該複數個絕緣結構與另一絕緣結構鄰接，該複數個連接器元件在該複數個絕緣結構之複數個相鄰的絕緣結構之複數個邊緣之間進行延伸，並具有不同於該複數個相鄰的絕緣結構的截面積。
  6. 如申請專利範圍第3項所述之裝置，其中至少一該島狀物在第一方向上有一實質上方形截面。
  7. 如申請專利範圍第3項所述之裝置，其中該複數個島狀物或複數個間隙係設置成一柵格圖案。
  8. 如申請專利範圍第3項所述之裝置，其中至少二或更多該島狀物的表面，係與該裝置之該表面上的另一截面共面。
  9. 如申請專利範圍第3項所述之裝置，其中該第二元件之一連續部分與複數個絕緣結構整合為一體，該複數個絕緣結構及該複數個間隙係一起定義一棋盤圖案。
  10. 如申請專利範圍第9項所述之裝置，其中該棋盤圖案選定之群組，係由一蜂窩圖案以一柵格圖案所構成。
  11. 如申請專利範圍第1項所述之裝置，其中該裝置係為一中介層(interposer)。
  12. 如申請專利範圍第3項所述之裝置，其中該第二元件之一封裝材料，係覆蓋該第一元件之該第二表面。
  13. 如申請專利範圍第1項所述之裝置，其中該第一元件之半導體材料，係具有一表面在該第一元件之該第二表面上，而該第一元件之介電材料，係 重疊半導體材料層，該第一元件之該第一表面係為該介電材料之一表面。
  14. 如申請專利範圍第13項所述之裝置，其中該第一元件之複數個電路元件，係由主動電路元件及被動電路元件所組成。
  15. 如申請專利範圍第14項所述之裝置，其中該第一元件在該第一元件之該第一表面到其第二表面的一垂直方向上，具有一最大厚度：該最大厚度在該第一元件之該第一表面到其第二表面的一方向上係少於100微米；該最大厚度從該第一元件之該第一表面到其第二表面係少於10微米；或該最大厚度係少於該第二元件在垂直方向上的一最大厚度。
  16. 一種包含具有對立之第一側面及第二側面的裝置的系統，係包含如申請專利範圍第1項所述之一裝置以及電性耦接於該裝置之至少一另一裝置。
  17. 一種製造具有對立之一第一側面以及一第二側面的一裝置之方法，該方法包含：形成一結構，該結構包含：一第一元件，係具有第一表面，與該第一側面重合或相鄰，以及一第二表面，與該第一表面對立，該第一元件包含一具有少於10ppm/℃的熱膨脹係數的一材料；一第二元件，係耦接到該第一元件之該第二表面，並具有與該第二側 面重合或相鄰的一表面，複數個導電元件，係位於該第一側面，其中該第二元件包含：由不同於該第一材料的至少一第二材料所組成的複數個電絕緣結構，每一該複數個電絕緣結構係至少部分，藉由從該第二元件之該表面朝向該第一元件進行延伸的至少一間隙，與另一電絕緣結構相分離；其中形成該結構的步驟包含：微影圖樣化一光顯像材料，該圖樣化材料所定義之該複數個相對應的絕緣結構，係藉由該至少一間隙相分離；其中該第二元件至少部分由一負型光阻形成；以及在該第二側面上形成複數個端部，以及形成導電結構，該複數個端部係用以與該裝置外的一另一裝置的複數個相對應的接觸部相連接，該導電結構係利用該複數個導電元件電性耦接於該複數個端部，該導電結構包含導電互連線，係延伸於開孔內，每一開孔係通過該絕緣結構之一者朝向該第一元件延伸；其中該導電結構包含一導電材料，係延伸於各別之該開孔之內；及金屬化孔，係各自延伸於該第一元件內之複數相對應獨立之開孔之一者內，該第一元件利用該絕緣結構之一者之內之一各別的開孔對齊，且每一金屬化孔係與該導電材料接觸。
  18. 如申請專利範圍第17項所述之方法，其中形成該結構的步驟包含：成型含有一介電材料的一材料，以定義該至少一間隙所分離的該複數個絕緣結構。
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US9691693B2 (en) 2017-06-27
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US10403510B2 (en) 2019-09-03
US20170294321A1 (en) 2017-10-12

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