TWI578521B - A thin film transistor and its preparation method - Google Patents

A thin film transistor and its preparation method Download PDF

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TWI578521B
TWI578521B TW105117319A TW105117319A TWI578521B TW I578521 B TWI578521 B TW I578521B TW 105117319 A TW105117319 A TW 105117319A TW 105117319 A TW105117319 A TW 105117319A TW I578521 B TWI578521 B TW I578521B
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source
drain
semiconductor layer
gate
thin film
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TW201711193A (zh
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Qi Dan
Xiu-Qi Huang
Shi-Xing Cai
Xiao-Bao Zhang
Rui Guo
Li Lin
xiao-yu Gao
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile

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Description

一種薄膜電晶體及其製備方法
本發明屬於光電顯示技術領域，特別是關於一種薄膜電晶體及其製備方法。
在現有技術中，為了提高薄膜電晶體的遷移率，可採用上下雙柵結構以在半導體層感應出雙溝道來增大導電通道。
圖1為現有技術所提供的一種具備雙柵結構的薄膜電晶體的結構示意圖。如圖1所示，該薄膜電晶體的上柵極1重疊覆蓋於源極2和汲極3上方。當上柵極1和下柵極4都達到開啟電壓(開啟電壓為一種閾值電壓，當柵極的電壓高於該開啟電壓時，即可在半導體層中感應形成導電溝道)時，可在半導體層5中感應形成相互平行的上下兩個導電溝道。由於上柵極1重疊覆蓋於源極2和汲極3上方(在與半導體層5中導電溝道平行的平面上，上柵極1的正投影分別與源極2的正投影和汲極3的正投影是部分重疊的)；因此，汲極3可單獨通過上方的導電溝道實現與源極2的導通。此外，汲極3也可單獨通過下方的導電溝道實現與源極2的導通。然而，這種雙柵結構薄膜電晶體存卻很難通過上下導電溝道的同時導通來 保證遷移率的提升，原因在於：由於工藝技術的原因，上柵極1下方的上絕緣層6與下柵極上方的下絕緣層7的電容等參數很難匹配，這會導致上柵極1和下柵極4分別形成的上下兩個導電溝道的開啟電壓不同，因此現有技術中的薄膜電晶體結構很難形成上下導電溝道的同時導通。
有鑑於此，本發明實施例提供一種薄膜電晶體以及製備方法，解決了現有技術中薄膜電晶體的上柵極和下柵極難以實現上下導電溝道的同時導通的問題。
本發明實施例提供的一種薄膜電晶體，包括：上柵極、下柵極、上絕緣層、下絕緣層、半導體層、源極和汲極；其中，該下柵極上方設有該下絕緣層；該下絕緣層上方設有該半導體層；該半導體層分別與該源極和汲極搭接；該半導體層上方覆蓋該上絕緣層；該上絕緣層上方設有上柵極；其中，在與該半導體層中導電溝道平行的平面上，該上柵極的正投影與該源極的正投影之間存在第一間隙，該上柵極的正投影與該汲極的正投影之間存在第二間隙。
本發明實施例還提供了一種薄膜電晶體的製備方法，包括：在基板上沉積金屬層，並將該金屬層圖案化以形成下柵極；在該下柵極表面沉積下絕緣層，並在該下絕緣層表面沉積半導體層，然後在該半導體層表面沉積上絕緣層；在該上絕緣層表面對應源極和汲極的位置處分別刻蝕成源 極孔和汲極孔；該源極孔和汲極孔的底部與該半導體層導通；在該上絕緣層表面、源極孔和汲極孔中沉積金屬層，並將該金屬層圖案化形成源極、汲極和上柵極；其中，在與該半導體層中導電溝道平行的平面上，該上柵極的正投影與該源極的正投影之間存在第一間隙，該上柵極的正投影與該汲極的正投影之間存在第二間隙。
本發明實施例提供的一種薄膜電晶體，在與半導體層中導電溝道平行的平面上，上柵極的正投影與源極的正投影之間存在第一間隙，上柵極的正投影與該汲極的正投影之間存在第二間隙，因而上柵極無法獨立形成上導電溝道的導通，而只有在下柵極達到開啟電壓時，才能利用下柵極感應形成的下導電溝道間接完成上導電溝道的導通，從而實現了上下導電溝道的同時導通。
1‧‧‧上柵極
2‧‧‧源極
3‧‧‧漏極
4‧‧‧下柵極
5‧‧‧半導體層
6‧‧‧上絕緣層
7‧‧‧下絕緣層
8‧‧‧第一間隙
9‧‧‧第二間隙
10‧‧‧上導電溝道
11‧‧‧下導電溝道
12‧‧‧第一半導體材料高阻區
13‧‧‧第二半導體材料高阻區
14‧‧‧源極孔
15‧‧‧漏極孔
16‧‧‧鈍化層
圖1是現有技術所提供的一種具備雙柵結構的薄膜電晶體的結構示意圖；圖2是本發明一實施例所提供的一種薄膜電晶體的結構示意圖；圖3是本發明另一實施例所提供的一種薄膜電晶體的結構示意圖；圖4是本發明一實施例所提供的一種薄膜電晶體的導電原理示意圖；圖5是本發明一實施例所提供的一種薄膜電晶體的導電原理示意圖；圖6是本發明一實施例所提供的一種薄膜電晶體的導電實驗結果圖；以及圖7是本發明一實施例所提供的一種薄膜電晶體的製備方法流程示意 圖。
為使本發明的目的、技術方案和優點更加清楚，下面結合附圖對本發明作進一步的詳細描述。
圖2是本發明一實施例所提供的一種薄膜電晶體的結構示意圖。如圖2所示，該薄膜電晶體包括：上柵極1、下柵極4、上絕緣層6、下絕緣層7、半導體層5、源極2(source)和汲極3(drain)；其中，下柵極4上方設有下絕緣層7；下絕緣層7上方設有半導體層5；半導體層5分別與源極2和汲極3搭接；半導體層5上方覆蓋上絕緣層6；上絕緣層6上方設有上柵極1；其中，在與半導體層5中導電溝道平行的平面上，上柵極1的正投影與源極2的正投影之間存在第一間隙8，上柵極1的正投影與汲極3的正投影之間存在第二間隙9。
本領域技術人員可以理解，半導體層5與源極2和汲極3的搭接方式可根據實際結構設計需要而調整，只要能實現半導體層5中導電溝道與源極2和汲極3的導通即可，本發明對半導體層5與源極2和汲極3的搭接方式不做限定。
在本發明一實施例中，如圖2所示，上絕緣層6表面包括源極孔14和汲極孔15，半導體層5與源極2和汲極3所採用的搭接方式為：源極2通過上絕緣層6表面的源極孔14與半導體層5表面相搭接，汲極3通過上絕緣層6表面的汲極孔15與半導體層5表面相搭接。由此可見，與現有技術中具備上下雙柵結構的薄膜電晶體不同，當採用上述搭接方式 時，上柵極1並沒有重疊覆蓋於源極2和汲極3上方，而是與源極2和汲極3處於同一層。且由於在與半導體層5中導電溝道平行的平面上，上柵極1的正投影分別與源極2的正投影和汲極3的正投影分別存在第一間隙8和第二間隙9，故半導體層5與第一間隙8和第二間隙9對應的區域始終處於高阻狀態。因此，即使上柵極1達到了開啟電壓，且與上柵極1對應的半導體層5感應形成處於低阻狀態的上導電溝道，也無法實現上導電溝道與源極2和汲極3之間的導通；而只有在下柵極4達到開啟電壓時，才能利用下柵極4感應形成的下導電溝道間接完成上導電溝道的導通，從而實現上下導電溝道的同時導通。
此外，如圖1所示，在現有技術中上柵極1重疊覆蓋於源極2和汲極3上方，因而需要為上柵極1的製備單獨設計一層鈍化層16以進行掩膜刻蝕，這會增加製備成本。而當採用如圖2所示的薄膜電晶體結構時，上柵極1與源極2和汲極3處於同一層，無需為上柵極1的製備單獨設計一次掩膜刻蝕過程，上柵極1、源極2和汲極3可通過一次刻蝕過程同步形成，從而節約了製備成本。
圖3所示為本發明另一實施例所提供的一種薄膜電晶體的結構示意圖。與圖2所示的結構不同，在圖3所示的薄膜電晶體結構中，半導體層5與源極2和汲極3採用了另一種搭接方式，同樣可以實現上下導電溝道的同時導通。具體而言，源極2和汲極3設置在下絕緣層7上方，半導體層5同時與源極2表面、汲極3表面和下絕緣層7表面相搭接。這樣當上柵極1和下柵極4都達到了開啟電壓時，半導體層5中同樣可以感應形成相互平行的上下兩個導電溝道，並形成上下導電溝道與源極2和汲 極3的同時導通。
在本發明一實施例中，半導體層5的厚度通常較薄，這是為了避免源極2/汲極3的電流擊穿半導體層5達到導電溝道時的寄生電阻過大。然而，由於導電溝道在導通狀態下的深度在3nm~15nm左右，因此為了保證半導體層5中上下導電溝道同時開啟且互不影響，可將半導體層5的厚度設置在10nm至200nm之間。在一實施例中，半導體層5的厚度可以具體設定為30nm，此厚度既可以保證在半導體層5上下表面形成足夠寬的導電溝道，也可以盡可能的減少源極2/汲極3與導電溝道搭接的寄生電阻。
如前所述，在與半導體層5中導電溝道平行的平面上，上柵極1的正投影與源極2的正投影之間存在第一間隙8，上柵極1的正投影與汲極3的正投影之間存在第二間隙9。其中，第一間隙8的寬度對應第一半導體材料高阻區，第二間隙9的寬度對應第二半導體材料高阻區。為了保證上導電溝道10與源極2和汲極3之間存在半導體材料高阻區，同時為了盡可能減小薄膜電晶體的體積，第一間隙8和第二間隙9的寬度可根據半導體層5的半導體材料的固有電阻以及所能承受的最低漏電流進行調整。其中，當下柵極4未達到開啟電壓，而上柵極已達到開啟電壓時，流過半導體層5的漏電流可表示為：Ileak=Ud/(2R*W/D)，其中Ud為汲極電壓，R為半導體層5的固有電阻，W為半導體層5的寬度，Dum為第一間隙8/第二間隙9的寬度。
在本發明一實施例中，當半導體層5選用的半導體材料(例如金屬氧化物)的本征方塊電阻可以達到R=1e+12Ω，汲極電壓Ud=10V， 半導體層5的寬度W=5um，第一間隙8/第二間隙9的寬度D=1um時(這裡的1um為在上柵極1與源極2/汲極3之間加工第一間隙8/第二間隙9的工藝極限值)，此時求得的漏電流Ileak=0.5pA，可以符合OLED裝置產品需求。因而上柵極1與源極2/汲極3存在的第一間隙8/第二間隙9的寬度最小可達1um。在本發明一實施例中，第一間隙8和第二間隙9的寬度也可以具體設定為3um，這樣既可以保證光刻機在穩定的工藝條件下工作，實現較高工藝精度，又可以將上柵極1的漏電流控制在1pA量級，同樣可以符合OLED裝置產品需求。本發明對第一間隙8和第二間隙9的寬度不做嚴格限定。
在本發明一實施例中，半導體層5可採用金屬氧化物(例如銦鎵鋅氧IGZO)，或非晶矽，或多晶矽，或微晶矽材料等半導體材料製成。本發明對半導體層5的製備材料不做限定。
在本發明一實施例中，上柵極1、下柵極4、源極2和汲極3可由Mo金屬材料或其他導電材料製成。本發明對上柵極1、下柵極4、源極2和汲極3的製備材料同樣不做限定。
圖4是本發明一實施例所提供的一種薄膜電晶體的導電原理示意圖。如圖4所示，半導體層5與源極2和汲極3採用了如圖2所示的搭接方式，下柵極4還未達到下柵極4的開啟電壓，因而半導體層5中無法形成下導電溝道的導通。所以，即使上柵極1已達到了上柵極1的開啟電壓，但由於上柵極1並沒有重疊覆蓋與源極2和汲極3上方，而是與源極2和汲極3處於同一層並覆蓋了一部分上絕緣層6，而且上柵極1與源極2和汲極3之間存在第一間隙8和第二間隙9，因而上柵極1僅能在半導 體層5中與上柵極1對應的較短的上導電溝道10。該上導電溝道10與源極2和汲極3之間也就存在與第一間隙8對應的半導體材料高阻區12，以及與第二間隙9相對應的半導體材料高阻區13，因而該上導電溝道10與源極2和汲極3無法導通。由此可見，當下柵極4未達到下柵極4的開啟電壓時，無論上柵極1是否達到了上柵極1的開啟電壓，上導電溝道10都是無法與源極2和汲極3實現導通的。
圖5是本發明一實施例所提供的一種薄膜電晶體的導電原理示意圖。如圖5所示，半導體層5與源極2和汲極3採用了如圖2所示的搭接方式，下柵極4已達到下柵極4的開啟電壓，半導體層5中電流的流向如圖中的箭頭所示。具體而言，由於下柵極4已達到下柵極4的開啟電壓，因而在半導體層5中已形成下導電溝道11，由於半導體層5的厚度較薄，電流可從汲極3擊穿半導體層5到達下導電溝道11，並經由下導電溝道11再次擊穿半導體層5流向源極2。此時，當上柵極1也達到了上柵極1的開啟電壓時，電流就可從下導電溝道11擊穿半導體層5到達上導電溝道10，並經由上導電溝道10再擊穿半導體層5流回下導電溝道11，並最終流向源極2。由此便實現了上導電溝道10和下導電溝道11的同時導通，起到了提高遷移率的效果。
本領域技術人員可以理解，為了實現上導電溝道10和下導電溝道11的同時導通，操作者可以對上柵極1和下柵極4的電路結構採用多種設置方式。例如，操作者可以使上柵極1與下柵極4在電路結構中各自獨立設置而不並聯設置，使上柵極1的電壓一直保持高於上柵極1的開啟電壓的狀態。然而由於第一間隙8和第二間隙9的存在，上導電溝道10 並不會與源極2和汲極3導通，而只有在下柵極4達到下柵極開啟電壓時，上柵極1才能利用下柵極4感應形成的下導電溝道11間接完成上導電溝道10的導通。本發明對上柵極1和下柵極4各自的電路結構設置方式並不做限定。
圖6是本發明一實施例所提供的一種薄膜電晶體的導電實驗結果圖。如圖6所示，其中的Vg為下柵極4的電壓，Vth為下柵極4的開啟電壓，|Id|為半導體層5中導通的電流大小，比率指的是本發明薄膜電晶體與傳統單柵結構的遷移率的比值，測試條件為：汲極電壓Vd=0.1V，Vg=-10~20V。
由圖6可見，採用本發明實施例所提供的薄膜電晶體結構同樣可獲得相對於傳統單柵薄膜電晶體兩倍以上的遷移率。如下表所示：
圖7是本發明一實施例所提供的一種薄膜電晶體的製備方法流程示意圖，所形成的薄膜電晶體中的半導體層5與源極2和汲極3採用如圖2所示的搭接方式。如圖7所示，該薄膜電晶體的製備方法包括：
步驟701：在基板上沉積金屬層，並將金屬層圖案化以形成下柵極4。其中，可採取玻璃板作為基板。
步驟702：在下柵極4表面沉積下絕緣層7，並在下絕緣層7表面沉積半導體層5，然後在半導體層5表面沉積上絕緣層6。
在本發明一實施例中，由於下絕緣層7與下柵極4貼合，而下柵極4又可稱為gate極，因此該下絕緣層7又可稱為柵絕緣層(gate insulate)。
在本發明一實施例中，由於後續需採用刻蝕過程形成源極孔14和汲極孔15，因此上絕緣層6又可被稱為刻蝕阻擋層(ESL)。
步驟703：在上絕緣層6表面對應源極2和汲極3的位置處分別刻蝕源極孔14和汲極孔15；源極孔14和汲極孔15的底部與半導體層5導通。這樣源極孔14和汲極孔15中後續形成的源極2和汲極3才能和半導體層5相搭接。
步驟704：在上絕緣層6表面、源極孔14和汲極孔15中沉積金屬層，並將金屬層圖案化形成源極2、汲極3和上柵極1；在與半導體層5中導電溝道平行的平面上，上柵極1的正投影與源極2的正投影之間存在第一間隙8，上柵極1的正投影與汲極3的正投影之間存在第二間隙9。由此可見，由於上柵極1、源極2和汲極3處於同一層，上柵極1、源極2和汲極3可通過一次圖案化過程同步形成，而不用為上柵極1的製備單獨設計一次掩膜刻蝕過程，節約了製備成本。最終所製成的薄膜電晶體上可繼續沉積鈍化層、陽極，或進行OLED製備等其他工藝。
本發明實施例提供的一種薄膜電晶體，在與半導體層5中導電溝道平行的平面上，上柵極1的正投影與源極2的正投影之間存在第一間隙8，上柵極1的正投影與汲極3的正投影之間存在第二間隙9，因而上柵極1無法獨立形成上導電溝道10的導通，而只有在下柵極4達到開啟電壓時，才能利用下柵極4感應形成的下導電溝道11間接完成上導電溝道10 的導通，從而實現了上下導電溝道的同時導通。
以上僅為本發明的較佳實施例而已，並不用以限制本發明，凡在本發明的精神和原則之內，所作的任何修改、等同替換等，均應包含在本發明的保護範圍之內。
工業實用性
本發明的薄膜電晶體適合採用現有生產設備工業生產，可以應用於高集成度的、高解析度的液晶面板等相關技術領域的產品。其結構改善了半導體層上下導電溝道的同時導通性能。
本發明的薄膜電晶體製備方法，可以充分利用現有生產加工設備形成生產工藝過程，適合大規模工業生產，形成的薄膜電晶體具有高遷移率。
1‧‧‧上柵極
2‧‧‧源極
3‧‧‧漏極
4‧‧‧下柵極
5‧‧‧半導體層
6‧‧‧上絕緣層
7‧‧‧下絕緣層
8‧‧‧第一間隙
9‧‧‧第二間隙
14‧‧‧源極孔
15‧‧‧漏極孔

Claims (10)

  1. 一種薄膜電晶體，其特徵在於，包括：上柵極、下柵極、上絕緣層、下絕緣層、半導體層、源極和汲極；其中，該下柵極上方設有該下絕緣層；該下絕緣層上方設有該半導體層；該半導體層分別與該源極和汲極搭接；該半導體層上方覆蓋有該上絕緣層；該上絕緣層上方設有上柵極；其中，在與該半導體層中導電溝道平行的平面上，該上柵極的正投影與該源極的正投影存在第一間隙，該上柵極的正投影與該汲極的正投影之間存在第二間隙。
  2. 如請求項1所述的薄膜電晶體，其中，該上絕緣層表面包括源極孔和汲極孔；該半導體層分別與該源極和汲極搭接，包括：該源極通過該源極孔與該半導體層表面相搭接，該汲極通過該汲極孔與該半導體層表面相搭接。
  3. 如請求項1所述的薄膜電晶體，其中，該半導體層分別與該源極和汲極搭接，包括：該源極和汲極設置在該下絕緣層上方，該半導體層同時與該源極表面、汲極表面和下絕緣層表面相搭接。
  4. 如請求項1所述的薄膜電晶體，其中，使用時，該上柵極的電壓保持高於上柵極的開啟電壓。
  5. 如請求項1所述的薄膜電晶體，其中，該第一間隙或第二間隙的寬度根據半導體層的半導體材料的固有電阻以及所能承受的最低漏電流進行調整。
  6. 如請求項5所述的薄膜電晶體，其中，該第一間隙和/或第二間隙的寬度大於1um。
  7. 如請求項5所述的薄膜電晶體，其中，該第一間隙和/或第二間隙的寬度為3um。
  8. 如請求項1所述的薄膜電晶體，其中，該半導體層的厚度為30nm。
  9. 一種如請求項2所述薄膜電晶體的製備方法，其特徵在於，包括：在基板上沉積金屬層，並將該金屬層圖案化以形成下柵極；在該下柵極表面沉積下絕緣層，並在該下絕緣層表面沉積半導體層，然後在該半導體層表面沉積上絕緣層；在該上絕緣層表面對應源極和汲極的位置處分別刻蝕源極孔和汲極孔；該源極孔和汲極孔的底部與該半導體層導通；在該上絕緣層表面、源極孔和汲極孔中沉積金屬層，並將該金屬層圖案化形成源極、汲極和上柵極；其中，在與該半導體層中導電溝道平行的平面上，該上柵極的正投影與該源極的正投影之間存在第一間隙，該上柵極的正投影與該汲極的正投影之間存在第二間隙。
  10. 如請求項9所述的薄膜電晶體的製備方法，其中，該上柵極、源極和汲極通過一次圖案化同步形成。
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TW201711193A (zh) 2017-03-16
KR20180015659A (ko) 2018-02-13
US20180097119A1 (en) 2018-04-05
EP3306669A1 (en) 2018-04-11
CN106298883A (zh) 2017-01-04
EP3306669A4 (en) 2018-06-27
CN106298883B (zh) 2020-09-15
JP6541803B2 (ja) 2019-07-10
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KR102017228B1 (ko) 2019-09-02
WO2016192624A1 (zh) 2016-12-08

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