TWI578466B - 具有垂直柱之重疊堆疊的晶粒封裝 - Google Patents
具有垂直柱之重疊堆疊的晶粒封裝 Download PDFInfo
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Description
此處所述的實施例大致上關於堆疊的晶粒封裝,特別關於包含導電柱之重疊堆疊的晶粒封裝。
由於晶片/封裝面積及高度(諸如其它物理及電參數也不例外)典型上有嚴苛的限制,所以,行動產品(例如行動電話、智慧型電話、平板電腦、等等)在可利用空間上非常受限。因此,降低系統機板(例如印刷電路板PCB)上電子組件的尺寸是相當重要(例如,封裝的晶片或是離散裝置、整合的被動裝置(IPD)、表面安裝裝置(SMD)、等等)。
傳統的堆疊電子組件典型上需要相對大的z高度,使它們更難以在行動產品的機殼內適配,特別是當多個晶片、IPD、SMD需要被組裝及/或堆疊於彼此的頂部上時。此外,如同大部份的電子組件一般,通常有增加電性能的目標。
有二種現有的封裝方法用於高晶粒數堆疊晶粒封裝。
一方法形成線接合式封裝,其中,基底及包覆模會將額外的z高度加至封裝。此外,因為封裝中使用的接線之數目及長度,線接合式封裝典型上性能也受限。
用於高晶粒數堆疊的晶粒封裝之另一現有的封裝方法使用矽穿孔通路(TSV)技術。利用TSV之高晶粒數堆疊的晶粒封裝通常具有相對高的速度。但是,藉由TSV,z高度縮減仍然是困難的。此外,使用TSV技術形成的通路通常消耗矽上有價值的空間。使用TSV技術通常也有相對高的製造成本,使得使月TSV技術來生產高晶粒數堆疊的晶粒封裝更昂貴。習知的16晶粒BGA堆疊晶粒封裝的典型z高度是1.35mm,其中,各晶粒薄至35μm。
10‧‧‧電子組件
11‧‧‧晶粒
12‧‧‧上表面
13‧‧‧導電柱
14‧‧‧導電墊
16‧‧‧球形區
17‧‧‧圓柱區
18‧‧‧邊緣
19‧‧‧電子封裝
20‧‧‧堆疊
21‧‧‧模
22‧‧‧重分佈層
23‧‧‧銲接凸塊
50‧‧‧設備
1300‧‧‧電子設備
圖1是晶粒實例的側視圖。
圖2是具有形成於晶粒上的至少一導電柱之圖1中所示的晶粒實例的側視圖。
圖3是圖2中所示的導電柱之放大側視圖。
圖4是圖2中所示的晶粒之俯視圖。
圖5是包含重疊的電子組件堆疊之封裝的側視圖。
圖6是圖5中所示的封裝的俯視圖。
圖7是圖5及6中所示的封裝之側視圖,其中,重疊堆疊的晶粒被裝納於模中。
圖8是圖7中所示的封裝之側視圖,其中,模的一部份已被移除以曝露重疊堆疊晶粒上的柱。
圖9是圖8中所示的封裝之側視圖,其中,重分佈層設於重疊堆疊晶粒的曝露柱上。
圖10是圖9中所示的封裝之側視圖,其中,銲接凸塊設於重疊堆疊晶粒的重分佈層上。
圖11是圖10中所示的封裝之側視圖,其中,類似增加的封裝倒置且與圖10中所示的封裝上的銲球相對齊。
圖12是流程圖,顯示將堆疊的電子組件重疊以形成電子裝置之方法。
圖13是包含此處所述的電子組件及/或電子封裝之電子設備的方塊圖。
圖14是另一電子設備的側視圖。
下述說明及圖式充份地顯示具體實施例以使習於此技藝者能夠實施它們。其它實施例會將結構、邏輯、電氣、處理、及其它改變併入。某些實施例的部份及特點可以包含於其它實施例的部份及特點中或替代它們。申請專利範圍中揭示的實施例涵蓋這些申請項所有可取得的均等範圍。
例如「水平」等本申請案中使用的方向術語係界定無論晶圓或基底的方向為何都會與晶圓或基底的一般平面或表面相平行的平面。「垂直」一詞意指與上述界定的水平相垂直的方向。例如前「on(在...上)」、「側」(例如在「側壁」中)、「較高」、「較低」、「在...之上」、
及「在...之下」等前置詞係被定義為無論晶圓或基底的方向為何,就一般平面或表面而言是在晶圓或基底的上表面上。
此處說明的電子組件、封裝及方法可以克服與使用線接合封裝技術及TSV技術以形成高晶粒數堆疊晶粒封裝相關的缺點。此外,此處說明的電子組件、封裝及方法會增加高晶粒數堆疊的晶粒封裝之電性能。
此處說明的電子組件、封裝及方法相較於使用習知的TSV技術以形成高晶粒數堆疊的晶粒封裝,可以提供一些優點。
首先,可以取得較小的晶粒至晶粒間隙/間隔。習知的TSV技術通常會產生數十微米的間隙,而此處說明的組件、封裝、及方法可以產生5μm及更小的間隙。此較小的間隙可以降低高晶粒數堆疊晶粒封裝的整體尺寸及厚度。
其次,由於TSV技術必須製造穿過矽週邊區的通路,所以,此處說明的電子組件、封裝及方法的矽使用效率比TSV技術高。這需要(i)使用矽上有價值的空間;及(ii)增加形成高晶粒數堆疊晶粒封裝相關的製造成本,以在矽中製造開口來產生用於通路形成的開口。此處說明的電子組件、封裝及方法不需要任何型式的製造以為了通路而在矽中產生開口。
最後,此處說明的電子組件、封裝及方法可以使用現有的線接合設備以在晶粒的上表面上產生導電柱。能夠使
用現有的線接合設備之此能力可以降低與製造此處說明的電子組件、封裝及方法有關的成本。
此處說明的電子組件、封裝及方法相較於使用習知的基底式線接合技術可以提供一些優點。
首先,此處說明的電子組件、封裝及方法可以提供增進的電性能。由於導電柱比習知的線接合技術中使用的接線更短,所以,電性能更佳。
其次,此處說明的電子組件、封裝及方法的整體尺寸遠小於使用習知的線接合技術之基底式封裝。由於下述而可以降低整體尺寸:(i)可以節省線接合通常要求的基底上的X-Y空間;(ii)可以免除線接合中使用的導線通常要求的額外之包覆模製,而降低z高度;以及(iii)由於不需要線接合,所以,不需要基底。
圖1是舉例說明的晶粒11的側視圖,而圖2是具有形成於晶粒11上的至少一導電柱13以產生電子組件10之圖1中所示的舉例說明的晶粒11實例的側視圖。圖3是圖2中所示的導電柱13的放大側視圖,而圖4是圖2中所示的電子組件10的俯視圖。
圖2-4顯示電子組件10,其包含具有上表面12之晶粒11(或是某些其它形式的電子元件)。電子組件10又包含導電柱13,導電柱13從上表面12延伸,以致於在導電柱13接合晶粒11處之外的它處,導電柱13未由任何其它材料圍繞。
舉例而言,導電柱13可以是數佰μm長。應注意,
導電柱13可能不是如圖式中所示的長寬比一般高(亦即,導電柱13未依比例繪製)。導電柱13之長寬比的範圍實例可以從1至20。
在圖2-4中所示之舉例說明的電子組件10中,晶粒11包含導電墊14以致於導電柱13從晶粒11上的導電墊14延伸。應注意,圖1-4中所示的導電墊14僅是可以包含在晶粒11的上表面12上以用於與導電柱13接合之導體的實例。
此外,導電柱13可能包含接合導電墊14之球形區16以及從球形區16延伸的圓柱區17。應注意,可以慮及用於導電柱13的其它形式。導電柱13的配置及尺寸將部份地取決於電子組件10的整體設計以及與製造導電柱13有關的製造考量(在其它因素中)。
如圖4所示,導電柱13可以是複數個導電柱13之部份,其從上表面12延伸以致於各導電柱13在導電柱13接合晶粒11處之外的它處不會由任何材料圍繞。在圖4中所示之舉例說明的電子組件10中,在接近晶粒11的一邊緣18中,複數個導電柱13成列地對齊。
應注意,複數個導電柱13可以以任何方式配置在晶粒11的上表面12上。舉例而言,複數個導電柱可以以L形、C形、或是多列配置而配置於晶粒11的上表面12上。在晶粒11的上表面12上的複數個導電柱13之配置將部份地取決於電子組件10的整體設計以及與電子組件10製造有關的製造考量(在其它因素中)。
圖5是封裝19的側視圖,其包含類似於圖2-4中所示的電子組件10之電子組件10的重疊堆疊20。圖6是圖5中所示的電子組件10的重疊堆疊之俯視圖。
圖5及6中所示的封裝19包含電子組件10的堆疊20,其中,各電子組件10均包含具有上表面12之晶粒11及複數個導電柱13,複數個導電柱13從上表面12延伸,以致於在堆疊20中的各導電柱13在導電柱13接合晶粒11處之外的它處不會由任何材料圍繞。電子組件10的堆疊20以重疊方式配置,以致於各電子組件10上的複數個導電柱13不會由另一電子組件10遮蓋。
在圖5及6中所示的電子組件10的重疊堆疊中,在接近包含對應的複數個導電柱13之分別的晶粒11的一邊緣處,各電子組件10中的複數個導電柱13成列地對齊。各電子組件10中複數個導電柱13的此配置允許電子組件10的堆疊20以覆瓦配置(shingles configuration)設置。應注意,複數個電子組件10重疊以形成電子組件10的堆疊20之方式將部份地取決於複數個導電柱13如何配置於各分別的晶粒11上。
從各晶粒11延伸的導電柱13可以具有相同或不同的長寬比。此外,在形成電子封裝19之各電子組件10中可以有不同數目的導電柱13。應注意,在電子封裝19的各電子組件10中晶粒11可以是相同的、或是具有不同的尺寸、厚度、材料或功能。
圖7是圖5及6中所示的晶粒11的重疊堆疊20的側
視圖,其中,封裝19被包封於模21中。舉例而言,模21可以圍繞封裝19以及由例如環氧樹脂(在其它型式的材料中)等熱固模製化合物形成。在電子封裝19的某些形式中,在電子組件10的重疊堆疊20中底部晶粒11的底表面可以曝露(或是如圖7所示般未曝露)。
圖8是圖7中所示的電子組件10的重疊堆疊20的側視圖,其中,模21的一部份已被移除以曝露電子封裝19上的複數個導電柱13。舉例而言,藉由研磨而移除模21的一部份,但是,應注意,可以考慮其它的材料移除法。應注意,可以考慮其它形成的封裝19,其中,模21的一部份被移除,以致於最上方的電子組件10中的晶粒11的上表面12曝露。
圖9是圖8中所示的電子封裝19的側視圖,其中,重分佈層22設置於電子組件10的重疊堆疊20中曝露的柱13之上。重分佈層22以任何現有已知或未來發明的任何方式,設置於曝露的柱13之上。此外,重分佈層22的配置將部份地取決於電子封裝19的整體設計中曝露的柱13之位置。
圖10是圖9中所示的電子封裝19的側視圖,其中,銲接凸塊23設置於模21的上表面上的導電重分佈層22上及/或複數個導電柱13中的某些導電柱13的曝露部份上。銲接凸塊23可以以現在已知或未來發現之任何方式設置於導電重分佈層22上及/或曝露的柱13上。此外,銲接凸塊13將部份地取決於封裝19的整體設計中重分佈
層22的配置及曝露柱13的位置。
圖11是圖10中所示的封裝19之側視圖,其中,類似增加的封裝30倒置且與圖10中所示的重疊堆疊晶粒上的銲接凸塊23對齊。應注意,雖然封裝19顯示為已準備好用於組裝至圖11中的第二類似增加的封裝30,但是,可以使用銲接凸塊23(或是某些型式的導體)以將封裝19安裝至很多其它型式的電子裝置(例如基底、晶粒、晶片組、主機板、卡及/或其它型式的電子裝置中不同型式的電子封裝)。此外,晶粒11或封裝20可薄化(例如藉由研磨)以降低電子組件10及/或封裝20的高度。也可以考慮增加的電子裝置(例如類似於電子封裝19的另一封裝)安裝至電子封裝19的另一側以形成多電子封裝的堆疊之實例。
圖12是流程圖,顯示舉例說明的方法[1200]。方法[1200]包含[1210],其藉由將導電柱13接合至晶粒11的上表面12以致於導電柱13從上表面12延伸且在導電柱13接合晶粒11處之外的它處不由任何材料圍繞(請參見圖2及3),以形成電子組件10。在方法[1200]的某些形式中,將導電柱13接合至晶粒11的上表面12包含使用線接合技術以將導電柱13接合至晶粒11的上表面12,但是,可以使用現在已知或未來發現的任何技術以將導電柱13接合至晶粒11的上表面12。
如圖4中所示,[1210]形成電子組件10包含將複數個導電柱13接合至晶粒11的上表面12,以致於導電柱
13從上表面12延伸且在導電柱13接合晶粒11處之外的它處不由任何材料圍繞。在方法[1200]的某些形式中,將複數個導電柱13接合至晶粒11的上表面12包含在接近晶粒11的邊緣18處將複數個導電柱13成列地對齊。
如圖5及6所示,方法[1200]可以又包含[1220],其將增加的電子組件10堆疊至電子組件10以形成電子封裝19。各增加的電子組件10包含具有上表面12之晶粒11及複數個導電柱13,複數個導電柱13從上表面12延伸,以致於各導電柱13在導電柱13接合晶粒11處之外的它處不由任何材料圍繞。形成封裝19的電子組件10以重疊配置設置,以致於各電子組件10上的複數個導電柱13未由另一電子組件10遮蓋。
方法[1200]可以又包含[1230],其形成圍繞電子組件10的堆疊20之模21(請參見圖7)。此外,方法[1200]包含[1240],移除模21的一部份以使導電柱13曝露經過模21的上表面(請參見圖8)。
如圖9所示,方法[1200]可以又包含[1250],其在模21的上表面上形成導電重分佈層22。在方法[1200]的某些形式中,導電重分佈層22接合複數個導電柱13的各導電柱13的曝露部份。方法也包含[1260],在導電重分佈層22上或是複數個導電柱13中的某些導電柱13之曝露部份上形成銲接凸塊23(請參見圖10)。
取決於使用封裝19之應用,方法[1200]可以又包含[1270],其電子封裝倒置,以及,[1280],其電子封裝19
上的銲接凸塊23接合至另一電子裝置(請參見例如圖11中的封裝30)。當封裝19用於特定應用時,封裝19要接合的電子裝置之型式將部份地取決於所需的封裝19之功能。
應注意,雖然很多電子組件10及封裝19係以經過切粒的方式顯示,但是,此處所述的方法、電子組件10及封裝19可以是晶圓形式、列形式或任何可以提升電子組件10及電子組件10的重疊堆疊20的製造之其它形式。由方法、電子組件10及封裝19採用的形式將部份地取決於製造成本以及電子組件10及封裝19的整體所需功能。
圖13是包含此處所述的電子組件10及/或電子封裝19之電子設備1300的方塊圖。電子設備1300僅為使用此處所述的電子組件10及封裝19的形式之電子設備的一實例。電子設備1300的實例包含但不限於個人電腦、平板電腦、行動電話、遊戲機、MP3或其它數位音樂播放器、等等。在本實例中,電子設備1300包括資料處理系統,該資料處理系統包含系統匯流排1302以將電子設備1300的各種組件耦合。系統匯流排1302提供電子設備1300的各種組件之間的通訊鏈結且可實施成單一匯流排、多匯流排的組合、或是以任何其它適當方式實施。
電子設備1300耦合至系統匯流排1302。電子設備1300包含任何電路或電路的組合。在一實施例中,電子設備1300包含任何型式的處理器1312。如同此處使用般,「處理器」意指任何型式的計算電路但不侷限於微處
理器、微控制器、複雜指令集計算(CISC)微處理器、精簡指令集計算(RISC)微處理器、超長指令字(VLIW)微處理器、圖形處理器、數位訊號處理器(DSP)、多核心處理器、或任何其它型式的處理器或處理器電路。
包含於電子設備1300中的其它型式的電路可為客製電路、特定應用積體電路(ASIC)、等等,舉例而言,用於例如行動電話、平板電腦、膝上型電腦、雙向無線電裝置、及類似的電子設備等無線裝置中的一或更多電路(例如通訊電路1314)。IC可以執行任何其它形式的功能。
電子設備1300也包含外部記憶體1320,其接著包含一或更多適於特定應用的記憶體元件,例如隨機存取記憶體(RAM)形式的主記憶體1322、一或更多硬碟機1324、及/或一或更多處理例如光碟(CD)、快閃記憶體卡、數位影音光碟(DVD)等可卸式媒體1326之驅動器。
電子設備1300也包含顯示裝置1316、一或更多揚音器1318、及鍵盤和/或控制器1330,控制器1330可包含滑鼠、軌跡球、觸控螢幕、語音辨識裝置、或任何其它允許系統使用者對電子設備1300輸入及接收資訊之裝置。
圖14顯示舉例說明的設備50,其包含第一晶粒11’及在第一晶粒11’的表面上的第一導電柱17’。第二晶粒11”配置成相鄰第一晶粒11’及第二導電柱17”在第二晶粒11”的表面上。
模材料21在各分別表面、以及在各分別的第一導電柱17’和第二導電柱17”處接觸第一晶粒11’及第二晶粒11”。模材料21呈現遍及各第一導電柱17’及第二導電柱17”的特徵流體,以及,其中,模材料是一體的。
在設備50的某些舉例說明的形式中,設備50又包含後續的晶粒11”’以及在後續的晶粒11”’的表面上之後續的導電柱17”’。模材料21也呈現遍及後續的導電柱17”’之特徵餘留流體。
用於形成導電柱的傳統技術典型上包含鑽穿模材料而到達晶粒,以及,接著以導電材料填充鑽孔而形成導電柱。藉由使模材料流動圍繞已經存在的導電柱而形成的配置將呈現特殊的物理特徵,這些特殊的物理特徵是可偵測的且與藉由鑽製且事後填充而形成的配置不同。這些物理差異性的實例包含,但不限於,模聚合物或其它材料的微結構差異,其圍繞導電柱彎曲成為來自流體之餘留人造物。
另一示例物理差異包含模21中的流體標誌及銲接線。銲接線代表模製構件中的光學以及機械缺陷。銲接線典型上出現在聚合物流體在注入製程期間匯集的區域中。
另一舉例說明的物理差異包含溝槽。溝槽是表面缺陷,其中,「環」出現在模製構件的表面,主要圍繞針點閘及同心地散佈於模製物上。噴射也是類似於溝槽的缺陷,其中,粗糙或無光澤線出現在始於閘及散佈於整個構件上之模製物的表面。
另一舉例說明的物理差異實例包含空氣條紋。在模製構件中的空氣條紋在模製構件的表面上呈現無光澤的、銀色的或白色的線(條紋)。通常在接近圓頂、肋、模製構件的壁厚度變化之處可以發現它們。它們也可以出現在接近澆注口處或是接近雕刻處及凹陷處。
為了更佳地顯示此處揭示的電子組件、電子封裝及方法,於此提供非限定的實施例清單。
實例1包含電子組件,電子組件包括包含上表面的晶粒及導電柱,導電柱從上表面延伸以致於在導電柱接合晶粒處之外的它處,導電柱未由任何其它材料圍繞。
實例2包含實例1的電子組件,其中,晶粒包含導電墊,以致於導電柱從晶粒上的導電墊延伸。
實例3包含實例1-2中任一實例的電子組件,其中,導電柱包含與導電墊接合的球形區以及從球形區延伸的圓柱區。
實例4包含實例1-3中任一實例的電子組件,其中,導電柱是複數個導電柱的部份,複數個導電柱從上表面延伸以致於在導電柱接合晶粒處之外的它處,導電柱未由任何其它材料圍繞。
實例5包含實例1-4中任一實例的電子組件,其中,複數個導電柱在接近晶粒的一邊緣處成列地對齊。
實例6包含電子封裝,電子封裝包含電子組件堆疊,其中,各電子組件包括具有上表面的晶粒及複數個導電柱,複數個導電柱從上表面延伸以致於在導電柱接合晶粒
處之外的它處,各導電柱未由任何其它材料圍繞,以及,其中,電子組件的堆疊以重疊配置設置,以致於在各電子組件上的複數個導電柱未由另一電子組件遮蓋。
實例7包含實例6的電子封裝,其中,在各電子組件中的複數個導電柱在接近分別晶粒的一邊緣處成列地對齊,分別晶粒包含對應的複數個導電柱。
實例8包含實例6-7中任一實例的電子封裝,又包含圍繞電子組件堆疊的模。
實例9包含實例6-8中任一實例的電子封裝,其中,模的一部份被移除以使導電柱曝露經過模的上表面。
實例10包含實例6-9中任一實例的電子封裝,又包含在模的上表面上的導電重分佈層,導電重分佈層接合複數個導電柱中的各導電柱之曝露部份。
實例11含實例6-10中任一實例的電子封裝,又包含銲接凸塊,銲接凸塊接合模的上表面上的導電重分佈層或是複數個導電柱中的某些導電柱的曝露部份。
實例12含實例6-11中任一實例的電子封裝,又包含倒置之增加的電子封裝,以及,藉由連接電子封裝上的銲接凸塊與增加的電子封裝上的銲接凸塊,增加的電子封裝與電子封裝相接合。
實例13是方法,包含藉由將導電柱13接合至晶粒的上表面以致於導電柱從上表面延伸且在導電柱接合晶粒處之外的它處不由任何材料圍繞,以形成電子組件。
實例14包含實例13的方法,其中,將導電柱接合至
晶粒的上表面包含使用線接合技術以將導電柱接合至晶粒的上表面。
實例15包含實例13-14中任一實例的方法,其中,形成電子組件包含將複數個導電柱接合至晶粒的上表面,以致於導電柱從上表面延伸且在導電柱接合晶粒處之外的它處不由任何材料圍繞。
實例16包含實例13-15中任一實例的方法,其中,將複數個導電柱接合至晶粒的上表面包含在接近晶粒的邊緣處將複數個導電柱成列地對齊。
實例17包含實例13-16中任一實例的方法,又包含將增加的電子組件堆疊至電子組件以形成電子封裝,其中,各增加的電子組件包含具有上表面之晶粒及複數個導電柱,複數個導電柱從上表面延伸,以致於各導電柱在導電柱接合分別的晶粒處之外的它處不由任何材料圍繞,以及,其中,複數個電子組件以重疊配置設置,以致於各電子組件上的複數個導電柱未由另一電子組件遮蓋。
實例18包含實例13-17中任一實例的方法,又包含形成圍繞電子組件堆疊的模。
實例19包含實例13-18中任一實例的方法,又包含移除模的一部份以使導電柱曝露經過模的上表面。
實例20包含實例13-19中任一實例的方法,又包含在模的上表面上形成導電重分佈層,其中,導電重分佈層接合複數個導電柱中的各導電柱的曝露部份,以及,在導電重分佈層上或是複數個導電柱中的某些導電柱之曝露部
份上形成銲接凸塊。
實例21包含實例13-20中任一實例的方法,又包含將電子封裝倒置,以及,將電子封裝上的銲接凸塊接合至另一電子裝置。
實例22包含設備實例,其包含第一晶粒及在第一晶粒表面上的第一導電柱。第二晶粒配置成相鄰第一晶粒及第二導電柱在第二晶粒的表面上。模材料在各分別表面、以及在各分別的第一導電柱和第二導電柱處接觸第一晶粒及第二晶粒。模材料呈現遍及各第一導電柱及第二導電柱的特徵流體,以及,其中,模材料是一體的。
實例23包含實例22的設備,又包含後續的晶粒以及在後續的晶粒的表面上之後續的導電柱。模材料也呈現遍及後續的導電柱之特徵餘留流體。
本概述是要提供本標的之非限定性實例,不是要提供排它的或竭盡性的說明。所包含之詳細說明係提供關於方法的進一步資訊。
上述詳細說明包含參考形成其一部份的附圖。圖式以舉例說明的方式顯示可實施本發明之特定實施例。這些實施例於此也稱為「實例」。這些實例包含所示或所述以外的元件。但是,本發明人也慮及僅提供所示及說明的那些元件之實例。此外,本發明人也考慮到使用所示或所述、或是與特定實例(或是其一或更多態樣)有關、或是與此處所示或說明的其它實施例有關(或是其一或更多態樣)的那些元件之任何結合或替代(或其一或更多態樣)之實
例。
在本文件中,也使用專利文獻使用的「非定冠詞(a或an)」等詞以包含一或一個以上,與「至少之一」或是「一或更多」的任何情形或使用相獨立。在本文獻中,「或」一詞用以意指非排它的,或是,除非另外指明,否則「A或B」包含「A但非B」、「B但非A」、以及「A及B」。在本文獻中,使用「包含(including)」、及「其中(in which)」等詞作為「包括(comprising)」及「其中(wherein)」等分別的詞之一般英文的同義。而且,在後附的申請專利範圍中,「包含(including)」及「包括(comprising)」是開放式的,亦即,除了包含請求項中此詞之後列出的元件以外的元件之系統、裝置、物品、成份、配方、或處理仍被視為落在該請求項的範圍之內。此外,在後附的申請專利範圍中,「第一」、「第二」、及「第三」等等僅作為標示,而非要對它們的物件施加數字要求。
上述說明是說明性的而非限制性的。舉例而言,上述實例(或是其一或更多態樣)可以彼此結合地使用。具有此技藝的一般技術者在審視上述說明之後,可以使用其它實施例。
提供摘要以符合37.C.F.R.§1.72(b),以使讀者能夠快速地確定技術揭示的本質。須瞭解,摘要不應用以解釋或限定申請專利範圍的範圍或意義。
而且,在上述詳細說明中,各式各樣的特點可以分組
在一起以使揭示流暢。這不應被解釋為未請求的揭示特點對任何請求項是必要的。反而,發明的標的在於少於特定揭示的實施例之所有特點。因此,後附的申請專利範圍於此併入詳細說明中,以各請求項代表它自己分別的實施例,以及,可以慮及這些實施例以不同的結合或更換而彼此結合。應參考後附的申請專利範圍、及伴隨這些請求項的全均等範圍,而決定發明的範圍。
10‧‧‧電子組件
11‧‧‧晶粒
12‧‧‧上表面
13‧‧‧導電柱
14‧‧‧導電墊
16‧‧‧球形區
17‧‧‧圓柱區
18‧‧‧邊緣
19‧‧‧電子封裝
20‧‧‧堆疊
Claims (17)
- 一種電子組件,包括:晶粒,包含上表面;及複數個導電柱,從該上表面延伸以致於除了在該複數個導電柱接合該晶粒處之外,該複數個導電柱未被任何其它材料圍繞,其中複數個該電子組件用以被堆疊來重疊配置設置,以致於在各電子組件上的該複數個導電柱未由另一電子組件遮蓋。
- 如申請專利範圍第1項之電子組件,其中,該晶粒包含導電墊,以致於該複數個導電柱之各者從該晶粒上的該導電墊延伸。
- 如申請專利範圍第2項之電子組件,其中,該導電柱包含與該導電墊接合的球形區以及從該球形區延伸的圓柱區。
- 如申請專利範圍第1項之電子組件,其中,該複數個導電柱在接近該晶粒的一邊緣處成列地對齊。
- 一種電子封裝,包括:電子組件堆疊,其中,各電子組件包括具有上表面的晶粒及複數個導電柱,該複數個導電柱從該上表面延伸以致於在該導電柱接合該晶粒處之外的它處,各導電柱未由任何其它材料圍繞;以及,其中,該電子組件堆疊以重疊配置設置,以致於在各電子組件上的該複數個導電柱未由另一電子組件遮蓋。
- 如申請專利範圍第5項之電子封裝,其中,在各電子組件中的該複數個導電柱在接近包含對應的該複數個導電柱之該各別晶粒的一邊緣處成列地對齊。
- 如申請專利範圍第5項之電子封裝,又包括圍繞該電子組件堆疊的模。
- 如申請專利範圍第7項之電子封裝,其中,該模的一部份被移除以使該導電柱曝露經過該模的上表面。
- 如申請專利範圍第8項之電子封裝,又包括在該模的上表面上的導電重分佈層,該導電重分佈層接合該複數個導電柱中的各導電柱之曝露部份。
- 如申請專利範圍第9項之電子封裝,又包括銲接凸塊,該銲接凸塊接合該模的上表面上的該導電重分佈層或是該複數個導電柱中的某些導電柱的曝露部份。
- 如申請專利範圍第10項之電子封裝,又包括倒置之多增加的電子封裝,以及,藉由連接該電子封裝上的銲接凸塊與該增加的電子封裝上的銲接凸塊,該多增加的電子封裝與該電子封裝相接合。
- 一種用於形成晶粒封裝的方法,包括:藉由將導電柱接合至晶粒的上表面以致於該導電柱從該上表面延伸且在該導電柱接合該晶粒處之外的它處不由任何材料圍繞,以形成電子組件,其中,形成電子組件包含將複數個導電柱接合至晶粒的上表面,以致於該複數個導電柱從該上表面延伸且除了在該複數個導電柱接合該晶粒處之外不被任何材料圍繞, 其中,將複數個導電柱接合至晶粒的上表面包含在接近該晶粒的邊緣處將該複數個導電柱成列地對齊,及其中該方法又包括:將多增加的電子組件堆疊至該電子組件以形成電子封裝,其中,多增加的電子組件的各者包含具有上表面之晶粒及複數個導電柱,該複數個導電柱從該上表面延伸,以致於除了各導電柱在該導電柱接合該各別的晶粒處之外不被任何材料圍繞,以及,其中,該複數個電子組件以重疊配置設置,以致於該各電子組件上的該複數個導電柱未由另一電子組件遮蓋。
- 如申請專利範圍第12項的方法,其中,將導電柱接合至晶粒的上表面包含使用線接合技術以將該導電柱接合至該晶粒的該上表面。
- 如申請專利範圍第12項的方法,又包括形成圍繞該電子組件堆疊的模。
- 如申請專利範圍第14項的方法,又包括移除該模的一部份以使該複數個導電柱曝露經過該模的上表面。
- 如申請專利範圍第15項的方法,又包括:在該模的該上表面上形成導電重分佈層,其中,該導電重分佈層接合該複數個導電柱中的各導電柱的曝露部份;以及,在該導電重分佈層上或是該複數個導電柱中的某些導電柱之曝露部份上形成銲接凸塊。
- 如申請專利範圍第16項的方法,又包括:將該電子封裝倒置;以及, 將該電子封裝上的銲接凸塊接合至另一電子裝置。
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CN105830212A (zh) | 2016-08-03 |
EP3017463A1 (en) | 2016-05-11 |
US10256208B2 (en) | 2019-04-09 |
JP2016535463A (ja) | 2016-11-10 |
BR112015021244A2 (pt) | 2018-05-08 |
US10629561B2 (en) | 2020-04-21 |
EP3017463A4 (en) | 2017-03-01 |
US20190189585A1 (en) | 2019-06-20 |
WO2016049940A1 (en) | 2016-04-07 |
TW201626522A (zh) | 2016-07-16 |
US20170278821A1 (en) | 2017-09-28 |
KR20160055100A (ko) | 2016-05-17 |
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