BR112015021244A2 - pacote de matrizes empilhadas sobrepostas com colunas verticais - Google Patents

pacote de matrizes empilhadas sobrepostas com colunas verticais

Info

Publication number
BR112015021244A2
BR112015021244A2 BR112015021244A BR112015021244A BR112015021244A2 BR 112015021244 A2 BR112015021244 A2 BR 112015021244A2 BR 112015021244 A BR112015021244 A BR 112015021244A BR 112015021244 A BR112015021244 A BR 112015021244A BR 112015021244 A2 BR112015021244 A2 BR 112015021244A2
Authority
BR
Brazil
Prior art keywords
stacked
vertical columns
matrix package
package
matrix
Prior art date
Application number
BR112015021244A
Other languages
English (en)
Inventor
Yang Cheng
Zhao Junfeng
Original Assignee
Intel Coproration
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Coproration filed Critical Intel Coproration
Publication of BR112015021244A2 publication Critical patent/BR112015021244A2/pt

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    • H—ELECTRICITY
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Packaging Frangible Articles (AREA)
  • Ceramic Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
BR112015021244A 2014-10-03 2014-10-03 pacote de matrizes empilhadas sobrepostas com colunas verticais BR112015021244A2 (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2014/088096 WO2016049940A1 (en) 2014-10-03 2014-10-03 Overlapping stacked die package with vertical columns

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BR112015021244A2 true BR112015021244A2 (pt) 2018-05-08

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US (2) US10256208B2 (pt)
EP (1) EP3017463A4 (pt)
JP (1) JP2016535463A (pt)
KR (1) KR20160055100A (pt)
CN (1) CN105830212A (pt)
BR (1) BR112015021244A2 (pt)
TW (1) TWI578466B (pt)
WO (1) WO2016049940A1 (pt)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BR112015021244A2 (pt) 2014-10-03 2018-05-08 Intel Coproration pacote de matrizes empilhadas sobrepostas com colunas verticais
US10204884B2 (en) 2016-06-29 2019-02-12 Intel Corporation Multichip packaging for dice of different sizes
CN107579061B (zh) 2016-07-04 2020-01-07 晟碟信息科技（上海）有限公司 包含互连的叠加封装体的半导体装置
CN107611099B (zh) * 2016-07-12 2020-03-24 晟碟信息科技（上海）有限公司 包括多个半导体裸芯的扇出半导体装置
CN109643702A (zh) * 2016-10-01 2019-04-16 英特尔公司 电子器件封装
WO2018086395A1 (zh) * 2016-11-08 2018-05-17 华进半导体封装先导技术研发中心有限公司 半导体存储器、半导体存储模块及其制作方法
DE112016007539T5 (de) * 2016-12-23 2019-09-12 Intel Corporation VERTIKALES, GESTAPELTES CHIP-GRÖßENORDNUNG BONDDRAHTGEHÄUSE MIT ANWENDUNGSSPEZIFISCHEM INTEGRIERTEM SCHALTUNGS-DIE AUF DEM STAPEL UND VERFAHREN ZUM HERSTELLEN DESSELBEN
US11056465B2 (en) 2016-12-29 2021-07-06 Intel Corporation Semiconductor package having singular wire bond on bonding pads
KR20190093193A (ko) 2016-12-30 2019-08-08 인텔 아이피 코포레이션 마이크로전자 디바이스 내의 적층 다이를 위한 인터커넥트 구조
CN108695284A (zh) * 2017-04-07 2018-10-23 晟碟信息科技（上海）有限公司 包括纵向集成半导体封装体组的半导体设备
WO2019132933A1 (en) * 2017-12-28 2019-07-04 Intel Corporation Multi-die, vertical-wire package-in-package apparatus, and methods of making same
TWI700798B (zh) 2018-07-12 2020-08-01 南韓商三星電子股份有限公司 半導體封裝
KR102652872B1 (ko) 2018-09-04 2024-04-02 삼성전자주식회사 반도체 패키지
US11158608B2 (en) * 2019-09-25 2021-10-26 Powertech Technology Inc. Semiconductor package including offset stack of semiconductor dies between first and second redistribution structures, and manufacturing method therefor
US11086539B2 (en) 2019-10-21 2021-08-10 Sandisk Technologies Llc Mapping consecutive logical block addresses to consecutive good blocks in memory device
KR102664356B1 (ko) * 2019-11-29 2024-05-13 양쯔 메모리 테크놀로지스 씨오., 엘티디. 칩 패키지 구조체 및 그 제조 방법
KR102643424B1 (ko) * 2019-12-13 2024-03-06 삼성전자주식회사 반도체 패키지
KR20220010323A (ko) 2020-07-17 2022-01-25 삼성전자주식회사 반도체 패키지
JP2022112923A (ja) 2021-01-22 2022-08-03 キオクシア株式会社 半導体装置およびその製造方法

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5061989A (en) * 1990-03-22 1991-10-29 Transcomputer, Inc. Mechanical translator for semiconductor chips
US6348728B1 (en) 2000-01-28 2002-02-19 Fujitsu Limited Semiconductor device having a plurality of semiconductor elements interconnected by a redistribution layer
US6717245B1 (en) * 2000-06-02 2004-04-06 Micron Technology, Inc. Chip scale packages performed by wafer level processing
US6701614B2 (en) 2002-02-15 2004-03-09 Advanced Semiconductor Engineering Inc. Method for making a build-up package of a semiconductor
US7262074B2 (en) * 2002-07-08 2007-08-28 Micron Technology, Inc. Methods of fabricating underfilled, encapsulated semiconductor die assemblies
JP4105996B2 (ja) 2003-07-25 2008-06-25 株式会社新川 ワイヤボンディング方法
JP2006173232A (ja) * 2004-12-14 2006-06-29 Casio Comput Co Ltd 半導体装置およびその製造方法
US7317249B2 (en) * 2004-12-23 2008-01-08 Tessera, Inc. Microelectronic package having stacked semiconductor devices and a process for its fabrication
KR101133123B1 (ko) 2005-03-25 2012-04-06 삼성테크윈 주식회사 와이어 본딩 방법 및 그에 의한 반도체 패키지
US7656017B2 (en) * 2006-12-18 2010-02-02 Stats Chippac Ltd. Integrated circuit package system with thermo-mechanical interlocking substrates
US20080164605A1 (en) * 2007-01-08 2008-07-10 United Microelectronics Corp. Multi-chip package
TW200830520A (en) 2007-01-12 2008-07-16 United Microelectronics Corp Multi-chip package
WO2009022991A1 (en) * 2007-08-14 2009-02-19 Agency For Science, Technology And Research Die package and method for manufacturing the die package
WO2010041356A1 (ja) * 2008-10-07 2010-04-15 株式会社村田製作所 電子部品モジュールの製造方法
US20100193930A1 (en) * 2009-02-02 2010-08-05 Samsung Electronics Co., Ltd. Multi-chip semiconductor devices having conductive vias and methods of forming the same
IT1397716B1 (it) * 2009-02-05 2013-01-24 Lumson Spa Contenitore con decorazioni in rilievo
KR20100114421A (ko) 2009-04-15 2010-10-25 삼성전자주식회사 적층 패키지
US8446017B2 (en) 2009-09-18 2013-05-21 Amkor Technology Korea, Inc. Stackable wafer level package and fabricating method thereof
TW201205760A (en) 2010-06-08 2012-02-01 Mosaid Technologies Inc Multi-chip package with pillar connection
KR101686553B1 (ko) 2010-07-12 2016-12-14 삼성전자 주식회사 반도체 패키지 및 패키지 온 패키지
JP5803276B2 (ja) * 2011-05-26 2015-11-04 富士通株式会社 半導体装置の製造方法
EP2766931B1 (en) * 2011-10-03 2021-12-01 Invensas Corporation Stub minimization for wirebond assemblies without windows
US8637352B2 (en) * 2011-11-22 2014-01-28 Stmicroelectronics Pte Ltd. Ball grid array to pin grid array conversion
CN102790042B (zh) * 2012-07-12 2015-11-18 日月光半导体制造股份有限公司 半导体芯片堆叠构造
JP6297553B2 (ja) * 2012-07-17 2018-03-20 クリック アンド ソッファ インダストリーズ、インク． ワイヤ配線構造を形成する方法
US9111896B2 (en) 2012-08-24 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package semiconductor device
US9536850B2 (en) 2013-03-08 2017-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package having substrate with embedded metal trace overlapped by landing pad
CN106229270A (zh) * 2013-03-29 2016-12-14 日月光半导体制造股份有限公司 堆迭式封装及其制造方法
BR112015021244A2 (pt) 2014-10-03 2018-05-08 Intel Coproration pacote de matrizes empilhadas sobrepostas com colunas verticais

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