TWI576974B - Semiconductor device and method for manufacturing semiconductor device - Google Patents

Semiconductor device and method for manufacturing semiconductor device Download PDF

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Publication number
TWI576974B
TWI576974B TW100128611A TW100128611A TWI576974B TW I576974 B TWI576974 B TW I576974B TW 100128611 A TW100128611 A TW 100128611A TW 100128611 A TW100128611 A TW 100128611A TW I576974 B TWI576974 B TW I576974B
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Taiwan
Prior art keywords
rewiring
semiconductor device
opening
width
surface layer
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TW100128611A
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English (en)
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TW201214641A (en
Inventor
右田達夫
江澤弘和
山下創一
志摩真也
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東芝股份有限公司
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Publication of TW201214641A publication Critical patent/TW201214641A/zh
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    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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Description

半導體裝置及半導體裝置之製造方法
本實施形態一般係關於半導體裝置及半導體裝置之製造方法者。
關聯申請案之參照
本申請案享受於2010年8月31日申請之日本專利申請案號2010-195026之優先權之利益，且此日本專利申請案之全部內容援用於本申請案。
為達成半導體裝置之高積體化與高功能化，要求動作速度之提高及記憶體之大容量化。與其相一致於半導體基板上之再配線形成製程中亦要求10 μm間距以下之細微之再配線。
若使再配線之間距細微化，則有於再配線之間產生漏電之虞。又，於再配線上進一步形成配線或凸塊等之時之範圍減少，而藉由光微影法之加工變得困難。
根據實施形態，設置有半導體基板、再配線、表面層。半導體基板中形成有配線及焊墊電極。再配線形成於上述半導體基板上。表面層之特徵在於寬度較上述再配線寬。
以下，一面參照圖式一面對實施形態之半導體裝置及半導體裝置之製造方法進行說明。再者，本發明並不限定於該等實施形態。
(第1實施形態)
圖1(a)~(e)、圖2(a)~(d)、圖3(a)~(c)、圖4(a)~(b)、圖5(a)~(b)及圖6(a)~(b)係表示第1實施形態之半導體裝置之製造方法之剖面圖。
於圖1(a)中，於基材層1上形成有焊墊電極2a及配線2b，並且以覆蓋焊墊電極2a及配線2b之方式形成有保護膜3。又，於保護膜3中形成有使焊墊電極2a露出之開口部3a及使配線2b之一部分露出之開口部3b。
再者，作為基材層1，例如可使用形成有邏輯電路或DRAM(Dynamic Random Access Memory，動態隨機存取記憶體)等積體電路之半導體基板。又，焊墊電極2a及配線2b之材料例如可使用Al或以Al作為主成分之金屬。又，保護膜3之材料例如可使用氧化矽膜或氮氧化矽膜或氮化矽膜等無機絕緣體。
其次，如圖1(b)所示，藉由將感光性樹脂等塗佈於保護膜3上，而於保護膜3上形成緩衝層4。再者，作為緩衝層4之材料，例如可使用聚醯亞胺系樹脂。為使晶圓應力降低，亦可使用硬化溫度較聚醯亞胺系樹脂低之丙烯酸系樹脂或苯酚系樹脂。
其次，如圖1(c)所示，藉由使用光微影技術，於緩衝層4上形成使焊墊電極2a及配線2b之一部分分別露出之開口部4a、4b。
其次，如圖1(d)所示，藉由使用濺鍍、電鍍、CVD(chemical vapor deposition，化學氣相沈積)、ALD(Atomic Layer Deposition，原子層沈積)或蒸鍍等方法，於焊墊電極2a、配線2b、保護膜3及緩衝層4上形成底層障壁金屬膜5。再者，作為底層障壁金屬膜5，例如可使用Ti與其上之Cu之積層構造。再者，亦可使用TiN、TiW、W、Ta、Cr、Co等材料代替Ti。亦可使用Al、Pd、Au、Ag等材料代替Cu。
其次，如圖1(e)所示，藉由使用旋轉塗佈法等方法，於底層障壁金屬膜5上形成抗蝕劑膜6。
其次，如圖2(a)所示，藉由進行抗蝕劑膜6之曝光及顯影，而於抗蝕劑膜6上形成開口部6a~6c。再者，可將開口部6a配置於焊墊電極2a上，將開口部6b配置於緩衝層4上，將開口部6c配置於配線2b上。
其次，如圖2(b)所示，藉由利用電解電鍍將第1導體埋入開口部6a~6c中，而隔著底層障壁金屬膜5於焊墊電極2a、緩衝層4及配線2b上分別形成再配線7a~7c。進而，藉由利用電解電鍍將第2之導體埋入開口部6a~6c中，而於再配線7a~7c上分別形成表面層8a~8c。此處，再配線7a可使用於與焊墊電極2a之連接。再配線7c可使用於與配線2b之連接。再配線7b可使用於緩衝層4上之再配線7a、7c之引導等。
再者，表面層8a~8c可使用耐蝕刻性較再配線7a~7c高之材料，較理想的是相對於表面層8a~8c之再配線7a~7c之蝕刻選擇比為1以上。例如，再配線7a~7c之材料可選自Cu或以Cu為主成分之金屬，且表面層8a~8c之材料可選自Ni、Mn、Ta、Zn、Cr、Co、Sn及Pb中之至少任一者。又，較理想的是，再配線7a~7c之寬度為60 μm以下、較佳為40 μm以下，更佳為20 μm以下。
其次，如圖2(c)所示，藉由灰化等方法，將底層障壁金屬膜5上之抗蝕劑膜6去除。
其次，如圖2(d)所示，藉由蝕刻再配線7a~7c之側面，以寬度較表面層8a~8c狹窄之方式使再配線7a~7c細線化。
此處，藉由表面層8a~8c使用耐蝕刻性較再配線7a~7c高之材料，而與表面層8a~8c相比可促進再配線7a~7c之側面之蝕刻。因此，可以分別沿著再配線7a~7c而分別自再配線7a~7c於寬度方向伸出之方式於再配線7a~7c上形成表面層8a~8c。
此時，亦可藉由與蝕刻再配線7a~7c之側面同時地蝕刻底層障壁金屬膜5，而去除再配線7a~7c之周圍之底層障壁金屬膜5。因此，較佳為表面層8a~8c與底層障壁金屬膜5均具有蝕刻比。
其次，如圖3(a)所示，藉由將感光性樹脂等塗佈於配線2b、緩衝層4及表面層8a~8c上，而於配線2b、緩衝層4及表面層8a~8c上形成緩衝層9。再者，作為緩衝層9之材料，例如可使用聚醯亞胺系樹脂。為降低晶圓應力，亦可使用硬化溫度較聚醯亞胺系樹脂低之丙烯酸系樹脂或苯酚系樹脂。
其次，如圖3(b)所示，藉由使用光微影技術，而於緩衝層9上形成使焊墊電極2a上之表面層8a及配線2b之一部分分別露出之開口部9a、9b。
其次，如圖3(c)所示，藉由使用濺鍍、電鍍、CVD、ALD或蒸鍍等方法，而於配線2b、保護膜3、緩衝層4、9及表面層8a上形成底層障壁金屬膜10。再者，作為底層障壁金屬膜10，例如可使用Ti與其上之Cu之積層構造。
其次，如圖4(a)所示，藉由旋轉塗佈法等方法，而於底層障壁金屬膜10上形成抗蝕劑膜11。
其次，如圖4(b)所示，藉由進行抗蝕劑膜11之曝光及顯影，而於抗蝕劑膜11上形成使焊墊電極2a上之表面層8a露出之開口部11a。
其次，如圖5(a)所示，藉由以電解電鍍將障壁層12及焊錫層13、14依次埋入開口部11a中，而隔著底層障壁金屬膜10於表面層8a上形成突出電極。再者，例如，障壁層12之材料可使用Ni，焊錫層13之材料可使用Cu，焊錫層14之材料可使用Sn。
其次，如圖5(b)所示，藉由灰化等方法，而去除底層障壁金屬膜10上之抗蝕劑膜11。
其次，如圖6(a)所示，將包含障壁層12及焊錫層13、14之突出電極作為遮罩，蝕刻底層障壁金屬膜10，藉此去除包含障壁層12及焊錫層13、14之突出電極之周圍之底層障壁金屬膜10。
其次，如圖6(b)所示，藉由對焊錫層13、14進行回焊，使焊錫層13、14合金化，且於障壁層12上形成包含合金焊錫層15之突出電極。
以上之步驟可於基材層1為晶圓之狀態下進行。而且，於以上之步驟之後，藉由將該晶圓個片化，可切出半導體晶片。
此處，藉由使再配線7a~7c細線化，可一面抑制再配線7a~7c之間之漏電，一面使再配線7a~7c之間距細微化，並且藉由於再配線7a~7c上分別形成寬度分別較再配線7a~7c寬之表面層8a~8c，可擴大於再配線7a上形成開口部9a時之範圍。
又，藉由與蝕刻去除再配線7a~7c之周圍之底層障壁金屬膜5同時地進行再配線7a~7c之細線化，可抑制步驟數之增大。
再者，於上述之實施形態中，對使用焊錫球作為突出電極之方法進行了說明，但亦可使用鎳凸塊、金凸塊或銅凸塊等。又，於上述之實施形態中，對使用Ti與Cu之積層構造作為底層障壁金屬膜5、10之方法進行了說明，但亦可以單體使用Ti或Cu，且既可使用Cr、Pt、W等作為單體，亦可使用該等金屬之積層構造。
又，作為突出電極之接合方法，既可使用焊錫接合或合金接合等金屬接合，亦可使用ACF(Anisotropic Conductive Film，異方性導電膜)接合、NCF(Nonconductive Film，非導電性膠膜)接合、ACP(Anisotropic Conductive Paste，異方性導電膏)接合、NCP(Nonconductive Paste，非導電性黏著劑)接合等。
(第2實施形態)
圖7係表示第2實施形態之半導體裝置之概略構成之剖面圖。
於圖7中，於緩衝層21上隔著底層障壁金屬膜22形成有再配線23，於再配線23上形成有表面層24。
再者，作為緩衝層21之材料，例如可使用聚醯亞胺系樹脂。為降低晶圓應力，亦可使用硬化溫度較聚醯亞胺系樹脂低之丙烯酸系樹脂或苯酚系樹脂。又，作為底層障壁金屬膜22，例如可使用Ti與其上之Cu之積層構造。再者，亦可使用TiN、TiW、W、Ta、Cr、Co等材料代替Ti。亦可使用Al、Pd、Au、Ag等材料代替Cu。
表面層24可使用耐蝕刻性較再配線23高之材料。例如，再配線23之材料可為Cu，表面層24之材料為可選自Mn、Ta、Ni、Zn、Cr、Co、Sn及Pb中之至少任一種。
又，再配線23之剖面形狀可為頂部寬度B較底部寬度A狹窄之梯形形狀。表面層24之剖面形狀可為頂部寬度D較底部寬度C狹窄之梯形形狀。再者，因使再配線23及表面層24之剖面形狀為梯形形狀，故可使埋入有再配線23及表面層24之抗蝕開口部之剖面形狀為倒梯形形狀。
此處，將表面層24之寬度設定為較再配線23之底部寬度A寬。又，較佳為滿足∣A-B∣>∣C-D∣之關係。例如，可設定為：再配線23之厚度為5 μm、底部寬度A為4 μm、頂部寬度B為3 μm。可設定為：表面層24之厚度為0.1 μm、底部寬度C為5 μm、頂部寬度D為4.98 μm。此時，∣A-B∣為1 μm、∣C-D∣為0.02 μm。
此處，藉由使再配線23之剖面形狀為頂部寬度B較底部寬度A狹窄之梯形形狀，可使再配線23與其基底之密接強度增大，且可抑制再配線23之剝落，並且實現再配線23之細微化。
又，藉由將表面層24之寬度設定為較再配線23之底部寬度A寬，可使再配線23於俯視觀察時由於表面層24而觀察不到。因此，即便於晶圓面內或晶圓之間再配線23之側面之傾斜角產生偏差之情形時，亦可使自上表面照射光時之反射光之亮度均勻化。因此，於使用如此之反射光進行外觀檢查或尺寸測長之情形時，可降低誤判良品而判定為缺陷之錯誤檢測或由於配線端之錯誤識別而導致之錯誤測長，從而可使品質管理之精度提高。
對本發明之若干實施形態進行了說明，但該等實施形態係作為示例而提示者，並不意圖對發明之範圍進行限定。該等新穎實施形態可以其他各種之形態實施，且於不脫離發明之主旨之範圍內可進行各種省略、置換、變更。該等實施形態或其變形包含於發明之範圍或主旨中、並且包含於申請專利範圍所記載之發明及其均等之範圍內。
1．．．基材層
2a．．．焊墊電極
2b．．．配線
3．．．保護膜
3a．．．開口部
3b．．．開口部
4．．．緩衝層
4a．．．開口部
4b．．．開口部
5．．．底層障壁金屬膜
6．．．抗蝕劑膜
6a．．．開口部
6b．．．開口部
6c．．．開口部
7a．．．再配線
7b．．．再配線
7c．．．再配線
8a．．．表面層
8b．．．表面層
8c．．．表面層
9．．．緩衝層
9a．．．開口部
9b．．．開口部
10．．．底層障壁金屬膜
11．．．抗蝕劑膜
11a．．．開口部
12．．．障壁層
13．．．焊錫層
14．．．焊錫層
15．．．合金焊錫層
21．．．緩衝層
22．．．底層障壁金屬膜
23．．．再配線
24．．．表面層
A．．．底部寬度
B．．．頂部寬度
C．．．底部寬度
D．．．頂部寬度
圖1(a)~(e)係表示第1實施形態之半導體裝置之製造方法之剖面圖。
圖2(a)~(d)係表示第1實施形態之半導體裝置之製造方法之剖面圖。
圖3(a)~(c)係表示第1實施形態之半導體裝置之製造方法之剖面圖。
圖4(a)~(b)係表示第1實施形態之半導體裝置之製造方法之剖面圖。
圖5(a)~(b)係表示第1實施形態之半導體裝置之製造方法之剖面圖。
圖6(a)~(b)係表示第1實施形態之半導體裝置之製造方法之剖面圖。
圖7係表示第2實施形態之半導體裝置之概略構成之剖面圖。
1．．．基材層
2a．．．焊墊電極
2b．．．配線
3．．．保護膜
3a．．．開口部
3b．．．開口部
4．．．緩衝層
4a．．．開口部
4b．．．開口部
5．．．底層障壁金屬膜
6．．．抗蝕劑膜

Claims (20)

  1. 一種半導體裝置，其特徵在於包括：半導體基板，其中形成有配線及焊墊電極；再配線，其形成於上述半導體基板上；表面層，其形成於再配線上，其頂部寬度為20μm以下；及突出電極，其形成於上述表面層上；其中上述表面層之頂部寬度較上述再配線之底部寬度大，上述突出電極之寬度較上述頂部寬度小。
  2. 如請求項1之半導體裝置，其中相對於上述表面層之上述再配線之蝕刻選擇比為1以上。
  3. 如請求項1之半導體裝置，其中上述再配線之材料為Cu，且上述表面層之材料為選自Mn、Ta、Ni、Zn、Cr、Co、Sn及Pb中之至少任一種。
  4. 如請求項1之半導體裝置，其中上述再配線之頂部寬度較底部寬度狹窄。
  5. 如請求項4之半導體裝置，其中上述表面層之寬度較上述再配線之底部寬度寬。
  6. 如請求項1之半導體裝置，其中於上述半導體基板中形成有積體電路。
  7. 如請求項1之半導體裝置，其包括：保護膜，其係以覆蓋上述配線及焊墊電極之方式而形成於上述半導體基板上；第1開口部，其係形成於上述保護膜，且使上述焊墊 電極露出；及第2開口部，其係形成於上述保護膜，且使上述配線之一部分露出。
  8. 如請求項7之半導體裝置，其包括：第1緩衝層，其係形成於上述保護膜上；第3開口部，其係形成於上述第1緩衝層，且使上述焊墊電極經由上述第1開口部而露出；及第4開口部，其係形成於上述第1緩衝層，且使上述配線之一部分經由上述第2開口部而露出。
  9. 如請求項8之半導體裝置，其中上述保護膜為無機絕緣體，且上述第1緩衝層為樹脂。
  10. 如請求項9之半導體裝置，其中上述樹脂係選自聚醯亞胺系樹脂、丙烯酸系樹脂及苯酚系樹脂。
  11. 如請求項9之半導體裝置，其進而包括形成於上述第1緩衝層與上述再配線之間之第1底層障壁金屬膜。
  12. 如請求項11之半導體裝置，其中上述再配線包括：第1再配線，其係經由上述第1開口部及上述第3開口部而與上述焊墊電極連接；第2再配線，其係經由上述第2開口部及上述第4開口部而與上述焊墊電極連接；及第3再配線，其係形成於上述第1緩衝層上。
  13. 如請求項12之半導體裝置，其包括：第2緩衝層，其係形成於上述第1再配線、上述第2再配線及上述第3再配線上；及 第5開口部，其係形成於上述第2緩衝層，且使上述第1再配線之表面層露出。
  14. 如請求項13之半導體裝置，其進而包括經由上述第5開口部而與上述第1再配線之表面層連接之突出電極。
  15. 如請求項14之半導體裝置，其中上述突出電極包含合金焊錫層。
  16. 如請求項14之半導體裝置，其進而包括形成於上述第2緩衝層與上述突出電極之間之第2底層障壁金屬膜。
  17. 如請求項16之半導體裝置，其中上述第2緩衝層為樹脂。
  18. 如請求項17之半導體裝置，其中上述樹脂係選自聚醯亞胺系樹脂、丙烯酸系樹脂及苯酚系樹脂。
  19. 一種半導體裝置之製造方法，其特徵在於包括以下步驟：於半導體基板上形成底層障壁金屬膜；於上述底層障壁金屬膜上形成具有開口部之抗蝕劑圖案；於上述底層障壁金屬膜上形成再配線；於上述再配線上形成頂部寬度為20μm以下之表面層；藉由蝕刻上述再配線之側面，而使寬度較上述表面層狹窄；及於上述表面層上形成突出電極；其中上述表面層之頂部寬度較上述再配線之底部寬度 大，上述突出電極之寬度較上述頂部寬度小。
  20. 如請求項19之半導體裝置之製造方法，其中藉由與蝕刻上述再配線之側面同時地蝕刻上述底層障壁金屬膜，而去除上述再配線之周圍之上述底層障壁金屬膜。
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