TWI470756B - 半導體結構及形成半導體裝置的方法 - Google Patents

半導體結構及形成半導體裝置的方法 Download PDF

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TWI470756B
TWI470756B TW99125029A TW99125029A TWI470756B TW I470756 B TWI470756 B TW I470756B TW 99125029 A TW99125029 A TW 99125029A TW 99125029 A TW99125029 A TW 99125029A TW I470756 B TWI470756 B TW I470756B
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layer
conductive pad
conductive
pillar
substrate
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TW99125029A
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English (en)
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TW201133743A (en
Inventor
Ming Hong Tseng
Chen Shien Chen
Chen Cheng Kuo
Chih Hua Chen
Ching Wen Hsiao
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Taiwan Semiconductor Mfg Co Ltd
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Publication of TW201133743A publication Critical patent/TW201133743A/zh
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Description

半導體結構及形成半導體裝置的方法
本發明係有關於一種半導體裝置，特別是有關於一種半導體裝置的凸塊底部金屬化結構。
自從積體電路發明後，由於各種電子元件(即，電晶體、二極體、電阻、電容等)的積體密度的持續改良，半導體產業歷經了持續的快速成長。對於大部分而言，這種改良係由於不斷地降低最小特徵尺寸，這可使更多的元件被整合於一既定的面積中。
在過去的幾十年，可以看到許多半導體封裝上的改變，衝擊了整個半導體產業。引進表面黏著技術(surface mount technology，SMT)以及球柵陣列(ball grid array，BGA)封裝為各種IC裝置的高產能組裝的重要步驟，同時可降低印刷電路板的銲墊間距。傳統上，封裝後的IC具有基本上以細的金線連接晶粒的金屬墊之間的構造，且電極係從成形後的樹脂封裝延伸而出。另一方面，某些CSP(Chip Scale Package)或BGA封裝依賴銲墊提供晶粒與基材之間的電性接觸，基材為例如封裝基材、印刷電路板(PCB)、其他晶粒/晶圓等等。其他的CSP或BGA封裝利用銲球或銲墊形成於一導電柱體上，依靠銲料結合而達成結構的整體性。構成內連線的不同層通常具有不同的熱膨脹係數(CTE)，因此在結合區域由於熱膨脹係數的差異造成相對大的應力，而經常造成斷裂。
本發明的一較佳實施例提供一種半導體結構，包括一基材以及一柱體，基材包括一導電墊，該導電墊具有一第一寬度，柱體係電性耦接於該導電墊，該柱體具有一第二寬度，其中該第一寬度比該第二寬度大了大約6微米或6微米以上。
本發明的另一較佳實施例提供一半導體結構，其包括一基材以及一柱體，基材包括一導電墊，該導電墊具有一第一寬度，柱體係電性耦接於該導電墊，該柱體具有一第二寬度，其中該導電墊朝側向延伸而超過該柱體大約3微米或3微米以上的距離。
本發明也提供了一種形成半導體裝置的方法，該方法包括下列步驟：提供一基材，其具有一導電墊，該導電墊具有一第一外邊界；在該基材以及該導電墊上形成一鈍化層，該導電墊的至少一部份是暴露在外；以及形成一導電柱體，電性接觸於該導電墊，該導電墊具有一第二外邊界，從平面觀看，該第二外邊界與該第一外邊界相距至少3微米。
為了讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖示，作詳細說明如下。
以下詳細說明本發明的實施例的製作及使用。需瞭解的是這些實施例提供了許多啟發性的概念，可應用於各種特定的情況中。此處所探討的特定的實施例只是用於表示以特定的方式製作及使用該實施例，而並非用於限制本發明。
此處所探討的實施例是與使用於半導體裝置中凸塊底部金屬化結構(UBM)有關。如以下所探討，使用凸塊底部金屬化結構(UBM)是用於將一基材附著於另一基材，其中每一基材可以是晶粒、晶圓、印刷電路板、封裝基材等，而達成晶粒附著於晶粒、晶圓附著於晶圓、晶粒或晶圓附著於印刷電路板或封裝基材等。在該等實施例中，相同的元件係給予相同的符號。
第1圖為一基材100的平面圖，該實施例的基材100具有外部接點102。基材100的外表面係由一保護層104所覆蓋，例如聚亞醯胺(polyimide)層，以保護基材免於受環境污染。在保護層104中形成開口106，其具有一寬度WPadOpen ，而暴露出下方的導電墊108，導電墊108具有一寬度WPad 。
在第1圖中也顯示了一UBM 110的輪廓，UBM 110具有一寬度WUBM 。UBM 110可以是例如銅或其他導電材料的柱體結構，其提供了與下方的導電墊108的電性連接。UBM 110可以再連接至另一基材，例如晶粒、晶圓、印刷電路板、封裝基材等。
雖然產業的趨勢是如以上所探討的使裝置越來越小，但是尺寸的減小在某些區域會產生應力而可能使裝置失效。例如，形成半導體裝置時，UBM 110的寬度WUBM 與下方導電墊108的寬度WPad 的差異很小，例如2微米或更小，這樣可能會對鈍化層(未圖示，參照以下的圖式)及/或保護層104施加足夠的應力，而造成其中之一或兩者產生破裂。與現在的趨勢相反，當WUBM 與WPad 之間的差增加至6微米或更大(例如在每一方向朝側向延伸3微米)而非縮小WUBM 與WPad 之間的差異時，可以減低應力，而且可以減低及/或消除鈍化層及/或保護層的斷裂。
第2～6圖表示形成第1圖的本發明的實施例的半導體裝置的各種中間步驟。參照第2圖，其表示本實施例中，在基材202的一部份形成電路系統204。基材202可以包括例如塊狀矽(bulk silicon)、摻雜或無摻雜、或絕緣上覆矽(SOI)基材的主動層。一般而言，SOI基材包括一半導體材料(例如矽)形成於一絕緣層上。該絕緣層可以是例如埋層氧化層(buried oxide layer，BOX)或矽氧化層。該絕緣層係提供於一基材上，典型是一矽基材或一玻璃基材。也可以使用其他的基材，例如多層基材或梯度基材(gradient substrate)。
形成於基材202的電路系統204可以是適用於特殊用途的任何形態的電路系統。在一實施例中，電路系統204包括形成於基材202上的多個電子裝置，並具有一或多個介電層覆蓋於該等電子裝置上。在介電層之間可形成金屬層，用於在該等電子裝置之間傳遞訊號。電子裝置可形成於一或多個介電層上。
例如，電路系統204可包括不同的N型的金屬氧化半導體(NMOS)裝置以及/或P型的金屬氧化半導體(PMOS)裝置，例如電晶體、電容器、電阻、二極體、光二極體、保險絲等。對於熟習此技藝之人士而言可以理解上述例子只是用於圖示，以便對一些圖示的實施例做更進一步的說明，但並非用於限制本發明，對於一已知的用途而言也可以使用其他的電路系統。
第2圖表示一層間介電層(ILD層)208。該ILD層208可以用低K值的材料以已知的適當方法形成。該低K值的材料可以是例如磷矽玻璃(PSG)、硼磷矽玻璃(BPSG)、氟矽玻璃(FSG)、SiOx Cy 、旋塗式玻璃(SOG)、旋塗式聚合物、碳矽材料、上述該等物質的化合物、上述該等物質的複合物或上述該等物質的組合等。該已知的適當方法可以是例如旋轉塗佈法、化學氣相沈積法(CVD)、電漿輔助化學氣相沈積法(PECVD)。需注意的是ILD層208可包含複數個介電層。
接點，例如接點210是穿過ILD層208以提供與電路系統204的電性接觸。接點208可以藉由使用例如微影技術將光阻材料沈積於ILD層208並圖案化，而使ILD層208的一部份暴露而成為接點210。蝕刻製程，例如非等向性乾蝕刻，可用於在ILD層208上產生開口。該開口可形成擴散阻障層(diffusion barrier layer)及/或黏著層做為襯層(未圖示)，並以導電性材料充填。在一實施例中，擴散阻障層包括一或多層的TaN、Ta、TiN、Ti、CoW等，而導電性材料包括銅、鎢、鋁、銀以及該等物質的組合等，藉此形成如第2圖所示的接點210。
在ILD層208上形成一或多個金屬間介電層(IMD層)212以及相關的金屬化層(未圖示)。一般而言，該一或多個IMD層212以及相關的金屬化層係用於電路系統204彼此之間的連接並提供一外部連接。IMD層212可以由低K值的材料，例如FSG以PECVD技術或高密度電漿化學氣相沈積法(HDPCVD)等形成，也可以包括中間蝕刻終止層。接點214由最上層的IMD層提供，以提供外部電性連接。
需注意的是一或多個蝕刻終止層(未圖示)可設於相鄰的介電層之間，例如ILD層208與IMD層212。一般而言，蝕刻終止層在形成貫孔及/或接點時提供了終止蝕刻製程的機制。蝕刻終止層係形成於介電物質上，並與相鄰的層具有不同的蝕刻選擇比，例如下方的半導體基材202、上方的ILD層208以及上方的IMD層212。在一實施例中，蝕刻終止層可由SiN、SiCN、SiCO、CN以及該等物質的組合而形成，由CVD或PECVD技術沈積形成。
保護層216可由介電材料形成，例如SiN，電漿輔助氧化物(PEOX)、電漿輔助SiN(PE-SiN)、電漿輔助未摻雜矽玻璃(PE-USG)等，並使最上層的IMD層212的表面圖案化，以提供接點214上方的開口，以保護下方膜層免於環境污染。因此，導電墊218係形成於保護層216的上方並經圖案化。導電墊218提供了與UBM結構的電性連接，例如與銅柱體結構的電性連接，可以做為外部連接。導電墊218可由任何適當的導電性材料形成，例如銅、鎢、鋁、銀、或該等物質的組合等。
一或多個鈍化層，例如鈍化層220係形成於導電墊218上並將之圖案化，如第2圖所示。鈍化層220可由介電材料以任何適當的方法形成。介電材料可以是例如PE-USG、PE-SiN或其組合等。適當的方法可以是例如CVD、PVD等。在一實施例中，鈍化層具有大約10000埃至15000埃的厚度。在一實施例中，鈍化層220包括一多層結構，包含厚度750埃的SiN、6500埃的PE-USG以及6000埃的PE-SiN。
熟習此技藝之人士瞭解單一層的導電墊及鈍化層只是用於舉例說明。如此，其他的實施例可包括任意數量的導電層及/或鈍化層。而且，必須瞭解的是可使用一或多個導電層可以做為重分佈層(redistribution layer)，以提供所需的接腳或球的佈局。
可使用任何適當的製程以形成上述的結構，在後面的說明中不再詳細討論。熟習此技藝之人士瞭解以上的敘述是提供了本實施例的一般性的說明，除上述外，尚可尋找其他很多的特徵。例如，其他的電路系統、襯層、阻障層、凸塊底部金屬化特徵等。以上的說明只是提供用於實施例中討論的內容，而非用於限制這些實施例的範圍。
第3圖顯示一保護層310形成於鈍化層220上並經過圖案化。保護層310可以是以任何適當的製程所形成的聚亞醯胺材料，例如以CVD、PVD等形成。在一實施例中，保護層310具有大約2.5微米至大約10微米的厚度。
第4圖表示一順應性的晶種層410沈積於保護層310的表面。晶種層410為一導電性材料的薄層，其有助於在後續的製程中形成較厚的層。在一實施例中，晶種層410可以藉由沈積一薄導電層而形成，例如使用CVD或物理氣相沈積(PVD)法形成Cu、Ti、Ta、TiN、TaN或其組合等的薄層。例如可由PVD製程沈積Ti層而形成一阻障膜，可由PVD製程沈積Cu層而形成一晶種層。
因此，如第4圖所示，本實施例形成一圖案化的遮罩412並形成於晶種層410上。圖案化的遮罩412定義出該導電柱體的側邊界，以便在後續的製程中可以形成，在後面會詳細地說明。圖案化的遮罩412可以是圖案化的光阻遮罩、硬遮罩或兩者的組合等。
第5圖顯示本發明的實施例中形成導電柱體510。導電柱體510可以用任何適當的導電性材料形成，例如包括Cu、Ni、Pt、Al或該等物質的組合等，且可經由任意適當的技術形成，例如PVD、CVD、電化學沈積法(ECD)、分子束磊晶法(MBE)、原子層沈積法(ALD)、電鍍等。必須注意的是在某些實施例中，例如在晶圓的整個表面上沈積了相同大小的層(例如PVD及CVD)，需要實施蝕刻或平坦化製程(例如化學機械研磨(CMP)製程)，以便從圖案化遮罩412上除去多餘的導電性材料。在一實施例中，導電柱體510具有厚度大約在20微米至50微米之間。
第5圖表示在導電柱體510上形成一非必要的(optional)導電性覆蓋層512。如以下的詳細說明所述，銲料形成於導電柱體510上。在焊接製程中，一金屬間化合物層(IMC)(未圖示)可自然地形成於銲料與基材之間的結合處。某些材料可以產生較其他材料的更強、更耐用的IMC層。因此，需要形成一覆蓋層，例如需要導電性覆蓋層512，以提供具有更多所需要的特性的金屬間化合物層(IMC)。例如，在一實施例中，其導電柱體510由銅形成，導電性覆蓋層512由鎳形成。其他可以使用的材料例如Pt、Au、Ag或該等物質的組合等。導電覆蓋層512可經由數種適當的技術形成，例如PVD、CVD、ECD、MBE、ALD、電鍍等。
而且，第5圖也顯示銲料514的形成。在一實施例中，銲料514包括SnPb、高含鉛量材料、Sn基銲料、無鉛銲料或其他適當的導電性材料。
如上所述，在一實施例中，導電柱體510的尺寸及位置相對於導電墊218是有著3微米或3微米以上的距離D。目前已發現，當裝置中的導電墊218側向延伸而超過導電柱體510的外邊界3微米或3微米以上的距離時，可以降低保護層310及/或鈍化層220的應力及破裂。
之後，如第6圖所示，圖案化遮罩412可被移除。在實施例中，圖案化遮罩412係由光阻材料形成，此光阻材料可由例如化學溶液或其他光阻去除製程除去，化學溶液可以是下列成分的混合：乳酸乙酯、苯氧基甲烷、乙酸甲丁酯、乙酸戊酯、鄰甲酚環氧樹脂以及重氮系感光劑(稱為SPR9)。可實施一清洗製程，例如稱為DPP，其為浸泡於磷酸(H3 PO4 )及過氧化氫(H2 O2 )並具有2%的氫氟酸的化學溶液中，或實施其他的清洗製程，以移除晶種層410暴露的部分以及來自鈍化層220表面的污染物。
因此，可以實施回焊製程以及其他適用於特殊用途的半導體後段(BEOL)處理技術。例如，可形成密封膠材，可實施分割製程，用於分割個別的晶粒，可實施晶圓等級或晶粒等級的堆疊等。需注意的是，該等實施例可用於不同的情況。例如，該等實施例可用於晶粒對晶粒的結合、晶粒對晶圓的結合、晶圓對晶圓的結合、晶粒等級的封裝、晶圓等級的封裝等。
需注意的是，其他實施例中，在基材202結合於其他基材(未圖示)之前，銲料不會被置於導電柱體510上。在這些實施例中，銲料可以置於其他的基材上，然後在基材202上的導電柱體510可以與其他基材上的銲料接觸，實施回焊製程而將兩基材焊接在一起。
雖然已經詳述本實施例及其優點，但在不偏離由申請專利範圍所定義的實施例的精神與範疇的情況下，可做各種的變更、取代以及變化。而且本發明的範疇不受到說明書中所敘述實施例的製程、機器、生產以及物品的組合、裝置、方法及步驟所限制。對於熟習此技藝之人士而言，可從現有或未來發展的製程、機器、生產以及物品的組合、裝置、方法及步驟等，根據本發明的實施例達到大體上相同的功效或達到相同的結果。據此，申請專利範圍已經包含了此種製程、機器、生產以及物品的組合、裝置、方法及步驟。此外，每一申請專利範圍構成一實施例，且不同申請專利範圍與實施例的組合是包含於本發明的範疇之內。
100．．．基材
102．．．外部接點
104．．．保護層
106．．．開口
108．．．導電墊
110．．．凸塊底部金屬化結構
202．．．基材
204．．．電路系統
208．．．層間介電層
210．．．接點
212．．．金屬層間介電層
214．．．接點
216．．．保護層
218．．．導電墊
220．．．鈍化層
310．．．保護層
410．．．晶種層
412．．．遮罩
510．．．導電柱體
512．．．導電性覆蓋層
514．．．銲料
D．．．距離
第1圖為本發明實施例的半導體裝置的接觸墊的平面圖。
第2～6圖表示形成一半導體裝置的各種中間步驟，該半導體裝置具有本發明實施例的凸塊底部金屬結構。
202．．．基材
204．．．電路系統
208．．．層間介電層
210．．．接點
212．．．金屬層間介電層
214．．．接點
216．．．保護層
218．．．導電墊
220．．．鈍化層
310．．．保護層
410．．．晶種層
510．．．導電柱體
512．．．導電性覆蓋層
514．．．銲料
D．．．距離

Claims (10)

  1. 一種半導體結構，包括：一基材，包括一導電墊，該導電墊具有一第一寬度；以及一柱體，電性耦接至該導電墊，該柱體具有一第二寬度，其中該第一寬度大於該第二寬度約6微米或6微米以上。
  2. 如申請專利範圍第1項所述之半導體結構，其更包括一材料層，形成於該柱體上，並與該導電墊電性接觸，其中該材料層係由銲料、鎳、鉑、金或銀形成。
  3. 如申請專利範圍第1項所述之半導體結構，其更包括一鈍化層覆蓋於該導電墊的至少一部分，以及一保護層覆蓋於該鈍化層上。
  4. 如申請專利範圍第3項所述之半導體結構，其中該保護層為聚亞醯胺(polyimide)。
  5. 一種半導體結構，包括：一基材，包括一導電墊，該導電墊具有一第一寬度；以及一柱體，電性耦接至該導電墊，該柱體具有一第二寬度，其中該導電墊朝側向延伸而超過該柱體大約3微米或3微米以上的距離。
  6. 如申請專利範圍第5項所述之半導體結構，其更包括一銲料，形成於該柱體上，並與該導電墊做電性接觸。
  7. 如申請專利範圍第5項所述之半導體結構，其更 包括一覆蓋層，形成於該柱體上，其中該覆蓋層係由鎳、鉑、金或銀形成。
  8. 如申請專利範圍第5項所述之半導體結構，其更包括一鈍化層覆蓋於該導電墊的至少一部分，以及一保護層覆蓋於該鈍化層上。
  9. 一種形成半導體裝置的方法，該方法包括下列步驟：提供一基材，其具有一導電墊，該導電墊具有一第一外邊界；在該基材以及該導電墊上形成一鈍化層，且暴露出該導電墊的至少一部份；以及形成一導電柱體，與該導電墊電性接觸，該導電柱體具有一第二外邊界，從平面觀看，該第二外邊界與該第一外邊界相距至少3微米。
  10. 如申請專利範圍第9項所述之形成半導體裝置的方法，其更包括一步驟：形成一材料層於該柱體上，其中該材料層係由銲料、鎳、鉑、金或銀形成。
TW99125029A 2010-03-16 2010-07-29 半導體結構及形成半導體裝置的方法 TWI470756B (zh)

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