TWI552234B - 基板、其製造方法及其應用 - Google Patents

基板、其製造方法及其應用 Download PDF

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TWI552234B
TWI552234B TW103129906A TW103129906A TWI552234B TW I552234 B TWI552234 B TW I552234B TW 103129906 A TW103129906 A TW 103129906A TW 103129906 A TW103129906 A TW 103129906A TW I552234 B TWI552234 B TW I552234B
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Taiwan
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substrate
electrode
doped region
wafer
forming
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TW103129906A
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TW201513235A (zh
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蔡曜駿
許鎮鵬
溫士逸
楊季瑾
胡鴻烈
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財團法人工業技術研究院
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Description

基板、其製造方法及其應用
本揭露是有關於一種基板及其製造方法、及其應用，且特別是有關於一種具有二極體的基板及其製造方法、及其應用。
隨著科技的日新月異，現今行動裝置的需求愈來愈輕薄，所以應用在行動裝置上的電子元件的趨勢也是愈做愈小。然而，當靜電放電(Electro-Static Discharge，ESD)的現象產生時，電子元件會因為靜電放電所產生的突如其來的大電流所影響，而造成所屬系統當機，甚至造成永久性的破壞。
在習知靜電放電防護的技術領域中，常依據不同模式在可能發生靜電放電路徑上加設靜電放電防護元件來疏導靜電放電時所產生的電流。然而，上述靜電放電防護元件會導致其晶片的面積增加，不僅造成製造成本上的負擔，而且亦與現今電子產品輕薄短小的趨勢背道而馳。
本揭露提供一種基板，其包括基材、兩個導體結構以及至少一二極體。兩個導體結構分別從基材的第一表面，經由貫穿基材的兩個穿孔，延伸到基材的第二表面。至少一二極體埋入於所述穿孔其中之一的一側壁的基材中。
本揭露提供一種基板的製造方法，其步驟如下。提供具有第一導電型的基材。於基材中形成兩個穿孔，所述穿孔分別貫穿基材。於所述穿孔其中之一裸露的基材中埋入至少一二極體。於基材中形成兩個導體結構。兩個導體結構分別從基材的第一表面，經由所述穿孔貫穿基材，延伸到基材的第二表面。
本揭露提供一種封裝結構，其包括上述之基板與晶片。晶片配置於基板上。晶片與基板電性連接。
為讓本揭露的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
1、1a、2、3、4、5、6‧‧‧基板
10、20‧‧‧穿孔
40‧‧‧空腔
30、101a、101b、101c、101d‧‧‧開口
100、100a、200、300、400、500、600‧‧‧基材
102、202、302、402、502、602‧‧‧絕緣層
102a、202a、302a、502a、602a‧‧‧絕緣結構
104a、104b、104c、104d、104e、104f、104g、104h、204a、204b、304a、304b、404a、404b、504a、504b、604a、604b‧‧‧第一摻雜區
105、105a、105b、205a、205b、211、305a、305b、405a、405b、505a、505b‧‧‧二極體
106a、106b‧‧‧種層
108、110、208、210、308、310、408、410、508、510、608、610‧‧‧導體結構
108a、108b、110a、110b、208a、208b、210a、210b、308a、308b、310a、310b、508a、508b、510a、510b、608a、608b、610a、610b‧‧‧電極
108c、110c、208c、210c、308c、310c、508c、510c、608c、610c‧‧‧連接部
210、220‧‧‧部分
212‧‧‧第三摻雜區
230‧‧‧導角
240‧‧‧切割道
512a、512b‧‧‧第二摻雜區
700、800‧‧‧晶片
702、802‧‧‧晶片基板
704‧‧‧銲墊
706‧‧‧固晶膠
708‧‧‧導線
804、806‧‧‧凸塊
808‧‧‧透明基板
S1‧‧‧第一表面
S2‧‧‧第二表面
S3‧‧‧第三表面
θ‧‧‧導角
圖1A至圖1E為依照本揭露第一實施例所繪示的基板之製造流程的剖面示意圖。
圖2A為依照本揭露之一實施例所繪示的穿孔形狀的剖面示意圖。
圖2B為依照本揭露之另一實施例所繪示的穿孔形狀的剖面 示意圖。
圖2C為依照本揭露之又一實施例所繪示的穿孔形狀的剖面示意圖。
圖3A至圖3E為本揭露之各種實施例之基板的剖面示意圖。
圖4A為本揭露第二實施例之基板的剖面示意圖。
圖4B為本揭露之另一第二實施例之基板的剖面示意圖。
圖5為本揭露第三實施例之基板的剖面示意圖。
圖6為本揭露第四實施例之基板的剖面示意圖。
圖7為本揭露第五實施例之基板的剖面示意圖。
圖8為本揭露第六實施例之基板的剖面示意圖。
圖9為依照本揭露之一實施例所繪示的封裝結構。
圖10為依照本揭露另一實施例所繪示的封裝結構。
在以下的實施例中，當第一導電型為N型，第二導電型為P型；當第一導電型為P型，第二導電型為N型。在本實施例中，是以第一導電型為P型，第二導電型為N型為例來說明，但本揭露並不以此為限。P型摻雜例如是硼；N型摻雜例如是磷或是砷。
圖1A至圖1E為依照本揭露第一實施例所繪示的基板之製造流程的剖面示意圖。
請參照圖1A，首先，提供基材100。基材100材料例如 為半導體基底或半導體化合物基底。半導體例如是IVA族的原子，例如矽或鍺。半導體化合物例如是IVA族的原子所形成之半導體化合物，例如是碳化矽或是矽化鍺，或是IIIA族原子與VA族原子所形成之半導體化合物，例如是砷化鎵。在一實施例中，基材100可例如是具有第一導電型的基材100，第一導電型可例如是P型，但本揭露並不以此為限。
接著，於基材100上形成圖案化的絕緣層102。具體來說，先於基材100上形成絕緣層(未繪示)。絕緣層覆蓋基材100的第一表面S1、第二表面S2以及兩側面。然後，對絕緣層進行圖案化製程，以形成圖案化的絕緣層102。圖案化的絕緣層102具有多數個開口101a、101b、101c、101d。開口101a、101b裸露出基材100的第一表面S1。開口101c、101d裸露出基材100的第二表面S2。開口101a的位置與開口101c的位置相對應；而開口101b的位置與開口101d的位置相對應。絕緣層的材料可例如是氧化矽、氮化矽、氮氧化矽或其組合，其形成方法可利用化學氣相沈積法來形成。在一實施例中，絕緣層的厚度為100nm至3000nm。
請參照圖1B，以圖案化的絕緣層102為罩幕，對基材100進行等向性蝕刻製程，以形成至少兩個穿孔10、20。在一實施例中，上述等向性蝕刻製程可例如是濕式蝕刻製程，其可例如是使用KOH、NaOH、NH4OH或H3PO4等蝕刻劑來進行。具體來說，等向性蝕刻製程使用的蝕刻劑對於圖案化的絕緣層102與基材 100具有高蝕刻選擇比，因此，蝕刻劑與開口101a、101b、101c、101d所裸露的基材100接觸，使得開口101a與所對應的開口101c之間的部分基材100被移除，以形成穿孔10。同樣地，開口101b與所對應的開口101d之間的部分基材100被移除，以形成穿孔20。
另外，透過等向性蝕刻製程的蝕刻條件(Etch Recipe)的控制，穿孔10、20之兩側壁的形狀可以是各種的形狀。上述穿孔10、20之輪廓可依不同元件的需求來調整，但本揭露並不以此為限。舉例來說，穿孔10、20之輪廓為沙漏形(如圖1B所示)或倒梯形(如圖2A所示)或領結形(如圖2C所示)時，其可適用於發光二極體(LED)製程。穿孔10、20之兩側壁的形狀為I字形時(如圖2B所示)，其可適用於三維積體電路(3D IC)晶片製程。
請參照圖1C，對穿孔10、20之兩側壁進行摻雜製程，以於基材100a中形成具有第二導電型的第一摻雜區104a、104b。第一摻雜區104a、104b可例如是分別位於穿孔10、20之兩側壁的基材100a中。摻雜製程可例如是利用高溫爐管製程來形成。在一實施例中，基材100中的摻質例如是硼；而第一摻雜區104a、104b所植入的摻質例如是磷或是砷。
請參照圖3A至圖3E，以下針對本揭露各種實施例之第一摻雜區提供詳細的描述。第一摻雜區104c可例如是位於穿孔20的一側壁的基材100a中(如圖3A所示)，而穿孔20之另一側壁上則具有絕緣結構102a。另外，第一摻雜區104d可位於同一穿孔 20的兩側壁的基材100a中(如圖3B所示)。第一摻雜區104e亦可配置於穿孔10之至少一側壁與第一摻雜區104f同時位於同一穿孔20之兩側壁的基材100a中(如圖3C所示)。當第一摻雜區104e位於穿孔10之一側壁的基材100a中時，穿孔10之另一側壁上則具有絕緣結構102a。此外，第一摻雜區104g、104h可例如是分別位於穿孔20的一側壁的一部分的基材100a中(如圖3D、圖3E所示)，端看其需求而定，但本揭露並不以此為限。當第一摻雜區104g、104h分別位於穿孔20之一側壁的一部分的基材100a中時，穿孔20之一側壁的其他部分以及穿孔20之另一側壁上具有絕緣結構102a。
在對應圖3A至圖3E的實施例中，第一摻雜區104c、104d、104e、104f、104g或104h僅位於穿孔10、20其中之一，或僅位於穿孔10、20其中之一的部分側壁的基材100a中，則在進行摻雜製程之前，可先於穿孔10、20之兩側壁上形成圖案化的罩幕層(未繪示)。之後，以圖案化的罩幕層與圖案化的絕緣層102為罩幕，進行摻雜製程。摻雜製程例如是離子植入製程或是高溫擴散摻雜製程。如果是利用高溫擴散掺雜製程來達成掺雜時，則可用HF(氫氟酸)或乾蝕刻的方法，來去除高溫掺雜時在穿孔側壁所形成的薄氧化層。
請回頭參照圖1C，第一摻雜區104a與其鄰近的部分基材100a構成二極體105a；第一摻雜區104b與其鄰近的部分基材100a構成二極體105b。換言之，二極體105a、105b埋入於基材100a 中。二極體105a、105b具有稽納二極體(Zener Diode)的功效，其可當作後續封裝製程中的靜電放電防護元件(ESD Protection Device)，以防止所屬的電子元件被靜電放電所產生的大電壓所影響，而損傷元件。
請參照圖1D，於穿孔10、20之兩側壁上形成圖案化的種層(Seed layer)107a、107b。具體來說，先在穿孔10、20之兩側壁、第一表面S1與第二表面S2的部分圖案化的絕緣層102上形成種層(未繪示)。然後，對種層進行圖案化製程，暴露部分圖案化的絕緣層102，以形成圖案化的種層107a、107b。圖案化的種層107a覆蓋穿孔10之兩側壁、第一表面S1與第二表面S2的部分圖案化的絕緣層102。圖案化的種層107b覆蓋穿孔20之兩側壁、第一表面S1與第二表面S2的部分圖案化的絕緣層102。圖案化的種層107a與107b彼此分離，其可避免後續封裝製程中的晶片的陽極與陰極電性連接，而導致所屬的電子元件短路。在一實施例中，種層的材料可例如是金屬材料，金屬材料可例如是金(Au)、銀(Ag)、銅(Cu)或其組合，其形成方法可利用電子束蒸鍍法((E-beam Evaporation))、濺鍍法(Sputter)或電鍍(Electro-plating)法來形成。在一實施例中，種層的厚度為10nm至10000nm。
此外，在一實施例中，圖案化的種層107a、107b與基材100a之間可分別具有阻障層106a、106b，其可避免圖案化的種層107a、107b的金屬材料擴散至基材100a中。阻障層106a、106b 的材料可例如是金屬或金屬氮化物。金屬或金屬氮化物可例如是鎳(Ni)、鉑(Pt)、鈦(Ti)、氮化鈦(TiN)、氮化鉭(TaN)、鎢(W)、鈦鎢(TiW)或其組合，其可利用電子束蒸鍍法((E-beam Evaporation))、濺鍍法(Sputter)、電鍍(Electro-plating)法或化學氣相沈積法來形成。圖案化的種層107a、107b的材料與阻障層106a、106b的材料可以互相搭配以獲得最好的阻障效果。舉例來說，當圖案化的種層107a、107b的材料為金(Au)時，則可搭配鎳(Ni)、鈀(Pd)、鉑(Pt)或鈦(Ti)來當作阻障層106a、106b的材料；圖案化的種層107a、107b的材料為銀(Ag)時，則可搭配氮化鈦(TiN)或氮化鉭(TaN)來當作阻障層106a、106b的材料；圖案化的種層107a、107b的材料為銅(Cu)時，則可搭配鎢(W)、鈦鎢(TiW)或鈦(Ti)來當作阻障層106a、106b的材料，但本揭露並不以此為限。在一實施例中，圖案化的種層107a、107b與基材100a之間亦可省略上述阻障層106a、106b。
請參照圖1E，形成導體結構108與導體結構110。導體結構108包括第一電極108a、第二電極108b以及連接部108c。連接部108c貫穿基材100a，其使得第一電極108a與第二電極108b電性連接。同樣地，導體結構110包括第一電極110a、第二電極110b以及連接部110c。連接部110c貫穿基材100a，使得第一電極110a與第二電極110b電性連接。導體結構108與導體結構110彼此電性隔絕，其可避免後續封裝製程中的晶片的陽極與陰極電性連接，而導致所屬的電子元件短路。另外，第一電極108a、110a 與第二電極108b、110b必須具有足夠厚度，以承受所屬電子元件的電流量(約莫0.02至20安培)，以避免產生電流過大而導致電子元件損壞的問題。在一實施例中，導體結構108、110的材料可例如是金屬材料，金屬材料可例如是金(Au)、銀(Ag)、銅(Cu)或其組合，其形成方法可利用電鍍法、蒸鍍法或塗佈印刷來形成。在一實施例中，第一電極108a、110a的厚度為1μm至100μm。第二電極108b、110b的厚度為1μm至100μm。
圖1E為本揭露第一實施例之基板的剖面示意圖。
請參照圖1E，本揭露第一實施例之基板1包括：基材100a、圖案化的絕緣層102、兩個二極體105a、105b以及兩個導體結構108、110。兩個導體結構108、110分別從基材100a的第一表面S1，經由穿孔10、20，貫穿基材100a，延伸到第二表面S2。導體結構108包括：第一電極108a、第二電極108b以及連接部108c。導體結構110包括：第一電極110a、第二電極110b以及連接部110c。第一電極108a、110a分別配置於基材100a的第一表面S1上。第二電極108b、110b分別配置於基材100a的第二表面S2上。連接部108c配置於第一電極108a與第二電極108b之間，使得第一電極108a與第二電極108b電性連接。連接部110c配置於第一電極110a與第二電極110b之間，使得第一電極110a與第二電極110b電性連接。圖案化的絕緣層102配置於基材100a的第一表面S1上，位於基材100a與第一電極108a、110a之間，圖案化的絕緣層102還配置於基材100a的第二表面S2上，位於 基材100a與第二電極108b、110b之間。圖案化的絕緣層102使得基材100a與第一電極108a、110a以及第二電極108b、110b電性隔絕。
二極體105a、105b分別埋入於基材100a中。二極體105a與導體結構108的連接部108c接觸；而二極體105b與導體結構110的連接部110c接觸。二極體105a包括具有第一導電型的部分基材100a以及具有第二導電型的第一摻雜區104a。二極體105b包括具有第一導電型的部分基材100a以及具有第二導電型的第一摻雜區104b。第一摻雜區104a位於基材100a中，與導體結構108的連接部108c接觸。第一摻雜區104b位於基材100a中，與導體結構110的連接部110c接觸。在各種實施例中，第一摻雜區的位置、數量具有各種可能(如圖3A至圖3E所示)，端看其需求而定，但本揭露並不以此為限。舉例來說，如圖3D所示，基板1a的第一摻雜區104g位在穿孔20的一側壁的一部分的基材100a中。連接部108c、110c之輪廓可以是沙漏形、I字形、倒梯形或領結形(分別如圖1B、2A、2B與2C所示)。連接部108c、110c之輪廓可依不同元件的需求來調整，但本揭露並不以此為限。
在以下的實施例中，相同或相似的元件、構件、層以相似的元件符號來表示。舉例來說，圖案化的絕緣層102與圖案化的絕緣層202、302、402、502、602皆為相同或相似的構件；導體結構108與導體結構208、308、408、508、608亦為相同或相似的構件。於此不再逐一贅述。
圖4A為本揭露第二實施例之基板的剖面示意圖。圖4B為本揭露之另一第二實施例之基板的剖面示意圖。
請參照圖4A，本實施例與圖1E之基板1相似，不同之處在於圖4A之基板2包括基材200。基材200包括主體部210與邊緣部220。邊緣部220位於主體部210的邊緣。邊緣部220例如是切割道。邊緣部220具有導角230，其由第三表面S3與第二表面S2的連接處所構成。導角230的夾角θ為鈍角。在一實施例中，導角的夾角θ可例如是100度至170度。導角230可藉由每一基板2之間的切割道240上的開口30切割而成或是利用乾、濕蝕刻方法來形成。上述導角230可例如是鈍角。在後續封裝製程中，由於上述導角230的夾角θ為鈍角，其可解決基材200與下方的凸塊(Bump)進行貼合時，第二表面S2的第二電極208b、210b過度擠壓而外溢至角落，進而導致所屬電子元件漏電或短路的問題。在一實施例中，更可在第三表面S3下的部分基材200中形成具有第二導電型的第三摻雜區212，使得第三摻雜區212與其鄰近的部分基材200構成二極體211。二極體211亦具有稽納二極體的功效，以防止漏電流的發生。但本揭露不限於此，在其他實施例中，亦可利用噴塗或印刷的方式在基板2的第三表面S3上形成絕緣結構202a(如圖4B所示)，以防止漏電流的發生。絕緣結構202a的材料可例如是矽氧樹脂(Silicone)。
圖5為本揭露第三實施例之基板的剖面示意圖。
請參照圖5，本實施例與圖1E之基板1相似，不同之處 在於圖5之基板3更包括絕緣結構302a分別配置於連接部308c、310c之兩側壁與基材300之間。絕緣結構302a具有防止電荷擊穿(punch through)的功效。當圖5之基材300例如當作次載具(Submount)時，其所屬的電子元件不僅可以防止電荷擊穿，而且還具備靜電放電防護的作用之雙重保護的功效。在一實施例中，絕緣結構302a的材料可例如是氧化矽、氮化矽、氮氧化矽或其組合，其形成方法可利用化學氣相沈積法來形成。在一實施例中，絕緣結構302a的厚度為100nm至3000nm。
圖6為本揭露第四實施例之基板的剖面示意圖。
請參照圖6，本實施例與圖1E之基板1相似，不同之處在於圖6之基板4具有空腔(Cavity)40。二極體405a、405b埋入於空腔40底部的基材400中。由於圖5之基材400具有空腔40，因此，當基材400例如做為次載具時，除了具有靜電放電防護的作用之外，其可減少所連接的發光二極體元件之側向光。如此一來，不僅可減少黃暈(Yellowish Halo)問題，在空腔40的側壁上塗佈反射鏡亦可提升所連接的發光二極體元的光學效率。
圖7為本揭露第五實施例之基板的剖面示意圖。
請參照圖7，本實施例與圖1E之基板1相似，不同之處在於圖7之基板5還包括具有第一導電型的第二摻雜區512a、512b。第二摻雜區512a位於具有第二導電型的第一摻雜區504a與導體結構508的連接部508c之間。第二摻雜區512b位於具有第二導電型的第一摻雜區504b與導體結構510的連接部510c之 間。第二摻雜區512a、第一摻雜區504a與基底500可組成NPN結構或PNP結構。第二摻雜區512b、第一摻雜區504b與基底500亦可組成NPN結構或PNP結構。藉由增加第二摻雜區512a、512b與第一摻雜區504a、504b之間的接面(Junction)，可進一步增加抵抗漏電流的能力。此外，圖7之基板5更包括絕緣結構502a覆蓋於第一摻雜區504a、504b的表面上，而未覆蓋於第二摻雜區512a、512b的表面上。
圖8為本揭露第六實施例之基板的剖面示意圖。
請參照圖8，本實施例與圖1E之基板1相似，不同之處在於圖8之具有第二導電型的第一摻雜區604a與604b更延伸至基材600的第一表面S1與第二表面S2。第一摻雜區604a位於第一電極608a與基材600之間以及第二電極608b與基材600之間。第一摻雜區604b位於第一電極610a與基材600之間以及第二電極610b與基材600之間。藉由第一摻雜區604a與604b面積的增加，以減少漏電流的現象。
本揭露上述各實施例的基板上可安裝晶片，而形成封裝結構。在以下的實施例中，是以圖1E之基板來說明，然而，本揭露不以此為限，在其他的實施例中，可以直接將圖1E之基材100a替換成上述各實施例的基材，於此不再贅述。
圖9為依照本揭露之一實施例所繪示的封裝結構。圖10為依照本揭露另一實施例所繪示的封裝結構。
請同時參照圖1E、圖9以及圖10，本揭露之實施例的封 裝結構包括圖1E之基板1與晶片700、800。晶片700、800分別安裝於基板1上。晶片700、800可例如是半導體晶片、發光二極體晶片、記憶晶片或其組合。基板1與晶片700、800兩者之間可以各種方式來電性連接。連接的方是例如是打線(Wire Bonding)、共晶、銲接、覆晶封裝(Flip Chip Bonding)等。以下針對打線與覆晶封裝的方式來敘述本揭露之實施例的封裝結構。
如圖9所述，本揭露之一實施例的封裝結構包括晶片700與基板1，基板1與晶片700藉由打線方式來電性連接。具體來說，晶片700的晶片基板702的第二側表面藉由固晶膠706安裝於基板1上，並與導體結構108的第一電極108a電性連接。晶片700的晶片基板702的第一側表面則透過導線(Wire)708將晶片700的銲墊704與基板1的第一電極110a電性連接。本揭露實施例之基板1將二極體105a、105b埋入基材100中。埋入式的二極體105a、105b不僅具有靜電放電防護的功效，更可縮小其所屬封裝結構的體積，進而降低製造成本。
如圖10所述，本揭露另一實施例的封裝結構包括晶片800與基板1，基板1與晶片800可例如是藉由覆晶封裝方式來電性連接。具體來說，晶片800安裝於基板1上。晶片800包括透明基板808與晶片基板802。透明基板808位於晶片基板802的第一側的表面上。在一實施例中，透明基板808可例如是藍寶石基板(Sapphire)、SiC、InP或GaN等。晶片基板802的第二側的表面上藉由第一凸塊804與第二凸塊806與基板1電性連接。在一 實施例中，第一凸塊804配置於晶片基板802與基板1之間，以電性連接晶片基板802的P型半導體層(例如是P型GaN)與基板1的第一電極108a。第二凸塊806位於晶片基板802與基板1之間，以電性連接晶片基板802的N型半導體層(例如是N型GaN)與基板1的第一電極110a。
綜上所述，本揭露之實施例在基材的穿孔的側壁中埋入二極體，可有效地提升抗靜電放電的效能，增進所屬電子裝置的產品可靠度，其亦可縮小所屬封裝結構的體積。此外，上述埋入式的二極體與發光二極體電性連接，則可提升發光二極體的混光效果。如此一來，本揭露之實施例不僅可降低製造成本，且亦符合現今電子產品輕薄短小的趨勢。
雖然本揭露已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
1a‧‧‧基板
10、20‧‧‧穿孔
100a‧‧‧基材
102‧‧‧絕緣層
102a‧‧‧絕緣結構
104g‧‧‧第一摻雜區
105‧‧‧二極體
108、110‧‧‧導體結構
S1‧‧‧第一表面
S2‧‧‧第二表面

Claims (18)

  1. 一種基板，包括：具有一第一導電型的一基材；兩個導體結構，分別從該基材的一第一表面，經由貫穿該基材的兩個穿孔，延伸到該基材的一第二表面，其中每一導體結構包括：一第一電極，配置於該基材的該第一表面上；一第二電極，配置於該基材的該第二表面上；以及一連接部，配置於該第一電極與該第二電極之間，使得該第一電極與該第二電極電性連接；以及至少一二極體，埋入於該些穿孔其中之一的一側壁的該基材中，且至少該二極體包括：具有一第二導電型的一第一摻雜區，位於該些穿孔其中之一的該側壁的該基材中，其中該第一摻雜區與該連接部之側壁的至少一部分接觸。
  2. 如申請專利範圍第1項所述的基板，更包括一圖案化的絕緣層，配置於該基材與該些第一電極之間以及該基材與該些第二電極之間。
  3. 如申請專利範圍第1項所述的基板，更包括一絕緣結構，配置於該些連接部的兩側壁上，使得該第一摻雜區與該連接部彼此電性隔絕。
  4. 如申請專利範圍第1項所述的基板，更包括具有該第一導 電型的一第二摻雜區，配置於至少該第一摻雜區與所對應的該連接部之間。
  5. 如申請專利範圍第1項所述的基板，其中該第一摻雜區更延伸至該基材的該第一表面與該第二表面，位於與該第一摻雜區連接的該導體結構的該第一電極與該基材之間以及與該第一摻雜區連接的該導體結構的該第二電極與該基材之間。
  6. 如申請專利範圍第1項所述的基板，其中該些連接部之輪廓包括沙漏形、I字形、倒梯形或領結形。
  7. 如申請專利範圍第1項所述的基板，其中該基材包括：一主體部；以及一邊緣部，該邊緣部位於該主體部的邊緣，其中該邊緣部具有一導角，其中該導角由一第三表面與該第二表面的連接處所構成，且該導角為鈍角。
  8. 如申請專利範圍第7項所述的基板，更包括具有該第二導電型的一第三摻雜區，配置於該邊緣部的該第三表面下方的該基材中。
  9. 如申請專利範圍第1項所述的基板，其中該基材具有一空腔，其中至少該二極體埋入於該空腔底部的該基材中。
  10. 一種基板的製造方法，包括：提供具有一第一導電型的一基材；於該基材中形成兩個穿孔，該些穿孔分別貫穿該基材；於該些穿孔其中之一裸露的該基材中埋入至少一二極體，且 至少該二極體包括：具有一第二導電型的一第一摻雜區，位於該些穿孔其中之一的該側壁的該基材中；以及於該基材中形成兩個導體結構，分別從該基材的一第一表面，經由該些穿孔貫穿該基材，延伸到該基材的一第二表面，其中該第一摻雜區與該導體結構之側壁的至少一部分接觸。
  11. 如申請專利範圍第10項所述的基板的製造方法，於該基材中形成該些導體結構的方法包括：於該基材的該第一表面上形成至少兩個第一電極；於該基材的該第二表面上形成至少兩個第二電極；以及於每一穿孔中形成所對應的一連接部，每一連接部與所對應的該第一電極與所對應的該第二電極電性連接。
  12. 如申請專利範圍第11項所述的基板的製造方法，於該基材中形成該些穿孔的步驟包括：於該基材上形成一圖案化的絕緣層，該圖案化的絕緣層具有至少兩組相對應的兩開口；以及以該圖案化的絕緣層為罩幕，對該些開口之間的該基材進行一等向性蝕刻製程，移除部分該基材。
  13. 如申請專利範圍第12項所述的基板的製造方法，於該基材中埋入至少該二極體的方法包括：於該基材中形成該些穿孔之後，以該圖案化的絕緣層為罩幕，對該些穿孔的側壁進行摻雜製程，以於部分該基材中形成具 有該第二導電型的該第一摻雜區。
  14. 如申請專利範圍第10項所述的基板的製造方法，更包括於該些連接部的兩側壁上形成一絕緣結構，電性隔絕該基材與所對應的該連接部。
  15. 如申請專利範圍第10至14項中任一項所述的基板的製造方法，在該基材中埋入至少該二極體之前，更包括於該基材中形成一空腔，使得至少該二極體埋入於該空腔底部的該基材中。
  16. 一種封裝結構包括如申請專利範圍第1至9項中任一項所述之基板，該封裝結構包括：一晶片，配置於該基板上，其中該晶片與該基板電性連接。
  17. 如申請專利範圍第16項所述的封裝結構，其中該晶片藉由導線(Wire)或凸塊與該基板電性連接。
  18. 如申請專利範圍第16項所述的封裝結構，其中該晶片包括半導體晶片、發光二極體晶片、記憶晶片或其組合。
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US20150063745A1 (en) 2015-03-05
US9653382B2 (en) 2017-05-16
TW201507754A (zh) 2015-03-01
US20150063386A1 (en) 2015-03-05
US9171779B2 (en) 2015-10-27
US9613886B2 (en) 2017-04-04
TWI589326B (zh) 2017-07-01
US9252079B2 (en) 2016-02-02
TW201513235A (zh) 2015-04-01
US20150061084A1 (en) 2015-03-05
CN104425394A (zh) 2015-03-18
US20160020578A1 (en) 2016-01-21

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