TWI529806B - 形成鎢接觸點及小臨界尺寸互連線之方法 - Google Patents
形成鎢接觸點及小臨界尺寸互連線之方法 Download PDFInfo
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- TWI529806B TWI529806B TW099111860A TW99111860A TWI529806B TW I529806 B TWI529806 B TW I529806B TW 099111860 A TW099111860 A TW 099111860A TW 99111860 A TW99111860 A TW 99111860A TW I529806 B TWI529806 B TW I529806B
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- Prior art keywords
- tungsten
- substrate
- layer
- cvd
- feature
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Links
- 238000000034 method Methods 0.000 title claims description 169
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims description 165
- 239000010937 tungsten Substances 0.000 title claims description 164
- 229910052721 tungsten Inorganic materials 0.000 title claims description 164
- 238000005229 chemical vapour deposition Methods 0.000 claims description 162
- 230000008569 process Effects 0.000 claims description 124
- 238000000151 deposition Methods 0.000 claims description 120
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- 238000012545 processing Methods 0.000 claims description 37
- 239000003638 chemical reducing agent Substances 0.000 claims description 35
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- 238000006243 chemical reaction Methods 0.000 claims description 17
- 229910052731 fluorine Inorganic materials 0.000 claims description 14
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- 238000009792 diffusion process Methods 0.000 claims description 3
- 238000010926 purge Methods 0.000 claims description 2
- 150000003657 tungsten Chemical class 0.000 claims description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 2
- 239000010410 layer Substances 0.000 description 148
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- 239000007789 gas Substances 0.000 description 27
- 229910052796 boron Inorganic materials 0.000 description 21
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- 235000012431 wafers Nutrition 0.000 description 17
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- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 11
- 238000012546 transfer Methods 0.000 description 11
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical group [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 10
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- 230000007547 defect Effects 0.000 description 9
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- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- DIOQZVSQGTUSAI-UHFFFAOYSA-N decane Chemical compound CCCCCCCCCC DIOQZVSQGTUSAI-UHFFFAOYSA-N 0.000 description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 7
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- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 4
- 229910052786 argon Inorganic materials 0.000 description 4
- 150000002431 hydrogen Chemical class 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
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- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
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- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- RYHBNJHYFVUHQT-UHFFFAOYSA-N 1,4-Dioxane Chemical compound C1COCCO1 RYHBNJHYFVUHQT-UHFFFAOYSA-N 0.000 description 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 1
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- 238000011010 flushing procedure Methods 0.000 description 1
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- 238000010574 gas phase reaction Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- 238000004519 manufacturing process Methods 0.000 description 1
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- 230000007246 mechanism Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000000414 obstructive effect Effects 0.000 description 1
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- 238000013021 overheating Methods 0.000 description 1
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- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 description 1
Classifications
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- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/02—Pretreatment of the material to be coated
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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- C23C16/045—Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- C23C16/08—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
- C23C16/14—Deposition of only one other metal element
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- C—CHEMISTRY; METALLURGY
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- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
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- C23C16/45523—Pulsed gas flow or change of composition over time
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- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
- H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Chemical Vapour Deposition (AREA)
Description
使用化學氣相沈積(CVD)技術之鎢膜沈積係許多半導體製造過程之組成部分。鎢膜可用作呈水平互連線形式之低電阻率電連接件、相鄰金屬層之間的介層孔,及第一金屬層與矽基板上之器件之間的接觸點。在一習知鎢沈積製程中,在一真空室中將晶圓加熱至製程溫度,且接著沈積鎢膜之一極薄部分,其充當晶種層或晶核層。之後,鎢膜之剩餘部分(主體(bulk)層)沈積於該晶核層上。按照慣例,藉由在正生長之鎢層上使用氫氣(H2)還原六氟化鎢(WF6)來形成該鎢主體層。
由於半導體器件按32 nm及32 nm以上之技術節點規定,因此收縮接觸點及介層孔尺寸使得鎢之化學氣相沈積更加具有挑戰性。增加縱橫比可能導致器件特徵內之空隙或大接縫,從而引起微處理器及記憶體晶片之較低良率及降低效能。國際半導體技術藍圖(ITRS)要求32 nm之堆疊電容器DRAM接觸點具有大於20:1之縱橫比。邏輯接觸點雖然不如DRAM接觸點挑釁(aggressive),但當縱橫比上升至10:1以上時,邏輯接觸點仍將受到挑戰。使用習知CVD鎢沈積技術來進行對如同此等之挑釁特徵的無空隙填充存在問題。
本發明之一項態樣係關於對高縱橫比特徵進行無空隙鎢填充之方法。根據各種實施例,該等方法涉及用以使用鎢來填充該等特徵之一降低溫度化學氣相沈積(CVD)製程。在特定實施例中,在用以填充該特徵之該化學氣相沈積期間,該製程溫度維持在小於約350℃。該降低溫度CVD鎢填充提供對高縱橫比特徵的改良之鎢填充,提供對到達下伏層中之氟遷移的改良之障壁,同時達成與標準CVD填充類似的薄膜電阻率。本發明之另一態樣係關於沈積具有低電阻率之薄鎢膜的方法。根據各種實施例,該等方法涉及:在沈積一鎢主體層之前對一經沈積之晶核層執行一降低溫度低電阻率處理,及/或經由一降低溫度CVD製程沈積一主體層,接著為一高溫CVD製程。
序言
在以下描述中,闡述眾多特定細節以便提供對關於形成薄鎢膜之本發明之透徹理解。對於熟習此項技術者而言,對本文中所展示並論述之特定方法及結構的修改、調適或變化將顯而易見,且其屬於本發明之範疇內。
對於維持記憶體及邏輯器件兩者之介層孔/接觸點效能及可靠性而言,將鎢擴展至32 nm以下之技術範圍係關鍵的。當器件按較小之技術節點規定時,在鎢填充方面存在多種挑戰。一個挑戰為:防止電阻歸因於接觸點及介層孔中之較薄膜而增加。隨著特徵變小,鎢(W)接觸點或線之電阻歸因於較薄之W膜中的散射效應而增加。雖然有效鎢沈積製程需要鎢晶核層,但此等層通常具有比主體鎢層之電阻率高的電阻率。隨著特徵變小,低電阻率之鎢膜最小化積體電路設計中的功率損失及過熱。薄障壁及鎢晶核膜(其電阻率較高)佔據該等較小特徵之較大百分比。
圖1展示一介層孔/接觸點結構100中由一晶核膜110及一主體鎢材料120佔據之體積。圖2展示由12 及50 之晶核膜佔據的隨技術節點而變之體積百分比。因為晶核層之電阻率高於主體層之電阻率(ρ晶核>ρ主體),所以應最小化晶核層之厚度以使總電阻保持儘可能低。另一方面,鎢晶核應足夠厚以完全覆蓋下伏基板,從而支援高品質之主體沈積。
當器件按較小之技術節點規定時,在鎢塞填(plugfill)方面之另一挑戰為步階覆蓋率。在32 nm節點下,堆疊電容器DRAM接觸點(例如)需要對特徵進行大於20:1之高縱橫比的鎢填充。邏輯接觸點雖然不如DRAM接觸點挑釁,但當較小接觸點開口將縱橫比要求增加至近10:1時,邏輯接觸點仍具有挑戰。記憶體器件通常使用基於CVD TiCl4之Ti/TiN襯墊/障壁,其相當保形。然而,邏輯器件仍依賴於基於PVD/MOCVD之Ti/TiN膜,其產生與大的突出物相關聯之額外步階覆蓋率挑戰,該大的突出物產生凹進(reentrant)形狀或夾斷(pinch off)。自襯墊/障壁膜突出之PVD突出物放大了填充小特徵之難度。此使得不僅難以使用晶核膜來填充特徵,且最終亦難以使用主體CVD膜來填充特徵。外來之突出物結合高縱橫比結構之尺寸使得使用先前之技術節點中所使用的CVD鎢沈積製程難以或不可能達成無空隙塞填。
根據各種實施例,本發明提供鎢填充製程來克服挑釁(aggressive)之縱橫比及襯墊/障壁步階覆蓋率限制,包括減小晶核膜之厚度及改良填充製程之步階覆蓋率。在特定實施例中,該等方法亦提供抵抗下伏障壁/襯墊層之氟攻擊的上部(superior)障壁膜。
圖3呈現說明根據特定實施例之提供填充之方法中之操作的製程流程圖。該製程開始於提供其中形成有一高縱橫比特徵之基板。(302)。雖然本發明之實施例不限於高縱橫比特徵,但本文中所描述之方法對於達成對高縱橫比特徵之良好無空隙填充係關鍵的,對此,先前技術節點中用以填充特徵之CVD製程不提供充分的填充。根據各種實施例,該基板特徵具有至少10:1、至少15:1、至少20:1、至少25:1或至少30:1之縱橫比。亦根據各種實施例,該特徵大小除了由縱橫比表徵之外或替代縱橫比亦由特徵開口大小表徵。該開口可為10 nm至100 nm寬,或10 nm至50 nm寬。舉例而言,在特定實施例中,該等方法可有利地用於具有窄開口之特徵,而不管縱橫比。
在特定實施例中,凹入特徵形成於基板上之一介電層內,該特徵之底部提供與一下伏金屬層之接觸。亦在特定實施例中,該特徵在其側壁及/或底部上包括一襯墊/障壁層。襯墊層之實例包括Ti/TiN、TiN及WN。除了擴散障壁層之外或替代擴散障壁層,該特徵可包括諸如黏著層、晶核層、其組合或襯於該特徵之側壁及底部之任何其他適用材料的層。
在特定實施例中,該特徵為一凹進特徵;亦即該襯墊層或其他材料形成部分地阻塞特徵開口之突出物。因為許多沈積製程不具有良好之步階覆蓋特性(亦即,較多材料沈積於場區上,且相比於在特徵內部而更靠近開口),所以襯墊層在靠近開口處比(例如)在特徵內部更厚。為達成此描述之目的,將「靠近開口」界定為特徵內(亦即,沿特徵之側壁)之對應於自場區開始量測之特徵深度之約0至10%之間的大致位置或區域。在特定實施例中,靠近開口之區域對應於在開口處之區域。另外,將「在特徵內部」界定為特徵內之對應於自特徵之頂部上的場區開始量測之特徵深度之約20%至60%之間的大致位置或區域。通常,當特定參數(例如,厚度)之值經指定為「靠近開口」或「在特徵內部」時,此等值表示在此等位置/區域內獲取的一量測值或多個量測值之平均值。在特定實施例中,靠近開口之下層(under-layer)的平均厚度比在特徵內部之下層的平均厚度大至少約10%。在更特定實施例中,此差異可為至少約25%、至少約50%、或至少約100%。在一特徵內材料之分佈亦可由其步階覆蓋率表徵。為達成此描述之目的,將「步階覆蓋率」界定為兩個厚度之比率,亦即,在特徵內部之材料的厚度除以靠近開口之材料的厚度。在特定實例中,襯墊或其他下層之步階覆蓋率小於約100%,或更具體地,小於約75%或甚至小於約50%。
返回至圖3,接著在該特徵中沈積一鎢晶核層,其通常用以保形地塗佈該特徵之側壁及底部(304)。一般而言,晶核層為一薄的保形層,其用來促進主體材料在其上之隨後形成。與下伏特征適形對於支援高品質之沈積而言係關鍵的。可使用多種製程來形成該晶核層,包括(但不限於)CVD製程、原子層沈積(ALD)製程及脈衝晶核層(PNL)沈積製程。
在PNL技術中,依序地注入反應物之脈衝,且通常藉由反應物之間的沖洗氣體脈衝來將其沖洗出反應室。第一反應物通常吸附至基板上,其可用來與下一反應物進行反應。以一循環型式重複該製程,直至達成所要厚度為止。PNL類似於文獻中所報告之原子層沈積技術。PNL與ALD之區別之處大體上在於其較高之操作壓力範圍(大於1托)及其每循環之較高生長速率(每循環大於1個單層膜之生長)。在本文中所提供描述之情形中,PNL廣泛體現了依序添加反應物以用於在一半導體基板上進行反應的任何循環過程。因此,該概念體現按慣例稱為ALD之技術。在本文中所提供描述之情形中,CVD體現了將反應物一起引入至反應器以用於氣相反應之過程。PNL及ALD製程不同於CVD製程,且反之亦然。
使用一或多個PNL循環來形成一晶核層論述於以下專利中:美國專利第6,844,258號、第7,005,372號、第7,141,494號、第7,262,125號及第7,589,017號;美國專利公開案第2008/0254623號及第2009/0149022號;及美國專利申請案第12/407,541號,該等專利之全部內容以引用的方式併入本文中。此等PNL晶核層製程涉及將基板曝露於各種還原劑及鎢前驅體序列以生長所要厚度之晶核層。沈積一晶核層之組合PNL-CVD方法描述於美國專利第7,655,567號中,亦將該專利之全部內容併入。
晶核層之厚度足以支援高品質之沈積。在特定實施例中,該必要厚度部分地取決於該晶核層沈積方法。如下文所進一步描述,在特定實施例中,一提供步階覆蓋率近100%之厚度低達約12 (相比於50 之典型晶核膜)之晶核膜的PNL方法可用於特定實施例中。然而,不管用以沈積晶核層之方法是什麼,用以填充該特徵之降低溫度CVD操作可用於比習知較高溫度之CVD所要求的更薄的晶核層。在不受任何特定理論約束之情況下,據信此可因為降低溫度下之較慢化學反應改良了甚至未完全顯影之晶核位點上的生長。根據各種實施例,可形成在約30 至50 (3 nm至5 nm)之間的晶核層,在特定實施例中,可形成在低達10 至15 之間的晶核層。
在特定實施例中,在沈積該晶核層之後為一後沈積處理操作,以改良電阻率。此等處理操作在下文中進一步加以描述,且在美國專利公開案第2009/0149022號及美國專利申請案第12/407,541號中更詳細地加以描述,該等專利皆以引用的方式併入本文中。
一旦形成該晶核層,製程即刻繼續使用低溫CVD鎢膜來填充該特徵(306)。在此操作中,一還原劑及一含鎢前驅體流入一沈積室中以在該特徵中沈積一主體填充層。可使用一惰性運載氣體來遞送該等反應物流中之一或多者,該等反應物流可或可不預先混合。不同於PNL或ALD製程,此操作大體上涉及連續地流動該等反應物直至沈積了所要量為止。在特定實施例中,該CVD操作可以多個階段進行,多個連續且同時之反應物流動的時段被一或多個經分流之反應物流動之時段分隔。
包括(但不限於)WF6、WCl6及W(CO)6之各種含鎢氣體可用作含鎢前驅體。在特定實施例中,含鎢前驅體為一含鹵素之化合物,諸如WF6。在特定實施例中,還原劑為氫氣,然而可使用其他還原劑,包括矽烷(SiH4)、二矽烷(Si2H6)、肼(N2H4)、二硼烷(B2H6)及鍺烷(GeH4)。在許多實施例中,氫氣用作CVD製程中之還原劑。
在一降低溫度下執行對特徵之CVD填充。根據各種實施例,該降低溫度(製程及/或基板溫度)在以下範圍中之一者中:介於約250℃至350℃之間、介於約250℃至340℃之間、介於約250℃至330℃之間、介於約250℃至325℃之間、介於約250℃至320℃之間、介於約250℃至315℃之間、介於約250℃至310℃之間、介於約250℃至305℃之間,或介於約250℃至300℃之間。亦根據各種實施例,該製程及/或基板溫度在:介於約260℃至310℃之間、介於約270℃至310℃之間、介於約280℃至310℃之間,或介於約290℃至310℃之間。在特定實施例中,該製程及/或基板溫度為約300℃。
在填充該特徵之後,該溫度升高以沈積一高溫CVD層(308)。該高溫可在以下範圍中之一者中:介於約350℃至450℃之間、介於約360℃至450℃之間、介於約370℃至450℃之間、介於約380℃至450℃之間、介於約390℃至450℃之間,或介於約400℃至450℃之間。在特定實施例中,該高溫CVD在約395℃下執行。升高該溫度可涉及升高該基板溫度。根據各種實施例,該溫度升高至少約50℃、至少約60℃、至少約70℃、至少約80℃、至少約90℃、至少約100℃,或至少約110℃。接著沈積該高溫CVD層(310)。在特定實施例中,不執行操作308及310;亦即,在完成低溫CVD製程且填充了該特徵之後,基板繼續進行進一步處理(諸如,平坦化)。
在特定實施例中,自操作306轉變至操作308涉及在一多沈積台腔室(multi-station chamber)中將基板自一沈積台移至另一沈積台。另外,操作304、後沈積電阻率處理(若執行)、操作306及操作308中之每一者在同一多沈積台腔室之不同沈積台中執行。
在使用單一沈積台來執行操作306及308之替代性實施例中,自操作306至操作308之轉變涉及切斷鎢前驅體之流動(視情況允許氫氣或其他還原氣體及/或運載氣體行進),同時升高基板溫度。一旦基板溫度穩定,鎢前驅體及其他氣體(若必要)即刻流動至反應室中以用於高溫沈積。在其他實施例中,自操作306之轉變可涉及升高基板溫度,同時允許沈積在轉變時段期間繼續進行。
在沈積高溫鎢CVD膜之實施例中,可將其作為一過覆蓋層(overburden layer)沈積於經填充之特徵上。圖4說明在一填充製程之不同階段處一特徵之橫截面之一項實例的示意性表示,在該填充製程中,在使用降低溫度CVD填充該特徵410之後沈積一高溫CVD層。橫截面401表示在任何鎢沈積之前特徵410之一實例。在此實例中,特徵410形成於一介電層430中,在基板之頂部表面405處具有一開口425,且包括一襯墊層413(諸如,TiN層)。在特定實施例中,(例如)歸因於如圖4中所描繪之下層413之突出物415,靠近開口425處之空腔的大小比在特徵內部之空腔的大小窄。
橫截面411表示在執行降低溫度CVD以使用低溫CVD主體層453來填充特徵之後的該特徵。(在圖4中未描繪鎢晶核層)。在特定實施例中,執行該降低溫度CVD,至少直至特徵隅角417(基板自平坦區轉變至凹入特徵所在的點)覆蓋有低溫CVD鎢為止。此係因為在特定實施例中,襯墊層、介電層或其他下層在該特徵隅角處特定地易受F2攻擊。如下文進一步論述,該降低溫度CVD鎢具有出乎意料之良好障壁特性,且保護下層在隨後之高溫CVD沈積期間免於曝露於F2。
橫截面421表示在執行較高溫度之CVD以沈積過覆蓋層455之後的特徵。該特徵之側壁及隅角由低溫CVD膜453保護以免受到F2攻擊。橫截面431提供一諸如橫截面401中所描述之使用習知(高溫)製程而填充之窄特徵的比較性實例。藉由一高溫製程,由於突出物415及高溫層455之相對不良之步階覆蓋率,該封閉特徵具有一未被填充之空隙429(亦即,接縫)。該接縫由於以下各種原因而有問題:增加特徵中之電阻,及引起化學機械平坦化(CMP)期間之問題。雖然在示意圖中不可見,但襯墊之隅角或其他部分歸因於F2攻擊而具有黏著問題,從而展現剝落或缺陷。下文參看圖6進一步論述此等缺陷。
在特定實施例中,提供具有將使用鎢來填充之高縱橫比特徵及低縱橫比特徵兩者的一基板。舉例而言,一基板可具有一或多個縱橫比為至少約10:1之特徵,以及一或多個縱橫比小於約5:1、或1:1或1:2之特徵。接著可執行一降低溫度CVD操作以填充該一或多個高縱橫比特徵,接著執行一高溫CVD操作以填充該等低縱橫比特徵。圖5描繪以此方式填充之高縱橫比特徵510及低縱橫比特徵520之一實例。特徵510填充有低溫CVD膜553,其對於提供對窄開口高縱橫比特徵之良好無空隙填充係關鍵的。歸因於其寬開口(例如,大約幾百奈米至幾微米),極少量之低溫CVD膜沈積於特徵520中。接著使用一高溫CVD操作來以高溫CVD膜555填充特徵520,且在此狀況下,沈積過覆蓋層。
降低溫度CVD對於獲得對窄的、高縱橫比特徵之高品質鎢填充係關鍵的。在約400℃之溫度下執行當前鎢CVD。獲得對高級節點特徵之極佳塞填係一挑戰,當特徵具有夾斷之開口(如圖4之橫截面401處所說明)時,該挑戰被放大。另一挑戰呈現為:薄化TiN障壁以允許特徵中更多之空間用於鎢沈積。在特定實施例中,該等高級節點特徵具有小於5 nm厚、薄達1 nm之障壁層。在習知CVD製程中氟自WF6遷移至Ti襯墊區中,其引起整合問題,包括對襯墊之氟攻擊及良率損失。
上文所描述之降低溫度CVD對於獲得高品質塞填係關鍵的。在不受特定理論約束之情況下,據信由該降低溫度CVD提供之高品質塞填係歸因於若干因素。首先,較低之CVD溫度藉由減少含鎢前驅體之熱分解而減小鎢沈積速率。據信此藉由減少特徵開口處之鎢沈積而輔助對高縱橫比窄特徵之塞填,藉此允許更多之WF6(或其他含鎢前驅體)分子到達該特徵之較低區並沈積鎢。在習知CVD製程中,在特徵之頂部處的沈積防止前驅體擴散至特徵之較低區中。此引起特徵之內部區中的空隙或接縫(諸如圖4中之橫截面431中所描繪)。較佳之塞填具有多個益處:其在特徵中產生更多之鎢,促成電子輸送且減小接觸點及線電阻,且其防止後CMP問題。舉例而言,其減少CMP漿液陷入接縫及空隙中的可能性。
除了上文之機制之外,亦據信極佳之塞填係歸因於在降低溫度下之能量不足以促成氟遷移經過鎢晶核層及TiN層,及/或即使氟原子或六氟化鎢分子確實遷移,能量亦不足以使得由Ti與F或Ti與WF6之間的反應而形成TiFx。低溫CVD反應最小化氟對Ti之攻擊。
除了上文,亦發現:相比於由其他製程沈積之鎢膜,低溫CVD鎢膜提供出乎意料之良好氟障壁特性。圖6展示對習知PNL W及PNL W+低溫CVD進行之缺陷研究的結果。僅PNL W或PNL W+低溫W膜以以下厚度沈積於Ti/TiN基板上:
僅PNL W:34 、54 及76
PNL W+低溫CVD W:22 PNL+8 CVD(總計30 )、22 PNL+10 CVD(總計32 )、22 PNL+15 CVD(總計37 )
PNL W及低溫CVD皆在300℃下發生。接著該等W膜經受一拷問測試(torture test),在該拷問測試中在395℃下將該等W膜曝露於WF6。若氟擴散通過W膜及TiN,則其與下伏Ti反應而形成揮發性TiFx化合物,且產生典型之「火山」缺陷以及局部剝落、破裂或起泡。此等缺陷在光學顯微鏡下係可見的。如圖6中所展示,低溫CVD W連同薄PNL W比僅PNL W表現地更像一較佳W擴散層。此結果之出乎意料之處在於:對於相同之W膜總厚度,低溫CVD膜提供改良之F障壁特性。原本預期薄PNL+低溫CVD層將具有與在相同溫度下沈積之薄PNL層類似的缺陷計數。
對經圖案化有100 nm之開口/10:1之縱橫比的特徵(包括PVD Ti/MOCVD TiN障壁層)的晶圓執行一氟攻擊研究。在特徵中沈積一鎢晶核層,其使用一薄(12 )層以便產生放大之信號。使用395℃之CVD鎢或是350℃之CVD鎢來填充特徵。接著檢查並比較特徵填充。低溫CVD填充提供較佳之塞填以及減小之氟攻擊。除了展示減小之氟攻擊之外,該等結果指示降低溫度提供對薄晶核層之較佳步階覆蓋。在不受任何特定理論約束之情況下,據信該降低溫度製程之較慢化學反應允許未完全形成之晶核位點上的生長。
使用300℃及395℃來執行對32 nm之凹進特徵的填充。比較經填充之特徵,且檢查該等膜之火山缺陷。低溫CVD產生較佳之填充,其具有較少或不具有接縫或空隙。在經高溫CVD填充之特徵中觀測到空隙。圖7展示395℃之膜(701)及300℃之膜(702)的微觀影像。在395℃之膜中觀測到許多火山缺陷;在300℃之膜中無火山缺陷。除了提供改良之塞填及減小之氟攻擊之外,低溫膜亦具有與高溫膜相當之電阻率。此展示於圖8中。
亦提供沈積超低電阻率之鎢膜的改良方法。根據各種實施例,此等方法涉及沈積一薄PNL晶核層,對該晶核層執行一低電阻率處理,及沈積一高溫CVD層以填充特徵。在特定實施例中,該低電阻率處理包括一低溫CVD製程。
已發現:生長厚度大於20 nm及20 nm以上之低電阻率鎢的低電阻率製程不可生長厚度為20 nm或20 nm以下之低電阻率鎢。當器件之臨界尺寸減小至40 nm或低於40 nm時,結構中之鎢層之厚度為20 nm或20 nm以下。圖9呈現說明針對使用第一低電阻率製程進行處理之膜(905)及針對使用根據特定實施例之薄膜低電阻率製程進行處理之膜(901)的隨厚度而變之膜電阻率的曲線。為進行比較,描繪在未進行低電阻率處理之情況下沈積的膜(907)。
用以沈積由905表示之膜的製程涉及:在降低溫度下於一無氫環境中沈積一PNL晶核層,接著為一高溫低電阻率處理。在一PNL晶核層旁邊沈積未經處理之膜(資料序列(data series)907),其未進行低電阻率處理。沈積約20 至25 之晶核層,剩餘之厚度由低溫CVD沈積。對於大於120 (12 nm)之厚度,高溫處理產生具有較低電阻率之膜,然而對於小於120 之厚度,情況相反。下文展示用於膜之沈積的製程參數:
B=B2H6/W=WF6/S=SiH4
對於經由使用高溫製程進行處理之薄膜,電阻率之增加係出乎意料的。如自圖式可見,甚至對於低於120 之膜,根據發明性製程之一實施例的低電阻率處理亦提供低電阻率。根據各種實施例,該薄膜電阻率處理涉及執行一低溫電阻率處理,該低溫電阻率處理涉及在一降低溫度下將經沈積之晶核層曝露於多個還原劑脈衝。該多個還原劑脈衝可或可不包括介入之含鎢前驅體脈衝。亦根據各種實施例,該薄膜電阻率處理涉及在完成經由高溫CVD進行之填充之前的一經由降低溫度CVD進行之部分填充。在沈積一定量之主體CVD材料時,該降低溫度CVD操作可被視為一低電阻率處理。在特定實施例中,在由圖9中之資料序列901表示之膜中,該製程涉及低溫曝露於多個還原劑脈衝及經由低溫CVD進行部分填充兩者。
雖然本文中所描述之此等製程適用於填充具有40 nm以下之臨限尺寸的特徵(特定地適用於具有32 nm或小於32 nm之臨限尺寸的膜),但其亦可用於較厚之膜。如下文所進一步論述,對於較厚之薄膜,亦觀測到改良之電阻率。
圖10至圖12呈現說明根據各種實施例之使用低電阻率鎢來填充特徵之方法中的操作的製程流程圖。首先,在圖10中,將具有一高縱橫比之凹入特徵的基板提供至一沈積室(1002)。如上文所提及,該特徵可具有一窄開口(例如,寬度為40 nm或小於40 nm)。亦在特定實施例中,該方法可用以填充具有較低縱橫比及/或較寬開口之特徵。接著在該特徵中沈積一鎢晶核層(1004)。
雖然可藉由任何已知方法沈積該晶核層,但在特定實施例中,藉由在低溫下沈積該晶核層接著執行一多脈衝低電阻率處理而獲得改良之電阻率。沈積晶核層之此等方法描述於:美國專利第7,589,017號中,該專利以引用的方式併入本文中;及美國專利公開案2008/0254623中,該案亦以引用的方式併入本文中。
在特定實施例中,如圖13中所描述,沈積該晶核層。在提供一無晶核層之基板(如圖4中之401處)之後,將如所提供之基板曝露於一含硼還原劑,以在該基板表面上形成一含硼層(1302)。該含硼層常常為元素硼之層,然而在一些實施例中,其可含有其他化學物質,或來自含硼物質自身或來自反應室中之殘餘氣體的雜質。可使用任何合適之含硼物質,包括硼烷(BH3)、二硼烷(B2H6)、三硼烷等。其他含硼物質之實例包括硼鹵化物(例如,BF3、BCl3)以及氫。
基板溫度係低的(在約350℃以下),其(例如)介於約250℃與350℃之間或250℃與325℃之間。在特定實施例中,該溫度為約300℃。在特定實施例中,自一經稀釋之來源(例如,5%之二硼烷及95%之氮)提供二硼烷。可使用其他或額外運載氣體(諸如,氮及/或氬)來將二硼烷遞送至反應室。重要的是,不使用氫。
一旦將含硼層沈積至一足夠之厚度,即刻停止含硼物質至反應室之流動,且使用一運載氣體(諸如,氬、氫、氮或氦)來沖洗反應室。在特定實施例中,在運載氣體處僅使用氬。該氣體沖洗清除了靠近基板表面之區的可能與用於下一反應步驟之新鮮氣體反應物進行反應的殘餘氣體反應物。
繼續至圖13中之下一操作,使該基板與一含鎢前驅體接觸,以形成鎢晶核層之一部分(1304)。可使用任何合適之含鎢前驅體。在特定實施例中,含鎢前驅體為WF6、WCl6及W(CO)6中之一者。通常在一稀釋氣體(諸如,氬、氮或其組合)中提供該含鎢前驅體。如同含硼前驅體脈衝,在一無氫環境中遞送該含鎢前驅體。基板溫度係低的(在約350℃以下),其(例如)介於約250℃與350℃之間或250℃與325℃之間。在特定實施例中,該溫度為約300℃。在許多狀況下,該基板溫度與在曝露於含硼物質期間的溫度相同。含鎢前驅體劑量及基板曝露時間將視若干因素而變化。一般而言,曝露該基板直至所吸附之硼物質藉由與含鎢前驅體之反應而被充分地消耗為止,從而產生鎢晶核層之一部分。之後,停止含鎢前驅體至反應室之流動,且沖洗反應室。在一個含硼還原劑/含鎢前驅體PNL循環中沈積之鎢晶核層之所得部分可為約5 。
重複該低溫含硼還原劑脈衝及鎢前驅體脈衝操作,以將鎢晶核層建置至所要厚度(1306)。在特定實施例中,需要約2個至7個之間的PNL循環來沈積極薄之晶核層,然而在特定實施例中,單一循環可足夠。視基板而定,開始之一個或兩個循環歸因於晶核延遲而可能不會產生厚度增益。如先前所描述,鎢晶核層應足夠薄以便不會過度地增加總鎢膜,但應足夠厚以便支援高品質之主體鎢沈積。上文所描述之製程能夠在高縱橫比及/或窄寬度特徵中沈積一可支援高品質主體沈積之低達約10 的鎢晶核層。所沈積之晶核層之厚度通常介於約10 與50 之間,或(例如)介於10 與30 之間。
溫度為影響所沈積之鎢之量的製程條件中的一個條件。其他條件包括壓力、流動速率及曝露時間。將溫度維持在約350℃或約350℃以下使得在一個循環期間沈積較少之材料。此又提供較低之電阻率。在一些實施例中,溫度可為約300℃或200℃。
返回參看圖10,在沈積該鎢晶核層之後,經由低溫多脈衝處理來處理所沈積之晶核層以降低電阻率(1006)。圖14a及圖14b為展示可根據低電阻率處理之各種實施例而使用之脈衝序列之實例的圖表。圖14a展示諸如美國專利公開案第2009/0149022號中所描述之脈衝序列之實例,該案以引用的方式併入本文中。本文中所描述之處理製程涉及將所沈積之晶核層曝露於多個還原劑脈衝(無介入之另一反應化合物之脈衝)。在圖14a中,二硼烷經描繪為還原劑,然而可使用其他還原劑。該處理降低電阻率,同時提供良好之黏著及電阻不均一性。應注意,使用多個還原劑脈衝經展示比使用單一脈衝提供顯著改良之電阻率及均一性,即使使用相同之總曝露時間亦如此。然而,過多之脈衝可能導致最終之鎢膜與下伏層的不良黏著。使用最佳數目個脈衝(例如,2至8個)來獲得低電阻率、低不均一性及可接受之黏著。不同於圖13中所描述之晶核層沈積,可在氫背景下執行該處理操作。因此,在特定實施例中,自成核至處理操作之轉變可能涉及開啟氫之流動。亦在特定實施例中,在多沈積台沈積室之第一沈積台中沈積一晶核層,在第二沈積台中執行低電阻率處理。自晶核沈積至低電阻率處理之轉變涉及將基板轉移至該第二沈積台。
圖14b展示一脈衝序列之另一實例,其中以該脈衝序列來將晶核層曝露於交替之還原劑脈衝與含鎢前驅體脈衝的多個循環。二硼烷(B2H6)及六氟化鎢(WF6)分別經展示為還原劑及含鎢前驅體,然而特定實施例可使用其他化合物。亦可使用還原劑與含鎢前驅體之交替脈衝來沈積鎢晶核層,但在處理操作中,通常實質上不沈積鎢。含鎢前驅體之流動速率及/或脈衝時間限於僅清除表面上及沈積室中之由低電阻率處理產生的過量硼,從而減少硼雜質。在特定實施例中,此又引起較少之微剝落及較佳之膜黏著。因此,在該處理期間的含鎢前驅體脈衝曝露時間及/或流動速率(相對於還原劑脈衝)可小於用以沈積晶核層之曝露時間及/或流動速率。
在特定實施例中,亦可執行圖14a及圖14b中所展示之脈衝序列的某種組合。在本文中所描述之實施例中,在約350℃以下之降低溫度下執行該多脈衝處理操作(1006),該降低溫度(例如)介於約250℃與350℃之間或250℃與325℃之間。在特定實施例中,該溫度為約300℃。如上文圖9中所展示及下文所進一步論述,對於薄膜,在低溫下執行低電阻率處理比在較高溫度下執行該處理出乎意料地提供更佳之電阻率。在不受任何特定理論約束之情況下,據信此可歸因於基板所看到之硼的量。下文參看圖16A對此進行進一步論述。根據各種實施例,在該多脈衝處理期間,二硼烷(或其他含硼還原劑)曝露之總量可介於約1E-5莫耳至1E-2莫耳之間,或更特定地,為約1E-4莫耳至1E-3莫耳。接著沈積一CVD主體層以填充該特徵(1008)。此可涉及降低溫度填充、高溫填充,或(在一些實施例中)兩者之組合。
圖11展示根據特定實施例之使用低電阻率鎢來填充特徵之方法中的製程流程圖,其中在晶核層經沈積之後使用降低溫度CVD來部分地填充該特徵。接著執行高溫CVD來完成該特徵填充。如關於圖10所描述,提供具有高縱橫比及/或窄開口之一基板(1102)。接著在該特徵中沈積一晶核層(1104)。如上文所描述,在特定實施例中,如圖13中所描述地沈積該晶核層,其在一低溫無氫環境中使用交替之二硼烷脈衝及鎢前驅體脈衝。接著視情況執行一多脈衝低電阻率處理(1106)。此處理可涉及多個還原劑脈衝而不施加介入之鎢前驅體脈衝(如圖14a中所展示),或可涉及多個還原劑/鎢前驅體脈衝(如圖14b中所展示),或此等脈衝之某種組合。根據各種實施例,該多脈衝處理涉及將基板加熱至介於約350℃至450℃之間的溫度(例如,約395℃),且使該溫度穩定,且將晶核層曝露於該多個脈衝(同時維持該基板溫度)。在其他實施例中,該多脈衝處理在一較低溫度下執行(如上文關於圖10所描述)。
接著,使用一降低溫度CVD主體層來部分地填充該特徵(1108)。包括(但不限於)WF6、WCl6及W(CO)6之各種含鎢氣體可用作含鎢前驅體。在特定實施例中,含鎢前驅體為一含鹵素之化合物,諸如WF6。在特定實施例中,還原劑為氫氣,然而可使用其他還原劑,包括矽烷、二矽烷、肼、二硼烷及鍺烷。在許多實施例中,氫氣用作CVD製程中之還原劑。
根據各種實施例,該降低溫度(製程及/或基板溫度)在以下範圍中之一者中:介於約250℃至350℃之間、介於約250℃至340℃之間、介於約250℃至330℃之間、介於約250℃至325℃之間、介於約250℃至320℃之間、介於約250℃至315℃之間、介於約250℃至310℃之間、介於約250℃至305℃之間,或介於約250℃至300℃之間。亦根據各種實施例,該製程溫度為:介於約260℃至310℃之間、介於約270℃至310℃之間、介於約280℃至310℃之間,或介於約290℃至310℃之間。在特定實施例中,該製程及/或基板溫度為約300℃。
經由一高溫CVD沈積來完成填充(1110)。該高溫可在以下範圍中之一者中:介於約350℃至450℃之間、介於約360℃至450℃之間、介於約370℃至450℃之間、介於約380℃至450℃之間、介於約390℃至450℃之間,或介於約400℃至450℃之間。在特定實施例中,該高溫CVD在約395℃下執行。升高該溫度可涉及升高該基板溫度。根據各種實施例,該溫度升高至少約25℃、30℃、50℃、至少約60℃、至少約70℃、至少約80℃、至少約90℃、至少約100℃、至少約110℃,或至少約125℃。在一項製程實例中,在約250℃下執行一低溫CVD操作,且在約350℃下執行一高溫CVD操作。在特定實施例中,該溫度升高不超過約150℃或甚至125℃以防止熱衝擊及後續的晶圓破裂。
在特定實施例中,自操作1108轉變至操作1110涉及在一多沈積台腔室中將基板自一沈積台移至另一沈積台。在使用單一沈積台來執行操作之替代性實施例中,自操作1108至操作1110之轉變可涉及切斷鎢前驅體之流動(視情況允許氫氣或其他還原氣體及/或運載氣體行進),同時升高基板溫度。一旦基板溫度穩定,鎢前驅體及其他氣體(若必要)即刻流動至反應室中以用於高溫沈積。在其他實施例中,自操作1210之轉變可涉及升高基板溫度,同時允許沈積在轉變時段期間繼續進行。
根據各種實施例,可使用降低溫度CVD來沈積主體CVD填充之總厚度的約0至70%。圖15說明在部分降低溫度CVD填充及經由高溫CVD之完成填充之後一特徵之橫截面之一項實例的示意性表示。橫截面1501展示保形之部分填充降低溫度CVD層1553及高溫填充1555。T指示所沈積之CVD層之總厚度(T為特徵填充之寬度減去鎢晶核層之厚度)。2T1為經由降低溫度CVD而沈積之總厚度。在特定實施例中,可使用降低溫度CVD來沈積主體CVD填充之總厚度的約30%至80%或30%至60%。該降低溫度層亦可依據所沈積之厚度來表徵,其中T1介於約1 nm至10 nm之間或約2 nm至8 nm之間。
如下文進一步論述,在使用高溫CVD完成間隙填充之前,使用降低溫度CVD部分地填充該間隙改良電阻率。當該降低溫度CVD操作在特徵中大體上沈積一定量之保形鎢時,其亦可被認為一低電阻率處理操作。在特定實施例中,該降低溫度操作之曝露時間及/或劑量可足夠短或小,以使得實質上不沈積鎢。
圖12呈現在經由高溫CVD完成填充之前執行一低溫多脈衝處理以及一經由降低溫度CVD之部分填充兩者的製程流程圖。如同參看圖10及圖11,提供具有高縱橫比特徵之一基板(1202),且在該特徵中沈積一晶核層(1204)。在圖13中描述根據特定實施例沈積一晶核層。接著執行一低溫多脈衝處理(1206)(如上文參看圖10所描述)。此時,在特定實施例中,晶核層形成及隨後之多脈衝處理操作兩者皆涉及將含硼化合物專門地用作還原劑;亦即,在CVD沈積之前進行的任何操作中不使用矽烷或其他不含硼之還原劑。接著執行經由降低溫度CVD之部分填充(1208),之後使用高溫CVD來完成填充(1210)(如上文參看圖11所描述)。
在特定實施例中,本文中所描述之製程涉及將所沈積之鎢晶核層曝露於多個依序之二硼烷或其他含硼還原劑脈衝。參見(例如)上文參看圖10進行之論述。圖16A繪製在對晶核層之一低溫多脈衝處理製程期間毯覆式鎢膜之隨總的二硼烷曝露量(以莫耳為單位)而變之電阻率。如所展示地給予晶核層二硼烷劑量,後續接著CVD以沈積50 nm或10 nm之毯覆式膜。50 nm之鎢膜的電阻率隨著增加之劑量時間(dose time)而減小。出乎意料地,對於薄的10 nm膜,電阻率隨著增加之劑量時間而增加。在特定實施例中,對於約20 nm或小於20 nm之薄膜,不執行該多脈衝處理,或將二硼烷曝露量維持在不超過約1E-5莫耳至1E-3莫耳之總曝露量。
如上文所指示,使用降低溫度CVD對一特徵進行部分填充來改良電阻率。圖16B繪製使用部分降低溫度(300℃)CVD及僅高溫(395℃)CVD進行沈積之50 nm之毯覆式膜的隨多脈衝低電阻率鎢(LRW)二硼烷脈衝而變的電阻率。使用圖13中所展示之製程來沈積晶核層,接著為在395℃下之如圖14a中所表示的多脈衝處理。該部分降低溫度CVD膜為6 nm,其中該膜之剩餘部分厚度由高溫CVD沈積。該等膜之電阻率皆隨著多脈衝處理之循環次數的增加而減小。然而,在該處理之後沈積之具有薄降低溫度CVD膜的該等膜具有比具有僅高溫CVD膜之彼等膜的電阻率低的電阻率。如所展示,對於厚膜(例如,>40 nm),該降低溫度CVD部分填充改良電阻率。在特定實施例中,該降低溫度CVD藉由較低數目之二硼烷脈衝而達成低電阻率。
圖17展示針對如上文參看圖10至圖12而描述之製程的對照膜厚度繪製的膜電阻率。對於所有膜,在300℃下沈積約2 nm之晶核層,其中晶核層序列為5 x(B2H6/WF6)(無H2環境)。以下展示用以沈積該等毯覆式膜之製程:
在8 nm與15 nm之間,製程C(低溫多脈衝處理及部分降低溫度CVD)產生最低之電阻率。出乎意料地,對於針對約7.5 nm及7.5 nm以上之膜的等同之成核及處理製程,部分降低溫度CVD(製程C)比僅降低溫度CVD(製程D)及僅高溫CVD(E)產生更低之電阻率。
製程A與製程E相比,對於小於約9 nm厚之膜,低溫低電阻率處理產生更低之電阻率。然而,對於僅降低溫度CVD(如上文關於圖9所論述),對於厚度在約120 nm以下之幾乎所有膜,高溫低電阻率處理(製程B)比低溫低電阻率製程(製程D)產生更高之電阻率。
在特定實施例中,降低溫度CVD在一鎢前驅體浸泡操作之後進行,以降低電阻率。圖18呈現說明此製程中之操作的製程流程圖。首先,提供具有高縱橫比之特徵的一基板(1802)。如同本文中所描述之所有製程,此製程亦可用於其他特徵幾何形狀。接著,藉由任何適當方法在該特徵中沈積一鎢晶核層(1804),接著為多脈衝處理(1806)(如上文參看圖14A及圖14B所描述)。此時,在一鎢前驅體浸泡操作中,將基板曝露於該鎢前驅體(不存在還原劑)(1808)。浸泡時間可介於約0.5秒至10秒之間,例如約1秒至5秒。該浸泡操作期間之溫度可與隨後之降低溫度CVD的溫度相同(例如,300℃)。在鎢前驅體浸泡之後,接著使用降低溫度CVD鎢膜來填充該特徵(1810)。在替代性實施例中,該鎢前驅體浸泡可在部分填充降低溫度CVD之前執行。
圖19為針對在存在及不存在WF6浸泡之情況下由降低溫度CVD沈積之膜的隨膜厚度而變之薄膜電阻率的曲線。對於所有膜,使用圖13中所展示之製程來沈積一晶核層,接著為多脈衝二硼烷低電阻率處理。對於介於約8 nm至12 nm之間的膜,浸泡比無浸泡之製程達成更低之電阻率。在特定實施例中,使用圖18中所描述之製程來達成低電阻率以及上文參看圖3所描述之高品質塞填。
裝置
可在可購自各種供應商之各種類型之沈積裝置中執行本發明之方法。合適之裝置的實例包括Novellus Concept-1 AltusTM、Concept 2 AltusTM、Concept-2 ALTUS-STM、Concept 3 AltusTM沈積系統,及Altus MaxTM,或各種其他市售CVD工具中之任一者。在一些狀況下,可依序地在多個沈積台上執行該製程。參見(例如)美國專利第6,143,082號,其以引用的方式併入本文中用於所有目的。在一些實施例中,在第一沈積台處(例如)藉由一脈衝成核製程沈積一晶核層,該第一沈積台為定位於單一沈積室內之兩個、五個或甚至更多之沈積台中的一者。因此,在該第一沈積台處,使用一獨立氣體供應系統來交替地將還原氣體及含鎢氣體引入至半導體基板之表面,該獨立氣體供應系統在該基板表面處形成一局部氛圍(localized atmosphere)。
接著可使用第二沈積台來完成晶核層沈積或執行一多脈衝低電阻率處理。在特定實施例中,可執行一單脈衝低電阻率處理。
接著使用一或多個沈積台來執行如上文所描述之CVD。可使用兩個或兩個以上之沈積台以並行處理之方式執行CVD。或者,可對一晶圓進行編索引以使該等CVD操作在兩個或兩個以上之沈積台上依序地執行。舉例而言,在涉及低溫及高溫CVD操作兩者之製程中,對於每一操作,在CVD沈積台之間對一晶圓或其他基板進行編索引。
圖20為根據本發明之實施例之適合於進行鎢薄膜沈積製程之處理系統的方塊圖。系統2000包括一轉移模組2003。該轉移模組2003提供一乾淨經加壓之環境,以最小化正被處理之基板在於各種反應器模組之間移動時受到污染的風險。多沈積台反應器2009安裝於該轉移模組2003上,多沈積台反應器2009能夠執行根據本發明之實施例的PNL沈積、多脈衝處理(若需要)及CVD。腔室2009可包括多個沈積台2011、2013、2015及2017,該等沈積台可依序地執行此等操作。舉例而言,腔室2009可經組態以使得沈積台2011執行PNL沈積,沈積台2013執行多脈衝處理,且沈積台2015及2017執行CVD。每一沈積台包括一加熱晶圓基座(pedestal)及一噴淋頭、分散板或其他氣體入口。在圖21中描繪沈積台2100之一實例,其包括晶圓支撐件2102及噴淋頭2103。可在基座部分2101中提供一加熱器。
一或多個單沈積台模組或多沈積台模組2007亦可安裝於轉移模組2003上,沈積台模組2007能夠執行電漿預清洗或化學(非電漿)預清洗。該沈積台模組亦可用於各種其他處理,例如後襯墊氮化鎢處理。系統2000亦包括一或多個(在此狀況下,兩個)晶圓源模組2001,在進行處理之前及之後,將晶圓儲存於該一或多個晶圓源模組2001中。大氣轉移腔室2019中之大氣機器人(圖中未繪示)首先將晶圓自源模組2001移除至裝載室(loadlock)2021。轉移模組2003中之一晶圓轉移器件(通常為機器人臂單元)將晶圓自裝載室2021移至安裝於轉移模組2003上之模組且使其位於該等模組當中。
在特定實施例中,使用一系統控制器2029來控制沈積期間之製程條件。該控制器通常將包括一或多個記憶體器件及一或多個處理器。該處理器可包括一CPU或電腦、類比及/或數位輸入/輸出連接件、步進馬達控制器板等。
該控制器可控制沈積裝置之所有活動。該系統控制器執行系統控制軟體,該系統控制軟體包括用於控制定時、氣體混合、腔室壓力、腔室溫度、晶圓溫度、RF功率位準、晶圓夾盤或基座位置及特定製程之其他參數的指令集合。在一些實施例中可使用儲存於與該控制器相關聯之記憶體器件上的其他電腦程式。
通常將存在一與該控制器相關聯之使用者介面。該使用者介面可包括一顯示螢幕、裝置及/或製程條件之圖形軟體顯示器,及諸如指標器件、鍵盤、觸控式螢幕、麥克風等之使用者輸入器件。
可以如下之任何習知電腦可讀程式設計語言撰寫用於控制一製程序列中之沈積及其他製程的電腦程式碼:例如,組合語言、C、C++、Pascal、Fortran或其他。由該處理器執行編譯目標碼或指令碼以執行程式中所識別之任務。
該等控制器參數係關於製程條件,諸如製程氣體成份及流動速率、溫度、壓力、電漿條件(諸如,RF功率位準及低頻RF頻率)、冷卻氣體壓力及腔室壁溫度。將此等參數以一配方形式提供給使用者,且可利用使用者介面來鍵入此等參數。
可藉由系統控制器之類比及/或數位輸入連接件提供用於監視該製程之信號。將用於控制該製程之信號輸出於沈積裝置之類比及數位輸出連接件上。
可以許多不同方式來設計或組態該系統軟體。舉例而言,可撰寫各種腔室組件副常式或控制物件以控制進行發明性沈積製程所必需之腔室組件的操作。為此目的之程式或程式區段之實例包括基板定位程式碼、製程氣體控制程式碼、壓力控制程式碼、加熱器控制程式碼及電漿控制程式碼。
一基板定位程式可包括用於控制用以將基板裝載至一基座或夾盤上且控制基板與腔室之其他部分(諸如,氣體入口及/或氣體靶)之間的間隔之腔室組件的程式碼。一製程氣體控制程式可包括用於控制氣體成份及流動速率且視情況用於在沈積之前使氣體流動至腔室中以便穩定腔室中之壓力的程式碼。一壓力控制程式可包括用於藉由調節(例如)腔室之排氣系統中之節流閥來控制腔室中之壓力的程式碼。一加熱器控制程式可包括用於控制至一加熱單元之用以加熱基板之電流的程式碼。或者,該加熱器控制程式可控制一熱轉移氣體(諸如,氦)至晶圓夾盤之遞送。
在沈積期間可被監視之腔室感測器之實例包括質量流量控制器、諸如流體壓力計之壓力感測器,及位於基座或夾盤中之熱電偶。經適當程式化之回饋與控制演算法可用於來自此等感測器之資料以維持所要製程條件。前述內容描述了以單腔室或多腔室半導體處理工具之形式實施的本發明之實施例。
應用
本發明可用以沈積用於許多不同應用之薄的低電阻率鎢層。一個應用為介層孔、接觸點及普遍出現於電子器件中之其他鎢結構。另一應用為諸如記憶體晶片及微處理器之積體電路中之互連線。互連線為固定於單一金屬化層上之電流線,且其通常為長薄扁平結構。互連線應用之一主要實例為記憶體晶片中之位元線。一般而言,本發明應用於需要薄的低電阻率之鎢層的任何環境中。
其他實施例
雖然已依據若干實施例描述了本發明,但存在在本發明之範疇內的更改、修改、置換及取代均等物。舉例而言,雖然上文之描述主要在特徵填充之背景下,但上文所描述之方法亦可用以在毯覆式表面上沈積低電阻率鎢膜。可藉由鎢層之毯覆式沈積(藉由如上文所描述之製程)、接著為界定載流鎢線之位置的圖案化操作,及將鎢自鎢線外部之區移除來形成此等鎢膜。
亦應注意,存在實施本發明之方法及裝置的許多替代性方法。因此,意欲將以下隨附之申請專利範圍解釋為包括屬於本發明之真實精神及範疇內的所有此等更改、修改、置換及取代均等物。
100...介層孔/接觸點結構
110...晶核膜
120...主體鎢材料
401...橫截面
405...頂部表面
410...特徵
411...橫截面
413...襯墊層
415...突出物
417...特徵隅角
421...橫截面
425...開口
429...空隙
430...介電層
431...橫截面
453...低溫CVD主體層/低溫CVD膜
455...高溫層/過覆蓋層
510...高縱橫比特徵
520...低縱橫比特徵
553...低溫CVD膜
555...高溫CVD膜
701...395℃之膜
702...300℃之膜
901...使用根據特定實施例之薄膜低電阻率製程進行處理之膜
905...使用第一低電阻率製程進行處理之膜
907...在未進行低電阻率處理之情況下沈積的膜
1501...橫截面
1553...保形之部分填充降低溫度CVD層
1555...高溫填充
2000...系統
2001...晶圓源模組
2003...轉移模組
2007...單沈積台或多沈積台模組
2009...多沈積台反應器
2011...沈積台
2013...沈積台
2015...沈積台
2017...沈積台
2019...大氣轉移腔室
2021...裝載室
2029...系統控制器
2100...沈積台
2101...基座部分
2102...晶圓支撐件
2103...噴淋頭
圖1為根據特定實施例之填充有鎢晶核層及鎢主體層之特徵的示意性說明。
圖2為展示針對12 及50 之晶核層的隨技術節點(特徵大小)而變之由晶核層佔據之特徵之體積百分比的曲線。
圖3為說明根據各種實施例之一使用鎢來填充一特徵之方法中的操作的製程流程圖。
圖4描繪根據特定實施例之在一製程之各個階段處的特徵橫截面的示意性說明。
圖5描繪根據特定實施例之在一特徵填充製程之後的基板橫截面的示意性說明。
圖6為描繪針對1)藉由脈衝晶核層(PNL)製程及低溫化學氣相沈積(CVD)製程而沈積之膜及2)僅藉由PNL製程而沈積之膜的隨膜厚度而變之缺陷的曲線。
圖7描繪在對32 nm之特徵進行高溫CVD填充及低溫CVD填充之後的膜的影像。
圖8描繪針對藉由高溫CVD及低溫CVD而沈積之膜的隨膜厚度而變之電阻率。
圖9為描繪針對藉由各種製程而沈積之鎢膜的隨膜厚度而變之電阻率的曲線。
圖10至圖12為說明根據各種實施例之使用鎢來填充一特徵之方法中的操作的製程流程圖。
圖13為說明沈積一可由特定實施例使用之鎢晶核層之方法中的操作的製程流程圖。
圖14A及圖14B說明根據各種實施例之低電阻率處理中的氣體脈衝序列。
圖15為根據特定實施例之在一特徵填充製程之後的特徵橫截面的示意性說明。
圖16A為說明在低電阻率處理過程期間50 nm及10 nm之膜的隨著還原劑曝露量而變之電阻率的曲線。
圖16B為說明針對僅經由高溫CVD填充之特徵及經由低溫CVD及高溫CVD填充之特徵的低電阻率處理中50 nm之膜之隨著還原劑曝露量而變之電阻率的曲線。
圖17為說明針對各種填充製程之隨膜厚度而變之電阻率的曲線。
圖18為說明根據各種實施例之使用鎢來填充一特徵之方法中的操作的製程流程圖。
圖19為說明針對各種填充製程之隨膜厚度而變之電阻率的曲線。
圖20為根據本發明之實施例之適合於進行鎢沈積製程之處理系統的示意性說明。
圖21為根據本發明之實施例之鎢沈積的基本說明。
(無元件符號說明)
Claims (15)
- 一種填充一基板上之一凹入特徵的方法,該方法包含:提供具有一場區及自該場區凹入之一第一凹入特徵的一基板,該第一凹入特徵包含多個側壁、一底部、一開口及多個隅角(corner);在該第一凹入特徵之該等側壁及底部上沈積一鎢晶核(nucleation)層,其中該鎢晶核層具有介於10埃(Angstroms)與50埃之間之一厚度並沈積於一襯墊層(liner layer)上;及經由一化學氣相沈積(CVD)製程來使用一低溫CVD鎢主體(bulk)層填充該第一凹入特徵;其中該基板溫度在該CVD製程期間維持在約250℃與350℃之間,其中該低溫CVD鎢主體層提供一障壁以防止氟擴散至該襯墊層。
- 如請求項1之方法,其進一步包含:在填充該第一凹入特徵之後,將該基板溫度升高至少約50℃;及在升高該基板溫度之後,在經填充之該第一凹入特徵上沈積一高溫主體鎢CVD層。
- 如請求項1之方法,其中該第一凹入特徵具有一至少10:1之縱橫比。
- 如請求項1之方法,其中該第一凹入特徵之開口的寬度不超過約50nm。
- 如請求項1之方法,其中填充該第一凹入特徵包含使用該低溫CVD主體層覆蓋該等特徵之隅角。
- 如請求項1之方法,其中該基板進一步包含自該場區凹入之一第二凹入特徵,該第二凹入特徵具有低於該第一 凹入特徵之縱橫比的一縱橫比。
- 如請求項6之方法,其進一步包含:在填充該第一凹入特徵之後,將該基板溫度升高至少約50℃;及在升高該基板溫度之後,沈積一高溫主體鎢CVD層以填充該第二凹入特徵。
- 如請求項7之方法,其中使用一低溫CVD鎢主體層填充該第一凹入特徵包含將一鹵化含鎢前驅體(precursor)及一還原劑引入至一罩住該基板之反應台中。
- 如請求項1之方法,其中該第一凹入特徵包括具有一不超過5nm之厚度的一襯墊層。
- 如請求項1之方法,其進一步包含:在於該凹入特徵之該等側壁及底部上沈積一鎢晶核層之後,且在使用一低溫CVD鎢主體層填充該特徵之前,使用一含鎢前驅體來浸泡該基板。
- 如請求項1之方法,其中該低溫CVD鎢主體層覆蓋該等特徵之隅角,且進一步包含:在填充該第一凹入特徵之後,將該基板溫度升高至少約50℃,且在升高該基板溫度之後,在該低溫CVD鎢主體層上且包括在由該低溫CVD鎢主體層覆蓋的該等特徵之隅角上沈積一高溫主體鎢CVD層。
- 如請求項1至11中任一項之方法,其中基板溫度在該CVD製程期間維持在約250℃與325℃之間。
- 如請求項1至11中任一項之方法,其中基板溫度在該CVD製程期間維持在約250℃與315℃之間。
- 一種用於在一基板上沈積鎢膜之裝置,其包含:a)一多沈積台基板沈積室,其包含:一鎢晶核層沈積台,該沈積台包含一基板支撐件及經組態以將該基板曝露於氣體脈衝之一或多個氣體入口;一主體層沈積台,該主體層沈積台包含一基板支撐件及經組態以將該基板曝露於氣體之一或多個氣體入口;及b)一控制器,其用於控制該多沈積台沈積室中之操作,該控制器包含用於進行以下操作之機器可讀指令:將複數個還原劑(reducing agent)脈衝/沖洗(purge)氣體脈衝/含鎢前驅體脈衝循環施加於該鎢晶核層沈積台中,以在一襯墊層上沈積具有介於10埃與50埃之間之一厚度之一鎢晶核層;將該基板自該鎢晶核層沈積台轉移至該主體層沈積台;及將還原劑及含鎢前驅體同時流動(flow)至該主體層沈積台中,同時使一基板溫度維持在約250℃與350℃之間以沈積一低溫CVD鎢主體層,其中該低溫CVD鎢主體層提供一障壁以防止氟擴散至該襯墊層。
- 如請求項14之裝置,其進一步包含一低電阻率處理台,該低電阻率處理台包含一基板支撐件及經組態以將該基板曝露於氣體脈衝之一或多個氣體入口;其中控制器進 一步包含用於將複數個還原劑脈衝施加至該低電阻率處理台之機器可讀指令,且其中該等用於將該基板自該鎢晶核層沈積台轉移至該主體層沈積台之指令包含用於將該基板自該鎢晶核層沈積台轉移至該低電阻率處理台之指令,及用於將該基板自該低電阻率處理台轉移至該主體層沈積台之指令。
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KR101642917B1 (ko) | 2016-07-26 |
TWI536458B (zh) | 2016-06-01 |
JP2010251760A (ja) | 2010-11-04 |
US20100267235A1 (en) | 2010-10-21 |
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TW201120959A (en) | 2011-06-16 |
KR20100114856A (ko) | 2010-10-26 |
KR101495372B1 (ko) | 2015-02-24 |
US20140162451A1 (en) | 2014-06-12 |
US20160118345A1 (en) | 2016-04-28 |
JP5791167B2 (ja) | 2015-10-07 |
KR101383384B1 (ko) | 2014-04-08 |
TWI623040B (zh) | 2018-05-01 |
US20100267230A1 (en) | 2010-10-21 |
KR20140096253A (ko) | 2014-08-05 |
TW201643963A (zh) | 2016-12-16 |
TW201118948A (en) | 2011-06-01 |
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