TWI523176B - 具有超過四個側邊之通孔結構的半導體元件與其形成方法 - Google Patents

具有超過四個側邊之通孔結構的半導體元件與其形成方法 Download PDF

Info

Publication number
TWI523176B
TWI523176B TW101133093A TW101133093A TWI523176B TW I523176 B TWI523176 B TW I523176B TW 101133093 A TW101133093 A TW 101133093A TW 101133093 A TW101133093 A TW 101133093A TW I523176 B TWI523176 B TW I523176B
Authority
TW
Taiwan
Prior art keywords
sides
rdl
contact pad
passivation layer
hole
Prior art date
Application number
TW101133093A
Other languages
English (en)
Other versions
TW201349415A (zh
Inventor
賴峯良
楊凱元
呂嘉仁
洪聖強
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201349415A publication Critical patent/TW201349415A/zh
Application granted granted Critical
Publication of TWI523176B publication Critical patent/TWI523176B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/0509—Disposition of the additional element of a single via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05684—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

具有超過四個側邊之通孔結構的半導體元件與其形成方法
本發明係關於半導體元件，更特別關於其通孔形狀。
一般的半導體晶粒可藉由不同封裝方法連接至外部的其他元件，比如打線接合法或採用焊料凸塊的覆晶封裝法。半導體晶粒可具有金屬化層，其包括金屬層、介電層、金屬通孔、再佈線層、與後鈍化內連線。打線接合法以接線將積體電路(IC)直接連接至基板。覆晶封裝(或晶圓等級的晶片尺寸封裝(WLCSP))之焊料凸塊的形成方法包括：先形成凸塊下金屬化層於半導體晶粒上，接著將焊料置於凸塊下金屬化層上，再進行再流動製程使焊料定形為所需的凸塊形狀。接著將焊料凸塊置於可物理接觸外部元件的地方，再進行另一再流動製程以接合焊料凸塊與外部元件。上述的打線接合與覆晶封裝，可作為半導體晶粒與外部元件(如印刷電路板、另一半導體晶粒、或類似物)之間的物理與電性連接。
本發明一實施例提供一種半導體元件，包括：接觸墊位於基板上，其中該接觸墊位於該基板上的積體電路上；第一鈍化層位於接觸墊上；以及第一通孔位於第一鈍化層中，其中第一通孔具有超過四個側邊，且其中第一通孔延伸至接觸墊。
本發明一實施例提供一種半導體元件，包括：第一接觸墊位於基板上；第一鈍化層位於第一接觸墊上；第一通 孔穿過第一鈍化層，其中第一通孔具有超過四個側邊；以及第一再佈線層位於第一鈍化層及第一通孔上，其中第一再佈線層經由第一通孔接觸第一接觸墊。
本發明一實施例提供一種半導體元件的形成方法，包括：形成積體電路於基板上；形成接觸墊於該基板上；沉積第一鈍化層於接觸墊上；以及形成第一通孔穿過第一鈍化層，其中第一通孔包括超過四個側邊。
實施例將搭配圖式詳述本發明。圖式與說明中將儘可能以相同標號標示類似元件。在圖式中，形狀與厚度可能稍微增加，這是為了方便本技術領域中具有通常知識者了解本發明。下述說明關於單元的形成方法與裝置。可以理解的是，這些單元並未限定於某種形式，而是本技術領域中具有通常知識者已知的形式。本技術領域中具有通常知識者自可在本發明的教示下變化或改良本發明。
在下述說明中，「一實施例」指的是特定特徵或結構。如此一來，在說明書中不同地方出現的「一實施例」並不必定為相同實施例。此外，特定特徵或結構可以任合適當態樣結合於一或多個實施例中。可以理解的是，下述圖式並未完全依比例繪示，但這些圖式僅用以方便說明。
某些實施例可以特定概念敘述，比如再佈線層通孔位於金屬結構上。然而其他實施例中，可採用後鈍化內連線或其他通孔位於金屬結構上。
如第1a圖所示，部份的半導體晶粒1包含基板10、內連線結構11、第一接觸墊20A、第二接觸墊20B、第一 鈍化層22、第一再佈線層(RDL)通孔開口24a穿過第一鈍化層22、第二RDL通孔開口24B穿過第一鈍化層22、第一RDL 26A、第二RDL 26B、第二鈍化層28與第三鈍化層29位於第一與第二RDL 26A與26B上、第三RDL 30、第四鈍化層32位於第三RDL 30下、凸塊下金屬化層(UBM)開口34、UBM 36、與連接物38。在此實施例中基板10可為矽，而在其他實施例中基板10包括矽鍺合金、氧化矽、氮化物、類似物、或上述之組合。基板10可包含積體電路，其包含主動與被動元件。
內連線結構11包括金屬線路14與通孔16以電性連接多種主動元件與被動元件，進而形成功能電路。金屬線路14與通孔16可採用導電材料如銅、鋁、或類似物，並視情況採用阻障層。金屬線路14與通孔16之形成方法可為單鑲嵌製程及/或雙鑲嵌製程、通孔優先製程、或金屬優先製程。內連線結構11包括多個金屬層M1、Mn、...至Mtop，其中金屬層M1為直接位於基板10上的金屬層，Mn為位於金屬層M1上的層間金屬層，而金屬層Mtop為最頂層的金屬層並直接位於RDL 26下方。在下述說明書中，「金屬層」指的是同一層中的金屬線路。金屬層M1至Mn至Mtop係形成於金屬間介電層(IMD)12中，而IMD 12可為氧化物如氧化矽、硼磷掺雜之矽酸鹽玻璃(BPSG)、未掺雜之矽酸鹽玻璃(USG)、氟化矽酸鹽玻璃(FSG)、低介電常數之介電材料、類似物、或上述之組合。低介電常數之介電材料其介電常數小於3.9。
金屬層Mtop可包括一或多個接觸墊如第一接觸墊 20A與第二接觸墊20B，其形成於內連線結構11之金屬層Mn上並與其電性接觸。第一接觸墊20A與第二接觸墊20B可為銅、鋁、銅鋁合金、鎢、鎳、類似物、或上述之組合。在一實施例中，金屬線路14、第一接觸墊20A、與第二接觸墊20B之厚度介於約0.3μm至約1.2μm之間。在另一實施例中，金屬線路14、第一接觸墊20A、與第二接觸墊20B可為頂金屬，或超厚金屬(UTM)。UTM的厚度為一般頂金屬的厚度之約三倍，或其他金屬層M1至Mn的厚度之約十倍。可以理解的是，說明書中提及的尺寸僅用以舉例，而其他實施例自可變化這些尺寸。
第一鈍化層22係形成於內連線結構11、第一接觸墊20A、與第二接觸墊20B上。在一實施例中，第一鈍化層22之厚度介於約0.7μm至約1μm之間。在形成第一鈍化層22後可移除部份第一鈍化層22，形成一或多個RDL通孔開口(如第一RDL通孔開口24A與第二RDL通孔開口24B)穿過第一鈍化層22，以露出至少部份下方的第一接觸墊20A與第二接觸墊20B。第一RDL通孔開口24A可讓第一接觸墊20A與RDL 26A之間具有接觸如下述。第二RDL通孔開口24B可讓第二接觸墊20B與RDL 26B之間具有接觸如下述。第一RDL通孔開口24A與第二RDL通孔開口24B的形成方法可採用合適的微影光罩與蝕刻製程，或採用露出第一接觸墊20A與第二接觸墊的任何適當製程。在一實施例中，多個RDL通孔開口24中的一者其直徑242介於約1.5μm至約5μm之間，如第2a圖所示。
RDL通孔開口24在上視角中，可具有超過四個側邊。 這些側邊之間的夾角(即內角241)可大於約90°，見第2a至2g圖。如第2a圖所示，RDL通孔開口24為八邊形，且八個內角241為約135°。在一實施例中，RDL通孔開口24的側邊不等長，以第2a圖為例，RDL通孔開口24具有四個長側邊與四個短側邊彼此交錯。四個長側邊實質上彼此等長，而四個短側邊實質上彼此等長。在另一實施例中，RDL通孔開口24可具有等長的側邊。
第2b至2g圖係RDL通孔開口24的其他實施例。第2b圖中的RDL通孔開口24為十邊形，其內角241為約144°。第2c圖中的RDL通孔開口24為十二邊形，其內角241為約150°。第2d圖中的RDL通孔開口24為圓形。在另一實施例中，RDL通孔開口24可具有非常多個側邊，比如超過三十個側邊以形成類圓形。第2e圖中的RDL通孔開口24為五邊形，其內角241為約108°。第2f圖中的RDL通孔開口24為六邊形，其內角241為約120°。第2g圖中的RDL通孔開口24為七邊形，其內角241為約128.6°。本技術領域中具有通常知識者應理解，RDL通孔開口24可為具有任何側邊數目與對應內角的多邊形，並不限於第2a至2g圖所示之實施例。此外，第2b至2g圖中的多邊形可具有不同長度的側邊如第2a圖。
在第1a圖中，第一RDL通孔開口24A與第二RDL通孔開口24B可沿著第一鈍化層22延伸，並電性連接至第一接觸墊20A與第二接觸墊20B。第一RDL 26A與第二RDL 26B可提供第一接觸墊20A、第二接觸墊20B、第三RDL 30、與其他形成於第一RDL 26A與第二RDL 26B上的其 他金屬結構之間的電性連接。在一實施例中，第一RDL 26A與第二RDL 26B可為鋁、銅、銅鋁合金、類似物、或上述組合，其厚度可介於約1.4μm至約2.8μm之間。在某些實施例中，一或多個阻障層(未圖示)係形成於第一RDL通孔開口24A與第二RDL通孔開口24B中，且可為鈦、氮化鈦、鉭、氮化鉭、類似物、或上述之組合。
在形成第一RDL 26A與第二RDL 26B後，可形成第二鈍化層28與第三鈍化層29以保護並電性隔離第一RDL 26A、第二RDL 26B、與其他下方結構。在一實施例中，第二鈍化層28為共形結構，且半導體晶粒1上任何部份的第二鈍化層28具有實質上相同的厚度。第二鈍化層28可為USG、FSG、氧化矽、氮化矽、類似物、或上述之組合。第三鈍化層29可為氮化矽、氧化矽、高分子、類似物、或上述之組合。在一實施例中，第二鈍化層28之厚度介於約1μm至約2μm之間，而第三鈍化層29之厚度為約5μm。
在形成第三鈍化層29後，可沿著第三鈍化層形成第三RDL 30。RDL 30可電性連接第一RDL 26A。第三RDL 30可提供第一RDL 26A、UBM 36、與連接物38之間的電性連接。在一實施例中，RDL 30可為銅、鋁、銅鋁合金、或類似物。
在形成第三RDL 30後，可形成第四鈍化層32以保護並電性隔離RDL 30與其他下方結構。在一實施例中，第四鈍化層32可為氮化矽、氧化矽、高分子、類似物、或上述之組合，且其厚度為約5μm。
在形成第四鈍化層32後，形成穿過第四鈍化層32的 UBM開口34，再形成UBM 36。接著形成連接物38於UBM 36上。
第1b圖係另一實施例的半導體晶粒1。在此實施例中，第1a圖中的第一RDL 26A與第二RDL 26B將電性與物理連接，以形成單一RDL 26。RDL 26電性連接至第一接觸墊20A與第二接觸墊20B。半導體晶粒1的形成方法同前述。
第1c圖為半導體晶粒的又一實施例。在此實施例中，RDL 27經由兩個RDL通孔開口24A1與24A2電性連接至第一接觸墊20A，而非經由單一開口(見第1a及1b圖)。在此實施例中，連接物38為打線接合而非焊料凸塊(見第1a及1b圖)。半導體晶粒1的形成方法同前述。
雖然前述實施例揭露接觸墊、RDL通孔開口、與RDL的特定組態，但其他實施例可採用其他組態，比如更多或更少的接觸墊、RDL通孔開口、或RDL。
第3至10圖係一實施例中，形成半導體晶粒1的製程。雖然此實施例中的步驟有特定順序，但只要是合乎邏輯的順序均可實施。
在第3圖的製程中間階段，金屬層M1至Mtop形成於基板10上。基板10可為矽、矽鍺合金、碳化矽、類似物、或上述之組合。基板10可包含掺雜或未掺雜之基體矽，或絕緣層上矽(SOI)基板的主動層。其他可用的基板包括多層基板、組成漸變式基板、或混合定向基板。
基板10可包含積體電路如主動元件與被動元件(未圖示)。本技術領域中具有通常知識者應理解，為了符合半導 體晶粒1其結構與功能的設計需求，可採用多種主動與被動元件如電晶體、電容、電阻、上述之組合、或類似物。積體電路包括的主動元件與被動元件可由任何合適方法形成。
如第3圖所示，IMD 12、金屬線路14、與通孔16形成於基板10上。在一實施例中，金屬線路14與通孔16可耦合至基板10上的積體電路，使其他元件耦合至積體電路。每一IMD 12可為氧化矽、BPSG、PSG、FSG、類似物、或上述之組合，其形成方法可為化學氣相沉積法(CVD)、高密度電漿CVD(HDP-CVD)、爐沉積法、電漿增強式CVD(PECVD)、類似方法、或上述之組合。每一IMD 12中的金屬線路14與通孔16之形成方法可為鑲嵌製程如雙鑲嵌製程，其組成可包含鋁、銅鋁合金、類似物、或上述之組合。金屬線路14與通孔16之沉積方法可為CVD、原子層沉積(ALD)、物理氣相沉積(PVD)、類似方法、或上述之組合。接著進行研磨製程如化學機械研磨製程(CMP)以移除多餘的導電材料。沿著個別的通孔12及金屬線路14，依序形成IMD 12。
第一接觸墊20A與第二接觸墊20B可形成於金屬線路14與通孔16上。第一接觸墊20A與第二接觸墊20B可包含銅、鋁、銅鋁合金、鎢、鎳、類似物、或上述之組合，且其形成方法可與前述形成金屬線路14之製程類似。在另一實施例中，在形成最上層的IMD 12前，可先形成並圖案化第一接觸墊20A與第二接觸墊20B。第一接觸墊20A與第二接觸墊20B可為UTM，其厚度可為一般頂金屬層厚度 之約三倍，或其他金屬層Mn與M1厚度之約十倍。在另一實施例中，第一接觸墊20A與第二接觸墊20B的厚度可與其他金屬層Mn與M1的厚度相同。必需注意的是，實施例可包含許多其他構件但未描述於此。舉例來說，蝕刻停止層可位於基板10與IMD 12的層狀結構之多個界面之間。此外，IMD 12與金屬層的數目可多於或少於圖示中的數目。
在第4圖中，第一鈍化層22形成於第一接觸墊20A、第二接觸墊20B、與最上層的IMD 12上。第一鈍化層22可為氮化矽、碳化矽、氧化矽、低介電常數之介電材料如掺雜碳的氧化物、超低介電常數之介電材料如孔洞狀掺雜碳的氧化矽、類似物、或上述之組合，且其沉積方法可為CVD或類似方法。
在第5圖中，第一RDL通孔開口24A與第二RDL通孔開口24B形成於第一鈍化層22中。藉由移除部份第一鈍化層22以露出至少部份其下方的第一接觸墊20A與第二接觸墊20B，可形成穿過第一鈍化層22的第一RDL通孔開口24A與第二RDL通孔開口24B。第一RDL通孔開口24A與第二RDL通孔開口24B可讓第一接觸墊20A與第二接觸墊20B，接觸後續形成之第一RDL 26A與第二RDL 26B。第一RDL通孔開口24A與第二RDL通孔開口24B之形成方法可採用合適的微影光罩與蝕刻製程，但亦可為露出部份第一接觸墊20A與第二接觸墊20B的任何合適製程。如第2a至2g圖所示，第一RDL通孔開口24A與第二RDL通孔開口24B於上視角可具有超過四個側邊及大於約 90°的內角。
在第6圖中，第一RDL 26A與第二RDL 26B沿著第一鈍化層22延伸，並分別延伸至第一RDL通孔開口24A與第二RDL通孔開口24B。在某些實施例中，一或多個阻障層(未圖示)可形成於第一RDL通孔開口24A與第二RDL通孔開口24B中，且阻障層之組成可為鈦、氮化鈦、鉭、氮化鉭、類似物、或上述之組合。一或多個阻障層可沿著第一鈍化層22形成，並延伸至第一RDL通孔開口24A與第二RDL通孔開口24B中。鈍化層之形成方法可為CVD、PVD、PECVD、ALD、類似方法、或上述之組合。在一實施例中，第一RDL 26A與第二RDL 26B之形成步驟可先形成晶種層(未圖示)如鈦銅合金於一或多個阻障層上，而晶種層之形成方法為CVD、濺鍍、類似方法、或上述之組合。接著形成光阻層(未圖示)覆蓋晶種層，再圖案化光阻層以露出需形成第一RDL 26A與第二RDL 26B部份的晶種層。在圖案化光阻層後，以沉積製程(如電鍍法、CVD、PVD、類似方法、或上述之組合)將導電材料(如銅、鋁、銅鋁合金、金、類似物、或上述之組合)形成於露出的晶種層上。在形成導電材料後，可採用適當的移除製程如灰化以移除光阻。此外，在移除光阻後可移除之前被光阻覆蓋的晶種層。移除晶種層的製程可為適當的蝕刻製程，且導電材料作為蝕刻製程的遮罩。
在第7圖中，形成第二鈍化層28與第三鈍化層29以保護並電性隔離第一RDL 26A、第二RDL 26B、與其他下方結構。第二鈍化層28可為USG、FSG、氧化矽、氮化矽、 類似物、或上述之組合。第二鈍化層28可順應性地沉積(比如CVD或類似方法)於第一RDL 26A、第二RDL 26B、與第一鈍化層22上。第二鈍化層28在半導體晶粒1的任何位置上具有實質上相等的厚度。第三鈍化層29可為氮化矽、氧化矽、高分子、類似物、或上述之組合。第三鈍化層29之沉積方法可為CVD或類似方法。雖然圖式中有兩層鈍化層形成於第一RDL 26A與第二RDL 26B上，但其他實施例中只有單一鈍化層形成於第一RDL 26A與第二RDL 26B上。
在第8圖中，形成第三RDL 30。在形成第三鈍化層29後，可形成通孔穿過第二鈍化層28與第三鈍化層29以露出部份第一RDL 26A。第三RDL 30係沿著第三鈍化層29形成，並延伸至通孔中。第三RDL可使後續形成的UBM 36電性連接至第一接觸墊20A。UBM 36可位於半導體晶粒1上的任何位置，並不限於直接位於第一接觸墊20A上。在一實施例中，第三RDL 30之形成步驟包括先形成晶種層(未圖示)如鈦銅合金，而晶種層之形成方法可為CVD、濺鍍法、類似方法、或上述之組合。接著形成光阻層(未圖示)覆蓋晶種層，再圖案化光阻層以露出需形成第三RDL 30部份的晶種層。在圖案化光阻層後，以沉積製程(如電鍍法、CVD、PVD、類似方法、或上述之組合)將導電材料(如銅、鋁、銅鋁合金、金、類似物、或上述之組合)形成於露出的晶種層上。在形成導電材料後，可採用適當的移除製程如灰化以移除光阻。此外，在移除光阻後可移除之前被光阻覆蓋的晶種層。移除晶種層的製程可為適當 的蝕刻製程，且導電材料作為蝕刻製程的遮罩。
在第9圖中，形成第四鈍化層32以保護與電性隔離第三RDL 30與其他下方的結構。第四鈍化層32可為氮化矽、氧化矽、高分子、類似物、或上述之組合，其沉積方法可CVD或類似方法，且其厚度可為約5μm。在一實施例中，第四鈍化層32係順應性結構，且半導體晶粒1上的任何位置的第四鈍化層32具有實質上相同的厚度。在另一實施例中，可平坦化第四鈍化層32使其具有實質上平坦的上表面。
在第10圖中，形成UBM 36與連接物38。在形成第四鈍化層32後，移除部份第四鈍化層32以露出其下方至少部份的第三RDL 30，以形成UBM開口34穿過第四鈍化層32。UBM開口34讓UBM 36與第三RDL 30接觸。UBM 34之形成方法可採用合適的微影光罩與蝕刻製程，亦可為露出部份第三RDL 30的任何合適製程。
當第三RDL 30自第四鈍化層32露出後，可形成UBM 36以電性連接至第三RDL 30。UBM 36可為一或多層的導電材料。UBM 36具有多種合適材料的多種排列，比如鉻/鉻-銅合金/銅/金、鈦/鈦鎢合金/銅、或銅/鎳/金。在本發明的範疇中，UBM 36可採用任何適當的材料或層狀排列。
連接物38可為接觸凸塊、打線接合、金屬柱、或類似物，其組成可為錫、銀、無鉛錫、銅、類似物、或上述之組合。在一實施例中，連接物38為接觸凸塊，其形成方法可為先形成導電材料層於UBM 36上，接著進行再流動製程，使導電材料層定型為所需的凸塊形狀。在另一實施例 中，連接物38為打線接合(見第1c圖)。打線接合製程所形成的打線接合連接物可接合第一RDL 26A與第二RDL 26B或第三RDL 30。
上述實施例之優點如下。RDL通孔開口24具有超過四個側邊且其內角大於約90°時，RDL通孔開口24上的第二鈍化層28與第三鈍化層29可避免產生裂縫或碎裂。第11a圖為RDL通孔開口24具有四個側邊且直徑介於1.5μm至4.3μm之間時，RDL通孔開口24上的鈍化層產生裂縫或碎裂的百分比測試。第11b圖為RDL通孔開口24具有八個側邊(內角為135°)且直徑介於1.5μm至4.3μm之間時，RDL通孔開口24上的鈍化層產生裂縫或碎裂的百分比測試。如第11b圖所示，RDL通孔開口24具有八個側邊且內角為135°時，鈍化層產生的裂縫或碎裂最多可降低80%(視通孔尺寸而定)。此外，當通孔尺寸降到約1.5μm至3.3μm之間時，通孔尺寸的製程容忍度極高。
一實施例之半導體元件包括接觸墊位於基板上，其中接觸墊位於基板上的積體電路上，以及第一鈍化層位於接觸墊上。第一通孔位於第一鈍化層中，其中第一通孔具有超過四個側邊，且其中第一通孔延伸至接觸墊。
另一實施例之半導體元件包括第一接觸墊位於基板上，第一鈍化層位於第一接觸墊上，第一通孔穿過第一鈍化層，其中第一通孔具有超過四個側邊，以及第一再佈線層位於第一鈍化層及第一通孔上，其中第一再佈線層經由第一通孔接觸第一接觸墊。
又一實施例之半導體元件的形成方法包括形成積體電 路於基板上，形成接觸墊於基板上，以及沉積第一鈍化層於接觸墊上。上述方法亦形成第一通孔穿過第一鈍化層，其中第一通孔包括超過四個側邊。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
M1、Mn、Mtop‧‧‧金屬層
1‧‧‧半導體晶粒
10‧‧‧基板
11‧‧‧內連線結構
12‧‧‧IMD
14‧‧‧金屬線路
16‧‧‧通孔
20A‧‧‧第一接觸墊
20B‧‧‧第二接觸墊
22‧‧‧第一鈍化層
24‧‧‧RDL通孔開口
24A‧‧‧第一RDL通孔開口
24B‧‧‧第二RDL通孔開口
26A‧‧‧第一RDL
26B‧‧‧第二RDL
28‧‧‧第二鈍化層
29‧‧‧第三鈍化層
30‧‧‧第三RDL
32‧‧‧第四鈍化層
34‧‧‧UBM開口
36‧‧‧UBM
38‧‧‧連接物
241‧‧‧內角
242‧‧‧直徑
第1a圖係一實施例中，半導體元件的剖視圖；第1b圖係另一實施例中，半導體元件的剖視圖；第1c圖係又一實施例中，半導體元件的剖視圖；第2a至2g圖係實施例中，通孔開口之上視圖；第3至10圖係實施例中，形成半導體元件的製程剖視圖；以及第11a及11b圖係實施例中，半導體元件之測試結果。
24‧‧‧通孔開口
241‧‧‧內角
242‧‧‧直徑

Claims (10)

  1. 一種具有超過四個側邊之通孔結構的半導體元件，包括：一接觸墊位於一基板上，其中該接觸墊位於該基板上的一積體電路上；一第一鈍化層位於該接觸墊上；以及一第一通孔位於該第一鈍化層中，其中該第一通孔具有超過四個側邊，且其中該第一通孔延伸至該接觸墊，其中該第一通孔之直徑介於1.5μm至5μm之間。
  2. 如申請專利範圍第1項所述之具有超過四個側邊之通孔結構的半導體元件，其中該接觸墊之厚度介於3μm至12μm之間。
  3. 如申請專利範圍第1項所述之具有超過四個側邊之通孔結構的半導體元件，其中該第一通孔之內角大於90°。
  4. 如申請專利範圍第1項所述之具有超過四個側邊之通孔結構的半導體元件，其中該第一通孔之內角大於或等於135°，且其中該第一通孔具有八個側邊或超過八個側邊。
  5. 一種具有超過四個側邊之通孔結構的半導體元件，包括：一第一接觸墊位於一基板上；一第二接觸墊與該第一接觸墊橫向分開；一第一鈍化層位於該第一接觸墊與該第二接觸墊上；一第一通孔穿過該第一鈍化層，其中該第一通孔具有超過四個側邊；一第二通孔穿過該第一鈍化層，其中該第二通孔具有 超過四個側邊；以及一第一再佈線層位於該第一鈍化層、該第一通孔、與該第二通孔上，其中該第一再佈線層經由該第一通孔接觸該第一接觸墊，並經由該第二通孔接觸該第二接觸墊，且其中該第一再佈線層、該第一通孔、與該第二通孔為連續的導電材料。
  6. 如申請專利範圍第5項所述之具有超過四個側邊之通孔結構的半導體元件，其中該通孔具有具有八個側邊或超過八個側邊，且該通孔之內角大於或等於135°。
  7. 如申請專利範圍第6項所述之具有超過四個側邊之通孔結構的半導體元件，其中該通孔包括四個長側邊與四個短側邊彼此交錯。
  8. 如申請專利範圍第5項所述之具有超過四個側邊之通孔結構的半導體元件，其中該通孔之該些側邊實質上等長。
  9. 一種具有超過四個側邊之通孔結構的半導體元件的形成方法，包括：形成一積體電路於一基板上；形成一接觸墊於該基板上；沉積一第一鈍化層於該接觸墊上；以及形成一第一通孔穿過該第一鈍化層，其中該第一通孔包括超過四個側邊，其中該第一通孔之直徑介於1.5μm至5μm之間。
  10. 如申請專利範圍第9項所述之具有超過四個側邊之通孔結構的半導體元件的形成方法，其中該第一通孔包括 八個側邊或超過八個側邊，且該第一通孔之內角大於或等於135°。
TW101133093A 2012-05-30 2012-09-11 具有超過四個側邊之通孔結構的半導體元件與其形成方法 TWI523176B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/483,999 US20130320522A1 (en) 2012-05-30 2012-05-30 Re-distribution Layer Via Structure and Method of Making Same

Publications (2)

Publication Number Publication Date
TW201349415A TW201349415A (zh) 2013-12-01
TWI523176B true TWI523176B (zh) 2016-02-21

Family

ID=49669231

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101133093A TWI523176B (zh) 2012-05-30 2012-09-11 具有超過四個側邊之通孔結構的半導體元件與其形成方法

Country Status (3)

Country Link
US (1) US20130320522A1 (zh)
KR (1) KR101423383B1 (zh)
TW (1) TWI523176B (zh)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5673627B2 (ja) * 2012-08-03 2015-02-18 トヨタ自動車株式会社 半導体装置及びその製造方法
US10204876B2 (en) * 2013-03-07 2019-02-12 Maxim Integrated Products, Inc. Pad defined contact for wafer level package
US9275925B2 (en) * 2013-03-12 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. System and method for an improved interconnect structure
US10141202B2 (en) * 2013-05-20 2018-11-27 Qualcomm Incorporated Semiconductor device comprising mold for top side and sidewall protection
US9379065B2 (en) * 2013-08-16 2016-06-28 Qualcomm Incorporated Crack stopping structure in wafer level packaging (WLP)
US9165885B2 (en) * 2013-12-30 2015-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Staggered via redistribution layer (RDL) for a package and a method for forming the same
TWI576869B (zh) * 2014-01-24 2017-04-01 精材科技股份有限公司 被動元件結構及其製作方法
US9373594B2 (en) 2014-02-13 2016-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Under bump metallization
US9704841B2 (en) * 2014-03-26 2017-07-11 United Microelectronics Corp. Method of packaging stacked dies on wafer using flip-chip bonding
US9449908B2 (en) 2014-07-30 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package system and method
TWI556386B (zh) * 2015-03-27 2016-11-01 南茂科技股份有限公司 半導體結構
KR102450326B1 (ko) 2015-10-06 2022-10-05 삼성전자주식회사 반도체 칩, 이의 제조방법, 및 이를 포함하는 반도체 패키지
US9893028B2 (en) * 2015-12-28 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Bond structures and the methods of forming the same
KR102406573B1 (ko) 2017-04-28 2022-06-09 삼성전자주식회사 반도체 소자 및 그 제조 방법
KR102029535B1 (ko) * 2017-08-28 2019-10-07 삼성전기주식회사 팬-아웃 반도체 패키지
US10249583B1 (en) * 2017-09-19 2019-04-02 Infineon Technologies Ag Semiconductor die bond pad with insulating separator
US10340229B2 (en) 2017-10-11 2019-07-02 Globalfoundries Inc. Semiconductor device with superior crack resistivity in the metallization system
KR102082821B1 (ko) * 2018-03-12 2020-04-23 하나 마이크론(주) 재배선 구조를 갖는 반도체 소자와 웨이퍼 레벨 패키지 및 그 제조 방법
US10658315B2 (en) 2018-03-27 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Redistribution layer metallic structure and method
KR102540961B1 (ko) 2018-07-05 2023-06-07 삼성전자주식회사 반도체 칩, 및 이를 가지는 반도체 패키지
KR102527569B1 (ko) * 2018-10-16 2023-05-03 에스케이하이닉스 주식회사 재배선층 구조를 포함하는 반도체 장치 및 제조 방법
CN112582398A (zh) * 2019-09-30 2021-03-30 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US11127674B2 (en) * 2019-10-16 2021-09-21 Globalfoundries U.S. Inc. Back end of the line metal structure and method
US11211301B2 (en) 2020-02-11 2021-12-28 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and method of manufacture
US11817406B2 (en) * 2021-09-23 2023-11-14 Qualcomm Incorporated Semiconductor die employing repurposed seed layer for forming additional signal paths to back end-of-line (BEOL) structure, and related integrated circuit (IC) packages and fabrication methods

Family Cites Families (52)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4196443A (en) * 1978-08-25 1980-04-01 Rca Corporation Buried contact configuration for CMOS/SOS integrated circuits
US4342045A (en) * 1980-04-28 1982-07-27 Advanced Micro Devices, Inc. Input protection device for integrated circuits
EP0510667B1 (en) * 1991-04-26 1996-09-11 Canon Kabushiki Kaisha Semiconductor device having an improved insulated gate transistor
US5412239A (en) * 1993-05-14 1995-05-02 Siliconix Incorporated Contact geometry for improved lateral MOSFET
JP3028080B2 (ja) * 1997-06-18 2000-04-04 日本電気株式会社 半導体装置の構造およびその製造方法
KR100230428B1 (ko) * 1997-06-24 1999-11-15 윤종용 다층 도전성 패드를 구비하는 반도체장치 및 그 제조방법
US7381642B2 (en) * 2004-09-23 2008-06-03 Megica Corporation Top layers of metal for integrated circuits
CN1220257C (zh) * 1999-07-08 2005-09-21 株式会社日立制作所 半导体器件及其制造方法
US6362087B1 (en) * 2000-05-05 2002-03-26 Aptos Corporation Method for fabricating a microelectronic fabrication having formed therein a redistribution structure
US6300234B1 (en) * 2000-06-26 2001-10-09 Motorola, Inc. Process for forming an electrical device
US6700203B1 (en) * 2000-10-11 2004-03-02 International Business Machines Corporation Semiconductor structure having in-situ formed unit resistors
US7088002B2 (en) * 2000-12-18 2006-08-08 Intel Corporation Interconnect
US6518675B2 (en) * 2000-12-29 2003-02-11 Samsung Electronics Co., Ltd. Wafer level package and method for manufacturing the same
JP2003045877A (ja) * 2001-08-01 2003-02-14 Sharp Corp 半導体装置およびその製造方法
JP4068838B2 (ja) * 2001-12-07 2008-03-26 株式会社日立製作所 半導体装置の製造方法
US7932603B2 (en) * 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
US6614091B1 (en) * 2002-03-13 2003-09-02 Motorola, Inc. Semiconductor device having a wire bond pad and method therefor
US6987031B2 (en) * 2002-08-27 2006-01-17 Micron Technology, Inc. Multiple chip semiconductor package and method of fabricating same
US6885101B2 (en) * 2002-08-29 2005-04-26 Micron Technology, Inc. Methods for wafer-level packaging of microelectronic devices and microelectronic devices formed by such methods
JP2006505933A (ja) * 2002-11-08 2006-02-16 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 少なくとも一つのバンプを有する集積回路
US6943446B2 (en) * 2002-11-08 2005-09-13 Lsi Logic Corporation Via construction for structural support
JP4502173B2 (ja) * 2003-02-03 2010-07-14 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
US6717270B1 (en) * 2003-04-09 2004-04-06 Motorola, Inc. Integrated circuit die I/O cells
DE10320579A1 (de) * 2003-05-07 2004-08-26 Infineon Technologies Ag Halbleiterwafer, Nutzen und elektronisches Bauteil mit gestapelten Halbleiterchips, sowie Verfahren zur Herstellung derselben
JP2005116756A (ja) * 2003-10-07 2005-04-28 Fujitsu Ltd 半導体装置及びその製造方法
US7095116B1 (en) * 2003-12-01 2006-08-22 National Semiconductor Corporation Aluminum-free under bump metallization structure
US7115985B2 (en) * 2004-09-30 2006-10-03 Agere Systems, Inc. Reinforced bond pad for a semiconductor device
JP4795677B2 (ja) * 2004-12-02 2011-10-19 ルネサスエレクトロニクス株式会社 半導体装置およびそれを用いた半導体モジュール、ならびに半導体装置の製造方法
US20060163734A1 (en) * 2005-01-24 2006-07-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fuse structure and method for making the same
JP2006303169A (ja) * 2005-04-20 2006-11-02 Seiko Epson Corp 半導体装置
JP2006339584A (ja) * 2005-06-06 2006-12-14 Sharp Corp 半導体装置およびその製造方法
US7215032B2 (en) * 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
TWI281699B (en) * 2005-07-26 2007-05-21 Siliconware Precision Industries Co Ltd Semiconductor device and fabrication method thereof
KR100804392B1 (ko) * 2005-12-02 2008-02-15 주식회사 네패스 반도체 패키지 및 그 제조 방법
US7385283B2 (en) * 2006-06-27 2008-06-10 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit and method of making the same
KR100764055B1 (ko) * 2006-09-07 2007-10-08 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 및 칩 스케일 패키지의 제조방법
TWI313037B (en) * 2006-12-12 2009-08-01 Siliconware Precision Industries Co Ltd Chip scale package structure and method for fabricating the same
US7547630B2 (en) * 2007-09-26 2009-06-16 Texas Instruments Incorporated Method for stacking semiconductor chips
JP5329068B2 (ja) * 2007-10-22 2013-10-30 ルネサスエレクトロニクス株式会社 半導体装置
EP2195837A1 (en) * 2007-10-31 2010-06-16 Agere Systems Inc. Bond pad support structure for semiconductor device
KR20090070916A (ko) * 2007-12-27 2009-07-01 삼성전기주식회사 반도체 장치 및 그 제조방법
US7880297B2 (en) * 2007-12-31 2011-02-01 Mediatek Inc. Semiconductor chip having conductive member for reducing localized voltage drop
US7821038B2 (en) * 2008-03-21 2010-10-26 Mediatek Inc. Power and ground routing of integrated circuit devices with improved IR drop and chip performance
US8274146B2 (en) * 2008-05-30 2012-09-25 Freescale Semiconductor, Inc. High frequency interconnect pad structure
JP5350022B2 (ja) * 2009-03-04 2013-11-27 パナソニック株式会社 半導体装置、及び該半導体装置を備えた実装体
US8759949B2 (en) * 2009-04-30 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside structures having copper pillars
EP2278614B1 (fr) * 2009-07-21 2013-04-03 STMicroelectronics (Crolles 2) SAS Via de connexion électrique comportant des excroissances latérales
US8274139B2 (en) * 2009-07-21 2012-09-25 Stmicroelectronics (Crolles 2) Sas Scalloped tubular electric via
US8203209B2 (en) * 2009-08-07 2012-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad design for reducing the effect of package stress
JP5383446B2 (ja) * 2009-11-18 2014-01-08 パナソニック株式会社 半導体装置
US8501618B2 (en) * 2010-07-26 2013-08-06 Stats Chippac, Ltd. Semiconductor device and method of forming RDL wider than contact pad along first axis and narrower than contact pad along second axis
US8441131B2 (en) * 2011-09-12 2013-05-14 Globalfoundries Inc. Strain-compensating fill patterns for controlling semiconductor chip package interactions

Also Published As

Publication number Publication date
KR20130134991A (ko) 2013-12-10
US20130320522A1 (en) 2013-12-05
TW201349415A (zh) 2013-12-01
KR101423383B1 (ko) 2014-07-24

Similar Documents

Publication Publication Date Title
TWI523176B (zh) 具有超過四個側邊之通孔結構的半導體元件與其形成方法
US11417599B2 (en) Plurality of different size metal layers for a pad structure
TWI470756B (zh) 半導體結構及形成半導體裝置的方法
US10153205B2 (en) Package with metal-insulator-metal capacitor and method of manufacturing the same
US8299616B2 (en) T-shaped post for semiconductor devices
US10163756B2 (en) Isolation structure for stacked dies
US11824026B2 (en) Connector structure and method of forming same
US8741732B2 (en) Forming metal-insulator-metal capacitors over a top metal layer
US8546945B2 (en) Pillar structure having a non-planar surface for semiconductor devices
TWI408786B (zh) 半導體元件之銲墊結構
US8531035B2 (en) Interconnect barrier structure and method
US8294264B2 (en) Radiate under-bump metallization structure for semiconductor devices
US20130292827A1 (en) Pillar Structure having a Non-Planar Surface for Semiconductor Devices
US11688728B2 (en) Integrated circuit structure and method for reducing polymer layer delamination
US11373970B2 (en) Semiconductor device having a redistribution line
US20220359642A1 (en) Structure and Method for Forming Integrated High Density Mim Capacitor
US20100072629A1 (en) Wiring Structure, Semiconductor Device Having the Wiring Structure, and Method for Manufacturing the Semiconductor Device
US20230360946A1 (en) Method for forming semiconductor structure