TWI556386B - 半導體結構 - Google Patents

半導體結構 Download PDF

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Publication number
TWI556386B
TWI556386B TW104109922A TW104109922A TWI556386B TW I556386 B TWI556386 B TW I556386B TW 104109922 A TW104109922 A TW 104109922A TW 104109922 A TW104109922 A TW 104109922A TW I556386 B TWI556386 B TW I556386B
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Taiwan
Prior art keywords
wiring
insulating layer
semiconductor structure
holes
dielectric layer
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TW104109922A
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English (en)
Other versions
TW201635460A (zh
Inventor
陳聖白
Original Assignee
南茂科技股份有限公司
百慕達南茂科技股份有限公司
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Application filed by 南茂科技股份有限公司, 百慕達南茂科技股份有限公司 filed Critical 南茂科技股份有限公司
Priority to TW104109922A priority Critical patent/TWI556386B/zh
Priority to US14/856,469 priority patent/US20160284639A1/en
Priority to CN201510657183.9A priority patent/CN106024751A/zh
Publication of TW201635460A publication Critical patent/TW201635460A/zh
Application granted granted Critical
Publication of TWI556386B publication Critical patent/TWI556386B/zh

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Description

半導體結構
本揭露涉及一種半導體結構，更具體地說，涉及一種半導體結構，其佈線具有複數個孔洞。
晶圓級封裝(Wafer Level Packaging,WLP)前段製程為晶圓凸塊(Wafer Bumping)，就凸塊製程(Bumping)而言，主要包括球下金屬層(Under Bump Metallurgy,UBM)與銲錫凸塊(Solder Bump)兩部份；在球下金屬層的進階製程裡則引進線路重佈技術以調整元件的輸出入位置，進而提升元件的結構穩定性。在重佈線路(Redistribution,RDL)製程中，因電鍍金屬的線路(例如銅)與塗佈之聚合物介電層(Polymer Dielectric layer)間的黏著度不好，易造成聚合物介電層與線路脫層(delamination)的缺陷，造成產品在長期可靠度測試中失敗。此外，在可靠度溫度循環測試(Thermal Cycling Test,TCT)過程中，因不同材料間(例如介電層所使用的高分子材料和佈線層所使用的金屬材料)之熱膨脹係數( coefficient of thermal expansion,CTE)的差異，材料間之介面易累積熱應力而產生脫層導致裂縫，影響產品功能及壽命。
有鑑於此，本領域亟需一種新穎的設計來改善上述相關問題。
本揭露提供一種半導體結構，其包含一半導體基板、一絕緣層以及多個佈線。絕緣層設置於半導體基板之上。佈線設置於半導體基板與絕緣層之間，佈線的至少其中之一包含複數個孔洞，其中孔洞口徑總面積占該佈線之表面積介於10%至70%之間。
本揭露另提供一種半導體結構，其包含一半導體基板、一介電層、多個佈線以及一絕緣層。介電層設置於半導體基板上。佈線設置於介電層上，且佈線的至少其中之一包含複數個孔洞。絕緣層設置於半導體基板上，絕緣層局部覆蓋佈線，且部分絕緣層容置於孔洞中並經由孔洞接觸介電層。其中孔洞口徑總面積占該佈線之表面積介於10%至70%之間。
本發明所提出的實施例可藉由在佈線上形成孔洞以提升佈線與絕緣層彼此間的結合力，並改善佈線與絕緣層之間的脫層問題。上文已相當廣泛地概述本揭露之技術特徵，俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其他技術特徵將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解，可相當容易地利用下文 揭示之概念與特定實施例可作為修改或設計其他結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解，這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
10‧‧‧半導體結構
11‧‧‧半導體基板
12‧‧‧金屬墊
13‧‧‧介電層
14‧‧‧保護層
15‧‧‧佈線
151‧‧‧晶種層
152‧‧‧導電層
153‧‧‧接墊
16‧‧‧絕緣層
20‧‧‧孔洞
21‧‧‧突起部
30‧‧‧凸塊
下列圖示係併入說明書內容之一部分，以供闡述本揭露之各種實施例，進而清楚解釋本揭露之技術原理。
為了使本揭露之敘述更加詳盡與完備，可參照下列描述並配合下列圖式，其中類似的元件符號代表類似的元件。然以下實施例中所述，僅用以說明本揭露，並非用以限制本揭露的範圍。
圖1為本發明之半導體結構之第一實施例的剖面圖；圖2為圖1之半導體結構的俯視圖；圖3A為本發明之半導體結構之第二實施例的俯視圖；圖3B為本發明之半導體結構之第三實施例的俯視圖；圖4為本發明之半導體結構之第四實施例的俯視圖；圖5A為本發明之半導體結構之第五實施例的俯視圖；圖5B為本發明之半導體結構之第六實施例的俯視圖；以及圖5C為本發明之半導體結構之第七實施例的俯視圖。
本揭露之半導體結構包含下列所述的各種圖式，然而並 不限於此，亦可因應不同的設計而省略或修正特定結構。
在此說明書及申請專利範圍中的名詞「上」包含第一物件直接或間接地設置於第二物件的上方。例如，第一元件設置於第二元件上就包含，第一元件「直接」設置於第二元件上及第一元件「間接」設置於第二元件上，兩種意義。此處的「間接」係指第一元件及第二元件在某一方位的垂直方向中具有上與下的關係，且兩者中間仍有其他物體、物質或間隔將兩者隔開。
圖1為根據本發明之一實施例之半導體結構之剖面圖。為方便描述本發明特徵，圖2~圖5為本發明之一實施例省略繪示絕緣層及凸塊後之半導體結構之俯視圖。如圖1所示，提供一半導體結構10，而半導體結構10包含一半導體基板11、一金屬墊12、一介電層13、一保護層(passivation layer)14、複數個佈線15以及一絕緣層16。金屬墊12形成於半導體基板11上。金屬墊12可例如是半導體晶圓上的積體電路之輸出入(I/O)墊，其材質可包含鋁、銅或其他適合的材質。保護層14設置於半導體基板11上，保護層14具有一開口局部暴露出金屬墊12，換言之，金屬墊12的一部分為保護層14所覆蓋，而金屬墊12的其餘部分則為保護層14之開口所暴露出來。保護層14係設置於半導體基板11上的電絕緣性的表面層，或稱為鈍化層，其材質可為氧化矽(Silicon Oxide)、氮化矽(Silicon Nitride)、氮化物(Nitride)、聚亞醯胺(Polyimide；PI)、苯環丁烯(Benzocyclobutene；BCB)或磷矽玻璃(Phosphosilicate Glass)等 ，可藉由化學氣相沉積(CVD)技術形成，用以保護半導體基板11上之積體電路(包含金屬墊12)。介電層13設置於保護層14上，且具有一開口對應保護層14之開口，也就是介電層13之開口也局部暴露出金屬墊12。請注意，本發明對於半導體基板11上的金屬墊12數目並不多作限制，在某些實施例中，半導體基板11上可以具有複數個金屬墊12，且各個金屬墊12分別對應一保護層開口和一介電層開口。於本實施例中，介電層13延伸入保護層14的開口中，換言之，介電層13的開口小於對應的保護層14的開口，因此保護層14是完全為介電層13所覆蓋。然而，於其他實施例中，介電層13的開口可不小於對應的保護層14的開口，使得保護層14局部為介電層13所暴露出。如圖1所示，介電層13係沿X軸間接設置於半導體基板11上。
複數個佈線15設置於介電層13上，在本實施例中，佈線15包含一晶種層151及一導電層152，其中導電層152係形成於晶種層151之上，且佈線15的至少其中之一係填入介電層13及保護層14的開口中而與金屬墊12相連接，並於介電層13上往遠離金屬墊12的方向延伸，即所謂的重佈線層(Redistribution Layer；RDL)。重佈線層的目的是為了因應不同需求將半導體基板11上的金屬墊12重新配置到其他位置。具體而言，佈線15的材料例如是鈦/銅、鈦/銅/金或鈦/銅/鎳/金等。以鈦/銅為例，佈線15可先以濺鍍技術形成鈦/銅薄層的晶種層151，再於晶種層151上以電鍍技術形成有足夠厚度的銅的導電層152。因此，電性訊號可藉由佈線15由半導體基板11上的金屬墊12傳輸至其他 元件(圖未繪示)。如圖1所示，佈線15更包含一接墊153，以供設置一凸塊30。凸塊30設置於接墊153上，換言之，凸塊30可經由佈線15電性連接至金屬墊12。凸塊30可為銲錫凸塊、電鍍凸塊、無電鍍凸塊、結線凸塊、導電聚合物凸塊或金屬複合凸塊，其材料可選自下列群組：錫、銅、金、銀、銦、鎳/金、鎳/鈀/金、銅/鎳/金、銅/金、鋁及其合金。於本實施例中，凸塊30為銲錫凸塊，其經由迴銲製程而接合於接墊153上。
絕緣層16設置於介電層13上並局部覆蓋佈線15。具體而言，絕緣層16具有開口分別局部暴露出各個接墊153，以供凸塊30設置於接墊153上。如圖1所示，絕緣層16係沿X軸間接設置於半導體基板11上。介電層13和絕緣層16可以係選自由聚亞醯胺(PI)、聚苯並噁唑(Polybenzoxazole；PBO)、苯環丁烯(BCB)及環氧樹脂(Epoxy)所組成的群組。
請同時參考圖1及圖2，圖2為圖1之半導體結構的俯視圖，請注意，為便於示意，圖2中並未繪示出覆蓋於介電層13與佈線15之上的絕緣層16與凸塊30。佈線15中的至少其中之一佈線15包含複數個孔洞20。孔洞20之口徑總面積占該至少其中之一佈線15之表面積介於大約10%至大約70%之間，上述之比例可根據絕緣層16與介電層13和佈線15之間的熱膨脹係數差異而定，且該至少其中之一佈線15因形成孔洞20而減少之金屬密度以不影響佈線15之電性傳輸效能為主。孔洞20有助於絕緣層16與佈線15之間的接觸面積增加，利用接觸面積增加提升佈線15與絕緣層16彼此間的整體結合力，故此種設計能避免 佈線15與絕緣層16產生脫層的現象。具體而言，當絕緣層16局部覆蓋佈線15後，部分絕緣層16會容置於孔洞20中。孔洞20可以包含未貫穿佈線15的盲孔及/或貫穿佈線15的貫通孔。當孔洞20為貫通孔時，絕緣層16可經由孔洞20接觸介電層13。且當絕緣層16及介電層13為相同或相近似之材質時，絕緣層16與介電層13更可經由孔洞20而連結成一體，使其與佈線15之間的結合力更進一步提升，以避免脫層現象。此外，由於佈線15為金屬材質，例如銅，銅的熱膨脹係數約為16-17ppm/℃，而絕緣層16與介電層13為塑膠材質，例如聚亞醯胺，其熱膨脹係數變異很大，可能高達80ppm/℃，兩種異質材料之間的熱膨脹係數差異甚鉅，而熱膨脹係數不匹配會使兩種材料之間產生熱應力，進而造成脫層的現象。本發明藉由於佈線15形成孔洞20，使佈線15之金屬密度降低，由於金屬比例減少，金屬與塑膠材料之間的熱膨脹係數不匹配程度降低，減少了熱機械應力的產生，進而避免脫層現象的發生。圖3A為本發明之半導體結構之第二實施例的俯視圖，圖3B為本發明之半導體結構之第三實施例的俯視圖。請注意，為便於示意，圖3A和圖3B中並未繪示出覆蓋於介電層13與佈線15之上的絕緣層16與凸塊30。如圖3A和圖3B所示，除了圓形之外，孔洞20的形狀更可包含但不限於長條形、橢圓形、三角形、梯形、梳形等形狀。
圖4為本發明之半導體結構之第四實施例的俯視圖。請注意，為便於示意，圖4中並未繪示出覆蓋於介電層13與佈線15 之上的絕緣層16與凸塊30。如圖4所示，除了佈線15之主要線段處形成有孔洞20之外，接墊153處也可形成孔洞20。因此當凸塊30設置於接墊153上時，部分凸塊30可容置於孔洞20內，藉由孔洞20增加凸塊30與接墊153之間的接觸面積，進而提升凸塊30與接墊153彼此間的結合力，此種設計能避免凸塊30從接墊153脫落。相同地，位於接墊153處之孔洞20也可以包含未貫穿接墊153的盲孔及/或貫穿接墊153的貫通孔。當孔洞20為貫通孔時，凸塊30可透過孔洞20接觸介電層13。
圖5A至圖5C為本發明之半導體結構之第五至第七實施例的俯視圖。請注意，為便於示意，圖5A至圖5C中並未繪示出覆蓋於介電層13與佈線15之上的絕緣層16與凸塊30。如圖5A至圖5C所示，佈線15之邊緣進一步包含複數個突起部21。突起部21包含但不限於圓弧形、波浪形、方形、梯形、鋸齒形等形狀。突起部21之總面積占佈線15之表面積介於5%至30%之間。由於突起部21可增加佈線15與介電層13及絕緣層16的接觸面積，利用接觸面積增加提升佈線15與絕緣層16及介電層13彼此間的結合力，因此能避免佈線15與介電層13及絕緣層16產生脫層的現象。此外，由於絕緣層16可填入相鄰突起部21間所形成的空間內，絕緣層16與佈線15之間形成多個彼此囓合的卡扣元件，可更進一步提升佈線15與絕緣層16之間的接合力。突起部21之總面積占佈線15之表面積的比例可根據絕緣層16與介電層13及佈線15之間的熱膨脹係數差異而定義。孔洞20的形狀與突起部21的形狀可依據需求作任意組合，而不限於圖 5A至5C所示。
本發明所提出的實施例可藉由在佈線上形成孔洞以增加絕緣層與佈線之間的整體接觸面積，降低熱膨脹係數不匹配程度，進而提升佈線與絕緣層彼此間的結合力，以改善佈線與絕緣層之間的脫層問題。此外，亦可進一步藉由在佈線之邊緣形成突起部來增加絕緣層與佈線之間的整體接觸面積，來更加地避免發生脫層現象。本發明亦可應用來增加佈線的接墊部分與凸塊彼此間的結合力，避免凸塊從接墊脫落。
本揭露之技術內容及技術特點已揭示如上，然而本揭露所屬技術領域中具有通常知識者應瞭解，在不背離後附申請專利範圍所界定之本揭露精神和範圍內，本揭露之教示及揭示可作種種之替換及修飾。例如，上文揭示之許多裝置或結構可以不同之方法實施或以其它結構予以取代，或者採用上述二種方式之組合。
10‧‧‧半導體結構
11‧‧‧半導體基板
12‧‧‧金屬墊
13‧‧‧介電層
14‧‧‧保護層
15‧‧‧佈線
151‧‧‧晶種層
152‧‧‧導電層
153‧‧‧接墊
16‧‧‧絕緣層
20‧‧‧孔洞
30‧‧‧凸塊

Claims (17)

  1. 一種半導體結構，包含：一半導體基板；一絕緣層設置於該半導體基板之上；以及複數個佈線設置於該半導體基板與該絕緣層之間，該些佈線的至少其中之一包含複數個孔洞，其中該些孔洞口徑的總面積占該至少一佈線之表面積介於10%至70%之間，其中該些孔洞口徑總面積占該至少一佈線之表面積的比例係根據該絕緣層及該至少一佈線之間的熱膨脹係數差異而定義。
  2. 根據請求項1所述之半導體結構，其中該絕緣層局部覆蓋該至少一佈線，且部分該絕緣層容置於該些孔洞中。
  3. 根據請求項1所述之半導體結構，進一步包含一介電層設置於該半導體基板與該些佈線之間，該絕緣層經由該些孔洞接觸該介電層。
  4. 根據請求項1所述之半導體結構，其中該至少一佈線之邊緣進一步包含複數個突起部。
  5. 根據請求項4所述之半導體結構，其中該些突起部之總面積占該至少一佈線之表面積介於5%至30%之間。
  6. 根據請求項5所述之半導體結構，其中該些突起部之總面積占該至少一佈線之表面積的比例係根據該絕緣層及該至少一佈線之間的熱膨脹係數差異而定義。
  7. 根據請求項1所述之半導體結構，其中該至少一佈線包含一接墊係供設置一凸塊。
  8. 根據請求項7所述之半導體結構，其中該絕緣層局部暴露出該接墊。
  9. 根據請求項8所述之半導體結構，其中該些孔洞的至少其中之一設置於該接墊。
  10. 根據請求項1所述之半導體結構，其中該些孔洞貫穿該至少一佈線。
  11. 一種半導體結構，包含：一半導體基板；一介電層設置於該半導體基板上；複數個佈線設置於該介電層上，該些佈線的至少其中之一包含複數個孔洞；以及一絕緣層設置於該半導體基板之上，該絕緣層局部覆蓋該些佈線，且部分該絕緣層容置於該些孔洞中並經由該些孔洞接觸該介電層；其中該些孔洞口徑總面積占該至少一佈線之表面積介於10%至70%之間，其中該些孔洞口徑總面積占該至少一佈線之表面積的比例係根據該絕緣層及該至少一佈線之間的熱膨脹係數差異而定義。
  12. 根據請求項11所述之半導體結構，其中該至少一佈線之邊緣進一步包含複數個突起部。
  13. 根據請求項12所述之半導體結構，其中該些突起部之總面積占該至少一佈線之表面積介於5%至30%之間。
  14. 根據請求項13所述之半導體結構，其中該些突起部之總面積占該至少一佈線之表面積的比例係根據該絕緣層及該至少一 佈線之間的熱膨脹係數差異而定義。
  15. 根據請求項11所述之半導體結構，其中該至少一佈線包含一接墊係供設置一凸塊。
  16. 根據請求項15所述之半導體結構，其中該絕緣層局部暴露出該接墊。
  17. 根據請求項16所述之半導體結構，其中該些孔洞的至少其中之一設置於該接墊。
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