TWI518854B - 模封組件及模封材料 - Google Patents

模封組件及模封材料 Download PDF

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Publication number
TWI518854B
TWI518854B TW102148974A TW102148974A TWI518854B TW I518854 B TWI518854 B TW I518854B TW 102148974 A TW102148974 A TW 102148974A TW 102148974 A TW102148974 A TW 102148974A TW I518854 B TWI518854 B TW I518854B
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Taiwan
Prior art keywords
molding
substrate
suppression structure
molding material
semiconductor element
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TW102148974A
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English (en)
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TW201526175A (zh
Inventor
林育民
詹朝傑
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財團法人工業技術研究院
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Application filed by 財團法人工業技術研究院 filed Critical 財團法人工業技術研究院
Priority to TW102148974A priority Critical patent/TWI518854B/zh
Priority to CN201410552591.3A priority patent/CN104752372B/zh
Priority to US14/561,546 priority patent/US9391049B2/en
Publication of TW201526175A publication Critical patent/TW201526175A/zh
Application granted granted Critical
Publication of TWI518854B publication Critical patent/TWI518854B/zh

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    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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Description

模封組件及模封材料
本揭露係關於一種模封組件及模封材料，具體而言，係關於一種可抵抗翹曲之模封材料及模封組件。
在電子封裝領域中，有些應用架構是必須在晶片對晶圓組裝(CoW assembly)之後，進行模封作業(molding process)以及晶圓薄化作業(wafer thinning)。
影響電子產品良率之因素包括晶片高度均勻性、晶片分佈均勻性、模封材料與晶片的硬度、剛性、熱膨脹係數、玻璃轉化溫度等性質、晶圓的翹曲量、翹曲均勻性等性質。
目前發現，在經過模封作業後，整體模封件會出現嚴重的翹曲現象，導致要進行後續研磨作業時，研磨機台無法有效吸真空。再者，即使研磨機台可以吸真空，卻發現研磨完成後晶圓的邊緣外露於模封材料外，因此，薄化過程中輕微的翹曲或晶片的分布仍會影響整體的薄化均勻度。另外，翹曲亦有可能導致後續可靠度的問題產生。
因此，防止晶圓之翹曲是業界極待解決的課題。
本揭露提供一種模封組件，係包含：基板，具有相對之第一 表面及第二表面；第一模封件，位於該基板之該第一表面上，該第一模封件包含：第一導電元件，位於該基板之該第一表面上；第一半導體元件，藉由該第一導電元件而與該基板電性連接；第一翹曲抑制結構，位於該第一半導體元件之周圍；第一模封材料，位於該基板之第一表面上，用於包覆該第一半導體元件、該第一導電元件及第一翹曲抑制結構；以及第一保護層，位於該第一半導體元件、該第一模封材料及該第一翹曲抑制結構上；以及第二模封件，位於該第一模封件上，包含：第二導電元件，位於該第一半導體元件上；第二半導體元件，藉由該第二導電元件而與該第一半導體元件電性連接；第二翹曲抑制結構，位於該第二半導體元件之周圍；第二模封材料，位於該第一模封件之該第一保護層上，用於包覆該第二半導體元件、該第二導電元件及該第二翹曲抑制結構；以及第二保護層，位於該第二半導體元件、該第二模封材料及該第二翹曲抑制結構上。更包含第三模封件位於該第二模封件上，包含：第三導電元件，位於該第二半導體元件上；第三半導體元件，藉由該第三導電元件而與該第二半導體元件電性連接；第三翹曲抑制結構，位於該第三半導體元件之周圍；以及第三模封材料，位於該第二模封件之該第二保護層上，用於包覆該第三半導體元件、該第三導電元件及該第三翹曲抑制結構。該第三模封件更包括第三保護層，位於該第三半導體元件、該第三模封材料及該第三翹曲抑制結構上。更包含第四導電元件位於該基板之該第二表面，其中該基板、該第一半導體元件和該第二半導體元件分別具有複數個貫穿電極。
本揭露另提供一種模封材料，係包括：本體；以及翹曲抑制 結構，包含：位於該本體內的邊緣之環狀部、位於該環狀部的內側之格柵以及連接該環狀部與該格柵之連接部，該翹曲抑制結構用於防止該模封材料於模封程序時之翹曲。
上述之模封材料包含平行堆疊之第一材料層及第二材料層，該第一材料層中的粒子尺寸係小於該第二材料層的粒子尺寸。上述翹曲抑制結構的材料硬度大於矽。
相較於先前技術，本揭露之模封材料中設計有翹曲抑制結構，俾於製作模封組件而於模封程序中防止翹曲之產生，並有益於後續之薄化作業。
1‧‧‧基板
11‧‧‧第一表面
12‧‧‧第二表面
13、31、631、731‧‧‧貫穿電極
2‧‧‧導電元件
3‧‧‧半導體元件
4‧‧‧模封材料
41‧‧‧第二材料層
42‧‧‧第一材料層
5‧‧‧翹曲抑制結構
51‧‧‧第一環狀部
52‧‧‧第二環狀部
53‧‧‧連接部
54‧‧‧格柵
6‧‧‧第一模封件
62‧‧‧第一導電元件
63‧‧‧第一半導體元件
64‧‧‧第一模封材料
65‧‧‧第一翹曲抑制結構
66‧‧‧第一保護層
7‧‧‧第二模封件
72‧‧‧第二導電元件
73‧‧‧第二半導體元件
74‧‧‧第二模封材料
75‧‧‧第二翹曲抑制結構
76‧‧‧第二保護層
8‧‧‧第四導電元件
9‧‧‧第三模封件
92‧‧‧第三導電元件
93‧‧‧第三半導體元件
94‧‧‧第三模封材料
95‧‧‧第三翹曲抑制結構
第1圖為本揭露之模封件之第一實施例之俯視示意圖；第2A至2D圖為本揭露之模封件之第一實施例之製法示意圖；第3圖為本揭露之模封件之第二實施例之俯視示意圖；第4A至4D圖為本揭露之模封件之第二實施例之製法示意圖；第5A圖為本揭露之模封件之第三實施例之俯視示意圖；第5B圖為本揭露之模封材料之剖視示意圖；第5C圖為本揭露之模封件之第三實施例之剖視示意圖；第6圖為本揭露之模封件之第四實施例之剖視示意圖；以及第7A至7E圖為本揭露之模封組件之製作流程示意圖，其中，第7D’圖為第7D圖之進一步實施例，第7E’圖為第7E圖之進一步實施例。
以下藉由特定的具體實施例說明本揭露之實施方式，熟習此項技藝之人士可由本文所揭示之內容輕易地瞭解本揭露之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“第一或第二”及“上”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
參閱第1圖配合第2A圖至第2D圖，其中，第1圖繪示本揭露之模封件之第一實施例之俯視示意圖，第2A圖至第2D圖繪示本揭露之模封件之第一實施例之製作流程示意圖。於本實施例中，模封件主要包括基板1、半導體元件3、模封材料4及翹曲抑制結構5。
基板1具有第一表面11。半導體元件3，例如晶片，藉由導電元件2設置於基板1的第一表面11上，半導體元件3與基板1之間填充有底部填充膠(underfill)(未標號)。模封材料4形成於基板1的第一表面11上以包覆半導體元件3。
翹曲抑制結構5係於模封材料4內的邊緣，且大致呈環狀。翹曲抑制結構5由較矽或較模封材料4為硬之材料組成，例如玻 璃纖維、碳纖維或添加有大量矽填充物的材料等等。
接著，以第2A至2D圖說明第1圖之第一實施例之模封件的製法。如第2A圖所示，將半導體元件3設置於基板1的第一表面11上，其中，半導體元件3透過導電元件2與基板1電性連接，且半導體元件3和基板1之間填充有底部填充膠(未標號)，而半導體元件3具有貫穿電極(Through-Silicon Via；TSV)31。需說明的是，此圖僅示意而非限制半導體元件3的數量。如第2B圖所示，提供一內置有翹曲抑制結構5之模封材料4，而翹曲抑制結構5位於模封材料4內的邊緣且大致呈環狀。如第2C圖所示，將內置有翹曲抑制結構5之模封材料4壓合於基板1上以包覆半導體元件3，則翹曲抑制結構5位於半導體元件3的周圍。如第2D圖所示，最後研磨模封材料4以使貫穿電極31外露。
藉此，於本實施例中，本揭露之模封件由於在模封材料4內置有翹曲抑制結構5，故可避免模封件之翹曲。
參閱第3圖配合第4A圖至第4D圖，其中，第3圖繪示本揭露之模封件之第二實施例之俯視示意圖，第4A圖至第4D圖繪示本揭露之模封件之第二實施例之製作流程示意圖。
本實施例與第一實施例之差異在於，翹曲抑制結構5具有位於模封材料4的邊緣之第一環狀部51、位於模封材料4的中央之第二環狀部52以及連接第一環狀部51與第二環狀部52之連接部53。如第3圖所示，模封件包括但不限於複數個半導體元件3，翹曲抑制結構5之第二環狀部52位於模封材料4的中央以圍繞於位於中央的半導體元件3，而其第一環狀部51位於模封材料4的邊緣以圍繞全部的半導體元件3，且第一環狀部51和第二環狀部 52又以連接部53相互連接，使得模封材料4於其中央及邊緣皆有支撐，故可避免模封件的翹曲。此外，同樣地，翹曲抑制結構5可由較矽或較模封材料4為硬之材料組成，例如玻璃纖維、碳纖維或添加有大量矽填充物材料等等。
第4A圖至第4D圖所示之製法基本上與第2A圖至第2D圖相似，其差異僅在於翹曲抑制結構的樣貌，故在此不予以贅述。
參閱第5A、5B及5C圖，其中，第5A圖繪示本揭露之模封件之第三實施例之俯視示意圖，第5B圖繪示本揭露之模封材料之剖視示意圖，第5C圖繪示本揭露之模封件之第三實施例之剖視示意圖。
本實施例與第一實施例之差異在於，如第5A和5B圖所示，翹曲抑制結構5包含位於模封材料4的邊緣之第一環狀部51、位於第一環狀部51的內側之格柵54以及連接第一環狀部51與格柵54之連接部53，而半導體元件3的數量為複數個且呈陣列排列，格柵54係圍繞該些半導體元件3且介於該些半導體元件3之間。藉此，於本實施例中，每一半導體元件3的周圍及全部半導體元件3的外圍皆環繞有翹曲抑制結構，故可避免模封件的翹曲。
第6圖繪示本揭露之模封件之第四實施例之剖視示意圖。於本實施例中，模封件主要包括基板1、半導體元件3、模封材料4及翹曲抑制結構5。
基板1具有第一表面11。導電元件2設置於基板1的第一表面11上。半導體元件3，例如晶片，藉由導電元件2設置於基板1的第一表面11之上。
模封材料4形成於基板1的第一表面11上並包覆半導體元件 3，模封材料4包含平行堆疊之第二材料層41及第一材料層42，且第一材料層42填充於半導體元件3與基板1之間以包覆導電元件2，如第6圖所示，翹曲抑制結構5位於模封材料4之第二材料層41與第一材料層42內。第二材料層41與第一材料層42之材料為相同或相異，於材料相異時，第二材料層41中的粒子尺寸大於第一材料層42中的粒子尺寸，且第一材料層42可由與基板1性質相似之材料組成。於材料相同時，可分次或同時形成，分次形成，例如，先於半導體元件3與基板1之間填充第二材料層41以包覆導電元件2，再以利用第二材料層41組成之模封材料4包覆半導體元件3；同時形成例如，直接以第二材料層41組成之模封材料4壓合於基板1上以包覆半導體元件3和導電元件2。
翹曲抑制結構5係於模封材料4內的邊緣，且大致呈環狀。翹曲抑制結構5係由較矽或較模封材料4為硬之材料組成，例如玻璃纖維、碳纖維或添加有大量矽填充物材料等等。另外，於本實施例中，翹曲抑制結構5可為如第1圖所示呈環狀，或如第3圖所示包含位於模封材料4的邊緣之第一環狀部51、位於模封材料4的中央之第二環狀部52以及連接第一環狀部51與第二環狀部52之連接部53，或如第5圖所示包含位於模封材料4的邊緣之第一環狀部51、位於第一環狀部51的內側之格柵54以及連接第一環狀部51與格柵54之連接部53。
藉此，模封材料4的第一材料層42可替代底部填充膠，直接將包含第二材料層41和第一材料層42之模封材料4壓合於基板1上，使材料層41包覆半導體元件3而使第一材料層42填充於半導體元件3與基板1之間以包覆導電元件2。因此，本實施例可 於製程時免去點膠的步驟。
另外，第7A至7E圖說明本揭露之模封組件之製作流程示意圖。
如第7A圖所示，基板1之第一表面11上設置有複數個具有貫穿電極631之第一半導體元件63，第一半導體元件63與基板1之間以第一導電元件62相互電性連接，第一模封材料64形成於基板1之第一表面11上以包覆第一半導體元件63與第一導電元件62，第一翹曲抑制結構65設置於第一模封材料64中，且複數個第一半導體元件63之周圍皆有第一翹曲抑制結構65。例如，基板1可為矽基板、有機基板或中介板。又，第一模封材料64及其中之第一翹曲抑制結構65基本上與第5A和5B圖所示之模封材料4及其中之翹曲抑制結構5相同。
如第7B圖所示，於第一半導體元件63、第一模封材料64及第一翹曲抑制結構65上形成第一保護層66，此時，第一半導體元件63、第一模封材料64、第一翹曲抑制結構65和第一保護層66形成第一模封件6。接著，於第一保護層66對應第一半導體元件63之貫穿電極631之處形成開口(未標號)，再於該開口中形成連接貫穿電極631之第二導電元件72。此外，因應第一導電元件62位置分布不同的需求，貫穿電極631上可經過線路重佈(RDL)而更改其開口以及第一導電元件62位置。
接著，如第7C和7D圖所示，於第一模封件6上形成第二模封件7。
如第7C圖所示，於第一模封件6上設置複數個具有貫穿電極731的第二半導體元件73以利用第二導電元件72與第一模封件6 電性連接。接著，將其中設置有第二翹曲抑制結構75之第二模封材料74壓合於第一保護層66上，以包覆第二半導體元件73及第二導電元件72，又，第二模封材料74及其中之第二翹曲抑制結構75基本上與第5A和5B圖所示之模封材料4及其中之翹曲抑制結構5相同，使得當第二模封材料74壓合於第一模封件6上時，各個第二半導體元件73的周圍皆有第二翹曲抑制結構75。接著，如第7D圖所示，再於第二半導體元件73、第二模封材料74和第二翹曲抑制結構75形成第二保護層76。此外，因應第二導電元件72位置分布不同的需求，貫穿電極731上可經過線路重佈(RDL)而更改其開口以及第二導電元件72位置。
最後，對第7D圖所示之結構執行切割，以完成第7E圖所示之模封組件，藉此，完成本揭露之包括基板1、第一模封件6和第二模封件7之模封組件。另外，於基板1中形成貫穿電極13以及於基板1之第二表面12形成電性連接貫穿電極13之第四導電元件8。
另外，如第7D’圖所示，於第二保護層76上再形成以第三導電元件92與第二模封件7電性連接之第三模封件9，最後，對第7D’圖所示之結構執行切割，以完成第7E’圖所示之模封組件，藉此，完成本揭露之包括基板1、第一模封件6、第二模封件7和第三模封件9之模封組件。
由第7A至7E和7D’和7E’圖可知，本揭露可於第二模封件7上垂直堆疊複數個模封件。需說明的是，第7D’圖僅為示意，若本揭露之模封組件僅包括基板1、第一模封件6、第二模封件7和第三模封件9，則位於最外層之第三半導體元件93並不需具有 貫穿電極，且其中設置有第三翹曲抑制結構95之第三模封材料94上亦不需再形成第三保護層。另一方面，於第二模封件7上堆疊有多層彼此電性連接之模封件時，這些模封件的結構與第一模封件6和第二模封件7相同，僅最外層之模封件無具有保護層及模封件中的半導體元件無具有貫穿電極。
再者，第7A至7E和7D’和7E’圖中之第一模封材料64、第二模封材料74或第三模封材料94皆可同第6圖所示之模封材料4般包含平行堆疊之二材料層，例如，第一模封材料64包含第一材料層42填充於第一半導體元件63與基板1之間，以及第二材料41層覆蓋第一半導體元件63與第一材料層42；第二模封材料74包含第三材料層(未繪示)填充於第二半導體元件73與第一模封件6之間，以及第四材料層覆蓋第二半導體元件73與該第三材料層。
綜上所述，本揭露之模封組件包含基板及堆疊於其上之至少一模封件，各模封件具有半導體元件、位於半導體元件周圍之翹曲抑制結構、包覆半導體元件及翹曲抑制結構之模封材料、及位於半導體元件、模封材料和翹曲抑制結構上之保護層。此外，本揭露主要在壓合於基板上之模封材料中設計一翹曲抑制結構，其含有位於模封材料內的邊緣的第一環狀部、位於第一環狀部內側之格柵及連接第一環狀部與格柵之連接部，藉此，翹曲抑制結構可提供模封材料支撐力，可於模封程序時抑制基板(晶圓)的翹曲，更有益於後續的薄化作業。另外，本揭露之模封材料可包含平行堆疊之二材料層，其中一材料層可代替底部填充膠而充填於半導體元件(晶片)與基板(晶圓)之間，故可免於點膠的步驟而達到 製程加速之功效。
上述該些實施樣態僅例示性說明本揭露之功效，而非用於限制本揭露，任何熟習此項技藝之人士均可在不違背本揭露之精神及範疇下，對上述該些實施態樣進行修飾與改變。此外，在上述該些實施態樣中之結構的數量僅為例示性說明，亦非用於限制本揭露。因此本揭露之權利保護範圍，應如後述之申請專利範圍所列。
1‧‧‧基板
11‧‧‧第一表面
12‧‧‧第二表面
13、631、731‧‧‧貫穿電極
6‧‧‧第一模封件
62‧‧‧第一導電元件
63‧‧‧第一半導體元件
64‧‧‧第一模封材料
65‧‧‧第一翹曲抑制結構
66‧‧‧第一保護層
7‧‧‧第二模封件
72‧‧‧第二導電元件
73‧‧‧第二半導體元件
74‧‧‧第二模封材料
75‧‧‧第二翹曲抑制結構
76‧‧‧第二保護層
8‧‧‧另一導電元件
9‧‧‧第三模封件
95‧‧‧第三翹曲抑制結構

Claims (12)

  1. 一種模封組件，包含：基板，具有相對之第一表面及第二表面；第一模封件，位於該基板之該第一表面上，該第一模封件包含：第一導電元件，位於該基板之該第一表面上；第一半導體元件，包含與該第一導電元件電性接觸之貫穿電極，並藉由該第一導電元件與該基板電性連接；第一翹曲抑制結構，位於該第一半導體元件之周圍；第一模封材料，位於該基板之該第一表面上，用於包覆該第一半導體元件、該第一導電元件、以及該第一翹曲抑制結構；以及第一保護層，位於該第一半導體元件、該第一模封材料及該第一翹曲抑制結構上；以及第二模封件，位於該第一模封件上，包括：第二導電元件，位於該第一半導體元件上；第二半導體元件，包含與該第二導電元件電性接觸之貫穿電極，並藉由該第二導電元件與該第一半導體元件電性連接；第二翹曲抑制結構，位於該第二半導體元件之周圍；第二模封材料，位於該第一模封件之該第一保護層上，用於包覆該第二半導體元件、該第二導電元件、以及該第二翹曲抑制結構；以及第二保護層，位於該第二半導體元件、該第二模封材 料及該第二翹曲抑制結構上。
  2. 如申請專利範圍第1項所述之模封組件，更包含位於該第二模封件上之第三模封件，包含：第三導電元件，位於該第二半導體元件上；第三半導體元件，藉由該第三導電元件與該第二半導體元件電性連接；第三翹曲抑制結構，位於該第三半導體元件之周圍；以及第三模封材料，位於該第二模封件之該第二保護層上，用於包覆該第三半導體元件、該第三導電元件、以及該第三翹曲抑制結構。
  3. 如申請專利範圍第2項所述之模封組件，更包含位於該基板之該第二表面之第四導電元件，其中，該基板包含貫穿電極以與該第四導電元件電性連接。
  4. 如申請專利範圍第2項所述之模封組件，更包括第三保護層，其位於該第三半導體元件、該第三模封材料及該第三翹曲抑制結構上。
  5. 如申請專利範圍第1項所述之模封組件，其中該第一翹曲抑制結構與該第二翹曲抑制結構的材料硬度大於矽。
  6. 如申請專利範圍第1項所述之模封組件，其中該第一翹曲抑制結構及該第二翹曲抑制結構的材料為玻璃纖維或添加有矽填充物之材料。
  7. 如申請專利範圍第1項所述之模封組件，其中該基板為矽基板、有機基板、中介板、或有貫穿電極之基板。
  8. 如申請專利範圍第1項所述之模封組件，其中該第一模封材料 包含第一材料層填充於該第一半導體元件與該基板之間，以及第二材料層覆蓋該第一半導體元件與該第一材料層；其中該第二模封材料包含第三材料層填充於該第二半導體元件與該第一模封件之間，以及第四材料層覆蓋該第二半導體元件與該第三材料層。
  9. 一種模封材料，包含：本體；以及翹曲抑制結構，包含：環狀部，位於該本體內的邊緣；格柵，位於該環狀部的內側；以及連接部，連接該環狀部與該格柵；其中該翹曲抑制結構用於防止該模封材料於模封程序時之翹曲。
  10. 如申請專利範圍第9項所述之模封材料，其中該模封材料包含第一材料層與第二材料層。
  11. 如申請專利範圍第10項所述之模封材料，其中該第一材料層中的粒子尺寸係小於該第二材料層的粒子尺寸。
  12. 如申請專利範圍第9項所述之模封材料，其中該翹曲抑制結構的材料硬度大於矽。
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