TWI414027B - 晶片尺寸封裝件及其製法 - Google Patents

晶片尺寸封裝件及其製法 Download PDF

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TWI414027B
TWI414027B TW099121402A TW99121402A TWI414027B TW I414027 B TWI414027 B TW I414027B TW 099121402 A TW099121402 A TW 099121402A TW 99121402 A TW99121402 A TW 99121402A TW I414027 B TWI414027 B TW I414027B
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wafer
layer
cladding layer
size package
active surface
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張江城
柯俊吉
黃建屏
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矽品精密工業股份有限公司
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    • H01L2224/10Bump connectors; Manufacturing methods related thereto
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    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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Description

晶片尺寸封裝件及其製法
本發明係有關於一種半導體封裝件及其製法,尤指一種晶片尺寸封裝件及其製法。
隨著半導體技術的演進,半導體產品已開發出不同封裝產品型態,而為追求半導體封裝件之輕薄短小,因而發展出一種晶片尺寸封裝件(chip scale package,CSP),其特徵在於此種晶片尺寸封裝件僅具有與晶片尺寸相等或略大的尺寸。
美國專利第5,892,179、6,103,552、6,287,893、6,350,668及6,433,427號案即揭露一種傳統之CSP結構,係直接於晶片上形成增層而無需使用如基板或導線架等晶片承載件,且利用重佈線(redistribution layer,RDL)技術重配晶片上的銲墊至所欲位置。
然而上述CSP結構之缺點在於重佈線技術之施用或佈設於晶片上的導電跡線往往受限於晶片之尺寸或其作用面之面積大小,尤其當晶片之積集度提昇且晶片尺寸日趨縮小的情況下,晶片甚至無法提供足夠表面以安置更多數量的銲球來與外界電性連接。
鑑此,美國專利第6,271,469號案揭露一種晶圓級晶片尺寸封裝件WLCSP(Wafer Level CSP)之製法,係於晶片上形成增層的封裝件,得提供較為充足的表面區域以承載較多的輸入/輸出端或銲球。
如第1A圖所示,準備一膠膜11,並將複數晶片12以作用面121黏貼於該膠膜11上,該膠膜11例如為熱感應膠膜;如第1B圖所示,進行封裝模壓製程,利用一如環氧樹脂之封裝膠體13包覆住晶片12之非作用面122及側面,再加熱移除該膠膜11,以外露出該晶片作用面121;如第1C圖所示,然後利用重佈線(RDL)技術,敷設一介電層14於晶片之作用面121及封裝膠體13的表面上,並開設複數貫穿介電層14之開口以露出晶片上的銲墊120,接著於該介電層14上形成線路層15,並使線路層15電性連接至銲墊120,再於線路層15上敷設拒銲層16及線路層預定位置植設銲球17,之後進行切割作業。
透過前述製程,因包覆晶片之封裝膠體的表面得提供較晶片作用面大之表面區域而能安置較多銲球以有效達成與外界之電性連接。
然而,上揭製程之缺點在於將晶片以作用面黏貼於膠膜上而固定之方式,常因膠膜於製程中受熱而發生伸縮問題,造成黏置於膠膜上之晶片位置發生偏移,甚至於封裝模壓時因膠膜受熱軟化而造成晶片位移,如此導致後續在重佈線製程時,線路層無法連接到晶片銲墊上而造成電性不良。再者,此製程中所使用膠膜為消耗性材料,造成製程成本之增加。
另外,請參閱第2圖,於前述封裝模壓時,因膠膜11遇熱軟化,封裝膠體13易發生溢膠130至晶片作用面121,甚或污染銲墊120,造成後續重佈線製程之線路層與晶片銲墊接觸不良,而導致廢品問題。
再者,請參閱第3A圖,前述封裝模壓製程僅透過膠膜11支撐複數晶片12,該膠膜11及封裝膠體13易發生嚴重翹曲(warpage)110問題,尤其是當封裝膠體13之厚度很薄時,翹曲問題更為嚴重,從而導致後續重佈線製程時,在晶片上塗佈介電層時會有厚度不均問題;如此即須額外再提供一硬質載具18(如第3B圖所示),以將封裝膠體13透過一黏膠19固定在該硬質載具18來進行整平;如此不僅造成製程複雜,且增加許多製程成本,同時在完成重佈線製程而移除該載具時,易發生在封裝膠體上會有先前固定在載具上之黏膠殘留190問題(如第3C圖所示)。其它相關習知技術的揭露如美國專利第6,498,387、6,586,822、7,019,406及7,238,602號。
因此,如何提供一種晶片尺寸封裝件及製法,俾能確保線路層與銲墊間之電性連接品質,並提昇產品的可靠度,減少製程成本,實為一重要課題。
有鑑於上述習知技術之缺點,本發明提供一種晶片尺寸封裝件之製法,係包括:提供複數具相對作用面及非作用面之晶片及一載具,該晶片作用面上設有複數銲墊,於該晶片作用面上覆蓋有保護層及於該載具表面設有第一包覆層,以將該晶片透過其非作用面而固定於該第一包覆層上;以第二包覆層包覆該晶片並外露出該晶片作用面上之保護層;移除該保護層以外露出該晶片作用面;於該晶片作用面及第二包覆層上設置介電層,並使該介電層形成開口以外露出該銲墊;於該介電層上形成線路層,並使該線路層電性連接至該銲墊;以及於該介電層及線路層上設置拒銲層,並使該拒銲層形成複數開口以植設銲球。後續即可移除該載具,並進行切割作業以形成複數晶圓級晶片尺寸封裝件(WLCSP)。
為薄化封裝件及提升晶片散熱效果復可移除該第一包覆層。另可利用重佈線技術於該線路層上形成線路增層(build-up)結構。本發明之晶片尺寸封裝件的製法中,因該第二包覆層與第一包覆層之附著力大於第一包覆層與載具之附著力,而可輕易在後段製程中移除該載具,藉此加速製程效率,重複利用該載具,進而節省製程成本。
透過前述製法,本發明復揭示一種晶片尺寸封裝件,係包括:晶片,該晶片具有相對之作用面及非作用面,且於該晶片作用面設有複數銲墊;第二包覆層,係包覆於該晶片周圍,且該第二包覆層之高度大於該晶片之高度;介電層,設於該晶片作用面及第二包覆層上,且該介電層具複數開口以外露該銲墊;以及線路層,設於該介電層上且電性連接至該銲墊。
該封裝件複包括有:拒銲層,設於該介電層及線路層上,該拒銲層具有複數開口以外露出線路層預定部分;以及銲球,設於該線路層預定部分上。
另外,該封裝件復可在該晶片非作用面及第二包覆層上設第一包覆層。
因此,本發明之晶片尺寸封裝件及製法主要在晶片作用面上設一保護層,並使晶片以非作用面固定於硬質載具上,接著進行封裝模壓製程及移除該保護層,接著再進行重佈線製程,藉以避免習知將晶片作用面直接黏置於膠膜上發生膠膜受熱軟化、封裝膠體溢膠及晶片偏移與污染問題,甚或造成後續重佈線製程之線路層與晶片銲墊接觸不良,導致廢品問題,且本發明中該載具於製程中因第二包覆層與第一包覆層之附著力大於第一包覆層與載具之附著力,而可輕易移除及重覆使用,以節省製程成本,同時本發明毋須使用膠膜,故可避免習知製程中使用膠膜而發生翹曲問題,而為解決該翹曲問題又須額外提供載具所導致製程複雜、成本增加及封裝膠體有殘膠等問題。
以下係藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點與功效。
請參閱第4A至4H圖,係為本發明之晶片尺寸封裝件及其製法第一實施例之示意圖。
如第4A及4B圖所示,提供一具複數晶片22之晶圓22A,該晶圓22A及晶片22具有相對之作用面221及非作用面222,且該晶片作用面221設有複數銲墊220,並於該晶圓作用面221上敷設一厚約3至20微米之保護層21,接著進行晶圓22A切割,以形成複數作用面221上設有保護層21之晶片22。
如第4C圖所示,另提供一硬質載具23,且於載具23上塗佈第一包覆層230,俾將前述作用面221上設有保護層21之複數晶片22以其非作用222透過黏膠24而黏置於該第一包覆層230上,並進行烘烤(cure)固定。該第一包覆層230例如為油墨之環氧樹脂。
如第4D圖所示,以如模壓方式使如環氧樹脂封裝材料之第二包覆層25包覆該晶片22並外露出該晶片作用面221上之保護層21。該第二包覆層25例如為環氧樹脂之封裝材料,其中該載具23、第一包覆層230及第二包覆層25之材料選擇須使該第二包覆層25與第一包覆層230之附著力大於第一包覆層230與載具23之附著力,以方便後續移除該載具23。
如第4E圖所示,以如化學藥劑之方式移除該保護層以外露出晶片作用面221。如此該第二包覆層25之高度即大於該晶片作用面221之高度。
如第4F圖所示,於晶片作用面221及第二包覆層25上設置介電層26,並利用例如黃光(photo-lithography)製程或雷射製程,使該介電層形成有複數開口以外露出該銲墊220。該介電層26係用以供後續之線路層附著其上之種子層(seed layer)。
接著,利用重佈線(RDL)技術於該介電層26上形成線路層27,並使該線路層27電性連接至該銲墊220。
如第4G圖所示,於該介電層26及線路層27上設置拒銲層28,並使該拒銲層28形成複數開口以外露出該線路層27預定部分,俾供植設銲球29於該線路層預定部分。
如第4H圖所示,之後因該第二包覆層25與第一包覆層230之附著力大於第一包覆層230與載具23之附著力,即可輕易移除該載具23,再進行切割作業,以形成複數晶圓級晶片尺寸封裝件(WLCSP)。
透過前述製法,本發明復揭示一種晶片尺寸封裝件,係包括:晶片22,該晶片22具有相對之作用面221及非作用面222,且於該晶片作用面221設有複數銲墊220;第二包覆層25,係包覆於該晶片22周圍,該第二包覆層25之高度大於該晶片22之高度;介電層26,設於該晶片22作用面及第二包覆層25上,且該介電層26具複數開口以外露該銲墊220;線路層27,設於該介電層26上且電性連接至該銲墊220;拒銲層28,設於該介電層26及線路層27上,該拒銲層28具有複數開口以外露出線路層27預定部分;銲球29,設於該線路層27預定部分上。另外,該封裝件在該晶片非作用面222及第二包覆層25上設第一包覆層230。
因此,本發明之晶片尺寸封裝件及製法主要在晶片作用面上設一保護層,並使晶片以非作用面固定於硬質載具上,接著進行封裝模壓製程及移除該保護層,接著再進行重佈線製程,藉以避免習知將晶片作用面直接黏置於膠膜上發生膠膜受熱軟化、封裝膠體溢膠及晶片偏移與污染問題,甚或造成後續重佈線製程之線路層與晶片銲墊接觸不良,導致廢品問題,且本發明中該載具於製程中因第二包覆層與第一包覆層之附著力大於第一包覆層與載具之附著力,而可輕易移除及重覆使用,以節省製程成本,同時本發明毋須使用膠膜,故可避免習知製程中使用膠膜而發生翹曲問題,而為解決該翹曲問題又須額外提供載具所導致製程複雜、成本增加及封裝膠體有殘膠等問題。
請參閱第5圖,係顯示本發明之晶片尺寸封裝件及其製法第二實施例之剖面示意圖。如圖所示,該晶片尺寸封裝件與前述實施例所揭露者大致相同,其不同處在於後續為薄化封裝件復可移除第一包覆層,同時有助於散逸晶片32運作所產生之熱量至外界,增進封裝件之散熱效率。
復請參閱第6圖,係顯示本發明之晶片尺寸封裝件及其製法第三實施例之剖面示意圖。如圖所示,該晶片尺寸封裝件與前述實施例所揭露者大致相同,其不同處在於可利用重佈線技術繼續於先前所形成之介電層及線路層上形成增層結構,例如在先前所形成之介電層26及線路層27上形成第二介電層26a及第二線路層27a,並使該第二線路層27a電性連接至該第一線路層27,然後,再於第二線路層27a上敷設拒銲層28,並開設複數貫穿拒銲層28之開口,以外露出第二線路層27a之預定部分,接著於第二線路層27a之預定部分上植設銲球29,以作為封裝件之輸入/輸出端,供與外界裝置作電性連接。如此得藉由增加晶片上之增層數目而能提昇封裝件中線路佈設的彈性。
請參閱第7A至7D圖,係顯示本發明之晶片尺寸封裝件及其製法第四實施例之剖面示意圖。如圖所示,本實施例與前述實施例所揭露者大致相同,主要差異係可在晶片非作用面上增設一強化防護層以保護晶片。
如第7A圖所示,提供一硬質載具33,且於載具33上塗佈第一包覆層330,再於該第一包覆層330上以如模壓方式形成如環氧樹脂封裝材料(EMC,Epoxy Molding Compound)之強化防護層333,其中該強化防護層333與第一包覆層330之附著力大於該第一包覆層330與載具33之附著力。
如第7B圖所示,將作用面上設有保護層31之晶片32以其非作用面透過黏膠34而黏置於該強化防護層333上。
如第7C圖所示,以如模壓方式使如環氧樹脂封裝材料之第二包覆層35包覆該晶片32並外露出該晶片作用面上之保護層31;接著移除該保護層31以外露出該晶片作用面,再於該晶片作用面及第二包覆層35上設置介電層36,及於該介電層36上形成線路層37。
而後於該介電層36及線路層37上設置拒銲層38,並植設銲球39。
如第7D圖所示,之後即可移除該載具33,並進行切割作業。
如此該晶片32之非作用面上即設有一強化防護層333,以提供晶片更佳保護。
上述實施例僅為例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修飾與變化。因此,本發明之權利保護範圍,應如後述之申請專利範圍所列。
11...膠膜
12...晶片
13...封裝膠體
14...介電層
15...線路層
16...拒銲層
17...銲球
18...載具
19...黏膠
21...保護層
22‧‧‧晶片
22A‧‧‧晶圓
23‧‧‧載具
24‧‧‧黏膠
25‧‧‧第二包覆層
26‧‧‧介電層
26a‧‧‧第二介電層
27‧‧‧線路層
27a‧‧‧第二線路層
28‧‧‧拒銲層
29‧‧‧銲球
31‧‧‧保護層
32‧‧‧晶片
33‧‧‧載具
34‧‧‧黏膠
35‧‧‧第二包覆層
36‧‧‧介電層
37‧‧‧線路層
38‧‧‧拒銲層
39‧‧‧銲球
110‧‧‧翹曲
120‧‧‧銲墊
121‧‧‧作用面
122‧‧‧非作用面
130‧‧‧溢膠
190‧‧‧黏膠殘留
220‧‧‧銲墊
221‧‧‧作用面
222‧‧‧非作用面
230‧‧‧第一包覆層
330‧‧‧第一包覆層
333‧‧‧強化防護層
第1A至1C圖係為美國專利US6,271,469所揭露之晶圓級晶片尺寸封裝件之製法示意圖;
第2圖係為美國專利US6,271,469所揭示之晶圓級晶片尺寸封裝件發生溢膠問題之示意圖;
第3A至3C圖係為美國專利US6,271,469所揭示之晶圓級晶片尺寸封裝件發生封裝膠體翹曲、增設載具及封裝膠體表面殘膠問題之示意圖;
第4A至4H圖係為本發明之晶片尺寸封裝件及其製法第一實施例示意圖;
第5圖係為本發明之晶片尺寸封裝件及其製法第二實施例示意圖;以及
第6圖係為本發明之晶片尺寸封裝件及其製法第三實施例示意圖;以及
第7A至7D圖係為本發明之晶片尺寸封裝件及其製法第四實施例示意圖。
22...晶片
25...第二包覆層
26...介電層
27...線路層
28...拒銲層
29...銲球
220...銲墊
221...作用面
222...非作用面
230...第一包覆層

Claims (22)

  1. 一種晶片尺寸封裝件之製法,係包括:提供複數具相對作用面及非作用面之晶片及一載具,該晶片作用面上設有複數銲墊;令保護層完全覆蓋住該晶片作用面;第一包覆層敷設於該載具表面上;將晶片透過其非作用面而固定於該第一包覆層上;以第二包覆層包覆該晶片並外露出該晶片作用面上之保護層;移除該保護層以外露出該晶片作用面;於該晶片作用面及第二包覆層上形成介電層,並使該介電層形成開口以外露出該銲墊;以及於該介電層上形成線路層,並使該線路層電性連接至該銲墊。
  2. 如申請專利範圍第1項所述之晶片尺寸封裝件之製法,復包括:於該介電層及線路層上設置拒銲層,並使該拒銲層形成複數開口以植設銲球。
  3. 如申請專利範圍第2項所述之晶片尺寸封裝件之製法,復包括:移除該載具,並進行切割作業。
  4. 如申請專利範圍第1項所述之晶片尺寸封裝件之製法,其中,該第二包覆層與第一包覆層之附著力大於第一包覆層與載具之附著力。
  5. 如申請專利範圍第1項所述之晶片尺寸封裝件之製法,其中,該第二包覆層之高度大於該晶片之高度。
  6. 如申請專利範圍第3項所述之晶片尺寸封裝件之製法, 復包括:移除該第一包覆層。
  7. 如申請專利範圍第1項所述之晶片尺寸封裝件之製法,復包括:以重佈線技術於該介電層及線路層上形成增層結構。
  8. 如申請專利範圍第1項所述之晶片尺寸封裝件之製法,其中,該晶片及載具之製程,係包括:提供一具複數晶片之晶圓,該晶圓及晶片具有相對之作用面及非作用面,以於該晶圓作用面上敷設保護層,接著進行晶圓切割,以形成複數作用面上設有保護層之晶片,以將該晶片透過其非作用面而固定於載具之第一包覆層上。
  9. 如申請專利範圍第1項所述之晶片尺寸封裝件之製法,其中,該第一包覆層上復形成有強化防護層,以供該晶片接置於該強化防護層上。
  10. 如申請專利範圍第9項所述之晶片尺寸封裝件之製法,其中,該強化防護層係藉由模壓方式形成。
  11. 如申請專利範圍第10項所述之晶片尺寸封裝件之製法,其中,該強化防護層係環氧樹脂材料。
  12. 如申請專利範圍第9項所述之晶片尺寸封裝件之製法,其中,該強化防護層與第一包覆層之附著力大於該第一包覆層與載具之附著力。
  13. 如申請專利範圍第1項所述之晶片尺寸封裝件之製法,其中,該第二包覆層係藉由模壓方式使封裝材料包覆該晶片。
  14. 如申請專利範圍第1項所述之晶片尺寸封裝件之製法, 其中,該第一包覆層係含環氧樹脂的油墨。
  15. 一種晶片尺寸封裝件,係包括:晶片,該晶片具有相對之作用面及非作用面,且於該晶片作用面設有複數銲墊;第二包覆層,係包覆於該晶片周圍,該第二包覆層之高度大於該晶片之高度;介電層,一體形成於該晶片作用面及第二包覆層上,且該介電層具複數開口以外露該銲墊;以及線路層,設於該介電層上且電性連接至該銲墊。
  16. 如申請專利範圍第15項所述之晶片尺寸封裝件,復包括:拒銲層,設於該介電層及線路層上,該拒銲層具有複數開口以外露出線路層預定部分;以及銲球,設於該線路層預定部分上。
  17. 如申請專利範圍第15項所述之晶片尺寸封裝件,復包括:第一包覆層,係設於該晶片非作用面及第二包覆層上。
  18. 如申請專利範圍第15項所述之晶片尺寸封裝件,復包括:強化防護層,係設於該晶片非作用面及第二包覆層上。
  19. 如申請專利範圍第18項所述之晶片尺寸封裝件,其中,該強化防護層係環氧樹脂材料。
  20. 如申請專利範圍第15項所述之晶片尺寸封裝件,復包括增層結構,係形成於該介電層及線路層上。
  21. 如申請專利範圍第15項所述之晶片尺寸封裝件,其中,該第二包覆層係環氧樹脂材料。
  22. 如申請專利範圍第15項所述之晶片尺寸封裝件,其中,該第一包覆層係含環氧樹脂的油墨。
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