TWI504153B - Phase - locked loop circuit and oscillation method - Google Patents
Phase - locked loop circuit and oscillation method Download PDFInfo
- Publication number
- TWI504153B TWI504153B TW103142101A TW103142101A TWI504153B TW I504153 B TWI504153 B TW I504153B TW 103142101 A TW103142101 A TW 103142101A TW 103142101 A TW103142101 A TW 103142101A TW I504153 B TWI504153 B TW I504153B
- Authority
- TW
- Taiwan
- Prior art keywords
- pulse
- signal
- pulse width
- circuit
- pulse signal
- Prior art date
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013253699A JP5747070B2 (ja) | 2013-12-07 | 2013-12-07 | 位相同期ループ回路及び発振方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201524129A TW201524129A (zh) | 2015-06-16 |
TWI504153B true TWI504153B (zh) | 2015-10-11 |
Family
ID=53529098
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW103142101A TWI504153B (zh) | 2013-12-07 | 2014-12-04 | Phase - locked loop circuit and oscillation method |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP5747070B2 (ja) |
TW (1) | TWI504153B (ja) |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6226506B1 (en) * | 1998-05-29 | 2001-05-01 | Silicon Laboratories, Inc. | Method and apparatus for eliminating floating voltage nodes within a discreetly variable capacitance used for synthesizing high-frequency signals for wireless communications |
US7113047B2 (en) * | 2004-06-09 | 2006-09-26 | Fujitsu Limited | Clock generator and its control method |
JP2007013950A (ja) * | 2005-06-29 | 2007-01-18 | Altera Corp | 別途の比例経路を有するクロックデータリカバリループ |
JP2007060649A (ja) * | 2005-08-01 | 2007-03-08 | Marvell World Trade Ltd | 低ノイズ且つ微細な周波数調節 |
US7330081B1 (en) * | 2005-01-24 | 2008-02-12 | Marvell Semiconductor Israel Ltd. | Digitally controlled oscillator and associated method |
US20080297208A1 (en) * | 2007-02-08 | 2008-12-04 | Stmicroelectronics Sa | Process for dithering a time to digital converter and circuits for performing said process |
US20090219187A1 (en) * | 2008-03-03 | 2009-09-03 | Qualcomm Incorporated | High-speed time-to-digital converter |
WO2012165260A1 (ja) * | 2011-05-27 | 2012-12-06 | 国立大学法人東京大学 | 信号変換回路、pll回路、遅延調整回路及び位相制御回路 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5445558A (en) * | 1977-09-17 | 1979-04-10 | Citizen Watch Co Ltd | Frequency adjusting set for oscillator |
JPH01258510A (ja) * | 1988-04-08 | 1989-10-16 | Ricoh Co Ltd | Pll回路 |
JP4763918B2 (ja) * | 2000-04-20 | 2011-08-31 | テキサス インスツルメンツ インコーポレイテツド | デジタル制御発信器同調入力をタイムディザリングするシステムおよび方法 |
-
2013
- 2013-12-07 JP JP2013253699A patent/JP5747070B2/ja active Active
-
2014
- 2014-12-04 TW TW103142101A patent/TWI504153B/zh active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6226506B1 (en) * | 1998-05-29 | 2001-05-01 | Silicon Laboratories, Inc. | Method and apparatus for eliminating floating voltage nodes within a discreetly variable capacitance used for synthesizing high-frequency signals for wireless communications |
US7113047B2 (en) * | 2004-06-09 | 2006-09-26 | Fujitsu Limited | Clock generator and its control method |
US7330081B1 (en) * | 2005-01-24 | 2008-02-12 | Marvell Semiconductor Israel Ltd. | Digitally controlled oscillator and associated method |
JP2007013950A (ja) * | 2005-06-29 | 2007-01-18 | Altera Corp | 別途の比例経路を有するクロックデータリカバリループ |
JP2007060649A (ja) * | 2005-08-01 | 2007-03-08 | Marvell World Trade Ltd | 低ノイズ且つ微細な周波数調節 |
US20080297208A1 (en) * | 2007-02-08 | 2008-12-04 | Stmicroelectronics Sa | Process for dithering a time to digital converter and circuits for performing said process |
US20090219187A1 (en) * | 2008-03-03 | 2009-09-03 | Qualcomm Incorporated | High-speed time-to-digital converter |
WO2012165260A1 (ja) * | 2011-05-27 | 2012-12-06 | 国立大学法人東京大学 | 信号変換回路、pll回路、遅延調整回路及び位相制御回路 |
Also Published As
Publication number | Publication date |
---|---|
TW201524129A (zh) | 2015-06-16 |
JP2015115618A (ja) | 2015-06-22 |
JP5747070B2 (ja) | 2015-07-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4850473B2 (ja) | デジタル位相検出器 | |
US8081013B1 (en) | Digital phase and frequency detector | |
US8531322B2 (en) | Time-to-digital converter | |
US9632486B2 (en) | Masking circuit and time-to-digital converter comprising the same | |
WO2021068326A1 (zh) | 一种基于控制信号脉宽提取的锁相加速电路及锁相环*** | |
US10819355B1 (en) | Phase to digital converter | |
TWI398151B (zh) | 資料時脈回復電路 | |
KR20150129794A (ko) | 임베딩된 t2v adc를 가진 혼합된 신호 tdc | |
JP5948195B2 (ja) | クロック生成装置およびクロックデータ復元装置 | |
CN104320130A (zh) | 一种基于双环dll的三段式高精度时间数字转换方法及其电路 | |
US9768759B2 (en) | Clock generator and method of adjusting phases of multiphase clocks by the same | |
US10284211B2 (en) | Injection-locked oscillator and semiconductor device including the same | |
US10691074B2 (en) | Time-to-digital converter circuit | |
US20120049912A1 (en) | Digital phase difference detector and frequency synthesizer including the same | |
US8094769B2 (en) | Phase-locked loop system with a phase-error spreading circuit | |
KR20090010386A (ko) | 인터폴레이션을 이용한 고해상도의 시간검출장치 및 이를이용한 시간검출방법 | |
KR20110038734A (ko) | 디지털 위상 록킹 루프에서의 누산된 위상-디지털 변환 | |
Patel et al. | Phase Frequency Detector and Charge Pump For DPLL Using 0.18 µm CMOS Technology | |
JP2017130838A (ja) | クロック生成装置およびクロックデータ復元装置 | |
TWI504153B (zh) | Phase - locked loop circuit and oscillation method | |
JP2019220763A (ja) | 半導体装置 | |
KR101548256B1 (ko) | 인젝션 락킹 기반 링오실레이터의 피브이티 변화 교정을 위한 장치 및 방법 | |
JP2021034784A (ja) | 注入同期型分周器 | |
Huang et al. | A time-to-digital converter based AFC for wideband frequency synthesizer | |
KR101621382B1 (ko) | 위상 고정 루프 및 그 인젝션 락킹 방법 |