TWI485837B - 具有多晶片模組結構的高頻電路 - Google Patents
具有多晶片模組結構的高頻電路 Download PDFInfo
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- TWI485837B TWI485837B TW099116838A TW99116838A TWI485837B TW I485837 B TWI485837 B TW I485837B TW 099116838 A TW099116838 A TW 099116838A TW 99116838 A TW99116838 A TW 99116838A TW I485837 B TWI485837 B TW I485837B
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- 239000000758 substrate Substances 0.000 claims description 218
- 239000004065 semiconductor Substances 0.000 claims description 85
- 230000008054 signal transmission Effects 0.000 claims description 52
- 239000003990 capacitor Substances 0.000 claims description 46
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 7
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- 229910002704 AlGaN Inorganic materials 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 229910052594 sapphire Inorganic materials 0.000 claims description 2
- 239000010980 sapphire Substances 0.000 claims description 2
- 101150073536 FET3 gene Proteins 0.000 description 42
- 230000005540 biological transmission Effects 0.000 description 19
- 229910002601 GaN Inorganic materials 0.000 description 17
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 17
- 238000012986 modification Methods 0.000 description 16
- 230000004048 modification Effects 0.000 description 16
- 150000001875 compounds Chemical class 0.000 description 15
- 150000004767 nitrides Chemical class 0.000 description 15
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 description 13
- 101150015217 FET4 gene Proteins 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- KCFIHQSTJSCCBR-UHFFFAOYSA-N [C].[Ge] Chemical compound [C].[Ge] KCFIHQSTJSCCBR-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- -1 nitride compound Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/255—Amplifier input adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/366—Multiple MOSFETs are coupled in parallel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
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-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/423—Amplifier output adaptation especially for transmission line coupling purposes, e.g. impedance adaptation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/543—A transmission line being used as coupling element between two amplifying stages
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Description
本發明基於JP2009-192326(2009/8/21)及JP2010-48155(2010/3/4)申請案,內容亦參照彼等全部內容。
本發明關於具有多晶片模組結構的高頻電路,特別關於微波頻帶之高頻用半導體裝置中,在1個封裝內以複數段放大器來構成模組的具有多晶片模組結構的高頻電路。
由1個封裝欲獲得高增益時可於封裝內串聯連接複數段電晶體。該複數段電晶體、複數個匹配電路、複數個偏壓電路形成於1片半導體基板上的技術、亦即混成微波積體電路(MMIC:Monolithic Microwave Integrated Circuit)被廣泛使用。
於習知MMIC,係於半導體基板上將半導體元件、輸出入匹配電路、電容器、電源供給線等予以集積而成。
已有電力放大器被揭示(參照例如專利文獻1),其具備藉由介電體基板上之電路將複數個MMIC並聯連接之構成。專利文獻1揭示的電力放大器,係具備:並聯配置之複數個半導體晶片(MMIC);介電體基板上之複數個匹配電路;1組輸出入端子;及複數個直流偏壓端子。複數個半導體晶片(MMIC)與介電體基板上之複數個匹配電路被收容於1個封裝。但是,為獲得高增益而將複數段
予以連接之電力放大器,係由主動電路元件與被動電路元件構成之MMIC予以構成,因而難以小型化。
另外,專利文獻2揭示之半導體裝置,係具有:於介電體基板上,藉由覆晶接合(flip)使晶片串聯連接的覆晶裝配(flip chip mount)結構。於專利文獻2,具有覆晶裝配結構的半導體裝置,除覆晶連接以外,僅電晶體部與端子被形成於半導體基板上,電路則被形成於介電體基板上。特別是,於專利文獻2之第2實施形態(第2圖)中,複數段放大器藉由複數個介電體基板上之匹配電路被耦合。但是,耦合放大器間之電路係被形成於1片介電體基板上,因而其之一部分無法使用高介電率基板,難以小型化。
專利文獻3揭示之半導體裝置,係為達成具備電力放大器之半導體裝置之小型化,而於佈局線路上配置FET。於專利文獻3,係於佈局線路上配置FET,使相位偏離來實現寬頻帶域,另外,整合其相位而進行電力合成。專利文獻3揭示之半導體裝置,可將上述合成電路與放大電路構成之電力放大器複數個予以組合,例如可為2個電力放大器並聯連接之構成或串聯連接之構成,或3個以上之電力放大器串聯/並聯連接之構成等。於專利文獻3,僅放大器由半導體基板來構成,被動電路元件則由便宜之介電體基板構成。但是,因為使放大器於介電體基板上施予覆晶連接之故,會損及放大器之散熱性。另外,構成被動電路元件的介電體基板設為1片,無法部分使用高介電率基板
,難以小型化。
專利文獻1:特開2000-49549號公報
專利文獻2:特開2002-110737號公報
專利文獻3:特表2003-110381號公報
於MMIC,電晶體與匹配電路均被形成於1片基板上,因此介電率為固定。,因而大的電容器或長線路為必要時,電路構成之面積會變大。
和習知矽(Si)系電晶體或砷化鎵(GaAs)系電晶體比較,矽碳(SiC)系電晶體或氮化鎵(GaN)系電晶體可以獲得高的輸出電力。但是,和Si或GaAs比較,如SiC或GaN等將複數個電晶體、複數個匹配電路、複數個偏壓電路形成於1片半導體基板上之MMIC,其之材料費用變高。
本發明之一態樣提供之具有多晶片模組結構的高頻電路,係包含:半導體基板,用於形成複數個分立式電晶體(discrete transistor);第1介電體基板,用於形成電容器;及第2介電體基板,用於形成匹配電路;上述複數個分立式電晶體被串聯連接。
本發明之另一態樣提供之具有多晶片模組結構的高頻電路,係包含:同一半導體基板,用於形成被串聯連接的
複數個分立式電晶體;第1介電體基板,用於形成電容器;第2介電體基板,用於形成匹配電路;封裝基板,用於配置上述半導體基板、上述第1介電體基板、與上述第2介電體基板;及輸入端子與輸出端子,被配置於上述封裝基板之對向之邊;上述複數個分立式電晶體之閘極端子電極與汲極端子電極間之信號傳送方向,係依各段別而呈互異。
以下參照圖面說明本發明之實施形態。以下針對同一邀素附加同一符號,省略重複說明。圖面以模式表示,和實際有所差別,此應予以留意。另外,圖面相互間異包含尺寸關係或比率相互不同之部份。
以下實施形態中說明將本發明技術思想予以具體化的方法或裝置之例,但本發明之實施形態並非將各構成元件之配置等界定為以下者。本發明之實施形態在申請專利範圍內可作各種變更實施。
本發明第1實施形態之具有多晶片模組結構的高頻電路30之模式平面圖案構成,係如圖1所示,具備:用於形成複數個分立式電晶體FET1~FET3的半導體基板161
~163
;用於形成電容器C1~C4的第1介電體基板141
~144
;及用於形成匹配電路的第2介電體基板181
~182
;複數個分立
式電晶體FET1~FET3被串聯連接。
複數個分立式電晶體FET1~FET3,分別被形成於各個半導體基板161
~163
上。
半導體基板161
~163
、第1介電體基板141
~144
、及第2介電體基板181
~182
,係於1個封裝基板10上被框架構件12包圍而配置,被收容於1個封裝內。
用於搭載分立式電晶體FET1~FET3的複數個半導體基板161
~163
,可以直接裝配於封裝基板10之表面上。
另外,半導體基板161
~163
,其之電路要素可以僅包含分立式電晶體FET1~FET3,及分立式電晶體FET1~FET3之閘極端子電極G1~G3、源極端子電極S1~S3及汲極端子電極D1~D3。
第1實施形態之具有多晶片模組結構的高頻電路30之模式平面圖案構成上,複數個分立式電晶體FET1~FET3之信號傳送方向,可以配置成為各段不同。亦即,如圖1所示,分立式電晶體FET1之閘極端子電極G1至汲極端子電極D1之信號傳送方向,與分立式電晶體FET2之閘極端子電極G2至汲極端子電極D2之信號傳送方向,係呈相反方向。分立式電晶體FET2之閘極端子電極G2至汲極端子電極D2之信號傳送方向,與分立式電晶體FET3之閘極端子電極G3至汲極端子電極D3之信號傳送方向,係呈相反方向。
和圖1對應之多段放大電路之模式電路構成,係如圖2所示。於圖2表示3段之分立式電晶體FET1~FET3被串聯
呈現級聯(cascade)連接而構成多段放大器之例。
如圖1、2所示,於輸入端子Pi被連接電容器C1,於輸出端子Po被連接電容器C4。
於介由電容器C1被連接於輸入端子Pi的閘極輸入端子g1,係藉由閘極偏壓VGG
被供給閘極電壓Vgg1。
閘極輸入端子g1,係介由輸入傳送線路λ g1被連接於分立式電晶體FET1之閘極端子電極G1。
分立式電晶體FET1之汲極端子電極D1,係介由輸出傳送線路λ d1被連接於汲極輸出端子d1。
於汲極輸出端子d1,係藉由汲極偏壓VDD
被供給汲極電壓Vdd1。
於汲極輸出端子d1被連接電容器C2。
於汲極輸出端子d1介由電容器C2被連接的閘極輸入端子g2,係藉由閘極偏壓VGG
被供給閘極電壓Vgg2。
閘極輸入端子g2,係介由輸入傳送線路λ g2被連接於分立式電晶體FET2之閘極端子電極G2。
分立式電晶體FET2之汲極端子電極D2,係介由輸出傳送線路λ d2被連接於汲極輸出端子d2。
於汲極輸出端子d2,係藉由汲極偏壓VDD
被供給汲極電壓Vdd2。
於汲極輸出端子d2被連接電容器C3。
於汲極輸出端子d2介由電容器C3被連接的閘極輸入端子g3,係藉由閘極偏壓VGG
被供給閘極電壓Vgg3。
閘極輸入端子g3,係介由輸入傳送線路λ g3被連接於
分立式電晶體FET3之閘極端子電極G3。
分立式電晶體FET3之汲極端子電極D3,係介由輸出傳送線路λ d3被連接於汲極輸出端子d3。
於汲極輸出端子d3,係藉由汲極偏壓VDD
被供給汲極電壓Vdd3。
於汲極輸出端子d3被連接電容器C4,電容器C4被連接於輸出端子Po。
於此,複數個分立式電晶體FET1~FET3之中,相對於最終段使用之分立式電晶體FET3之閘極寬,使其前段使用之分立式電晶體FET2之閘極寬構成為較窄,如此而構成級聯連接之多段放大器亦可。
另外,複數個分立式電晶體FET1~FET3之中,相對於第2段使用之分立式電晶體FET2之閘極寬,使第1段使用之分立式電晶體FET1之閘極寬構成為較窄,如此而構成級聯連接之多段放大器亦可。
又,第1實施形態之具有多晶片模組結構的高頻電路30所使用的複數個分立式電晶體FET1~FET3,例如可以適用場效電晶體(FET:Field Effect Transistor)、高電子移動度電晶體(HEMT:High Electron Mobility Transistor)等。
沿圖1之I-I線之模式斷面結構,係如圖3所示,具備:封裝基板10;配置於封裝基板10上的絕緣層20;配置於絕緣層20上的輸入帶狀線221
;配置於封裝基板10上的第1介電體基板141
、142
;及配置於封裝基板10上的半導體基
板161
。
於第1介電體基板141
、142
分別配置電容器C1、C2,於半導體基板161
配置分立式電晶體FET1。
藉由調整第1介電體基板141
之厚度t亦可以第1介電體基板141
作為電容器形成用基板使用。因為變化第1介電體基板141
之厚度t可以變化電容器值。同樣,變化第1介電體基板141
之介電率可以變化電容器值。
沿圖1之II-II線之模式斷面結構圖,係如圖4所示,具備:封裝基板10;配置於封裝基板10上的絕緣層20;配置於絕緣層20上的輸出帶狀線222
;配置於封裝基板10上的第1介電體基板143
、144
;配置於封裝基板10上的半導體基板163
;及配置於封裝基板10上的第2介電體基板181
、182
。
於第1介電體基板143
、144
分別配置電容器C3、C4,於半導體基板163
配置分立式電晶體FET3。
於第2介電體基板181
、182
分別配置輸入匹配電路、輸出匹配電路。
如圖4所示,可以適當變更第1介電體基板143
、144
及第2介電體基板181
、182
之厚度。另外,變化介電率可以調整電容器值,可以調整配置之傳送線路之特性阻抗。同樣,可以大幅縮短電容器面積、所配置之引線(stub)長度。
第1實施形態之具有多晶片模組結構的高頻電路之中,適用之分立式電晶體FET3之一部分被擴大的模式平面圖案構成,係如圖5A所示,圖5A之J部分之擴大圖,係如圖5B所示。另外,第1實施形態之具有多晶片模組結構的高頻電路所適用之分立式電晶體之構成例1~4,沿圖5B之III-III線之模式斷面構成例1~4,係分別如圖6~9所示。另外,分立式電晶體FET1~FET2之斷面結構,亦和分立式電晶體FET3為同樣構成。
第1實施形態之具有多晶片模組結構的高頻電路之中,分立式電晶體FET3,係如圖5及圖6~9所示具備:半絕緣性基板110;閘極指部電極124、源極指部電極120及汲極指部電極122,配置於半絕緣性基板110之第1表面,分別具有複數個指部;複數個閘極端子電極G3、複數個源極端子電極S3及複數個汲極端子電極D3,配置於半絕緣性基板110之第1表面,依閘極指部電極124、源極指部電極120及汲極指部電極122類別將複數個指部分別捆綁而形成;VIA導孔SC3,配置於源極端子電極S3下部;及背面接地電極(未圖示),配置於半絕緣性基板110之第1表面相反側的第2表面,介由VIA導孔SC3被連接於源極端子電極S3。
半絕緣性基板為,GaAs基板、SiC基板、GaN基板、SiC基板上形成有GaN磊晶層的基板、SiC基板上形成有GaN/AlGaN構成之異質接合磊晶層的基板、藍寶石基板、或鑽石基板之其中任一。
作為沿圖5B之III-III線之模式斷面構成,分立式電晶體之構成例1,係如圖6所示,具備:半絕緣性基板110;氮化物系化合物半導體層112,配置於半絕緣性基板110上;配置於氮化物系化合物半導體層112上的鋁氮化鎵層(Alx
Ga1-x
N)(0.1≦x≦1)118;配置於鋁氮化鎵層(Alx
Ga1-x
N)(0.1≦x≦1)118上的閘極指部電極124、源極指部電極120及汲極指部電極122。於氮化物系化合物半導體層112與鋁氮化鎵層(Alx
Ga1-x
N)(0.1≦x≦1)118之界面,被形成2次元電子氣體(2DEG:Two Dimension Electron Gas)層116。於如圖6所示構成例1表示高電子移動度電晶體(HEMT:High Electron Mobility Transistor)。
作為沿圖5B之III-III線之模式斷面構成,分立式電晶體之構成例2,係如圖7所示,具備:半絕緣性基板110;氮化物系化合物半導體層112,配置於半絕緣性基板110上;配置於氮化物系化合物半導體層112上的源極區域126及汲極區域128;配置於源極區域126上的源極指部電極120;配置於氮化物系化合物半導體層112上的閘極指部電極124;及配置於汲極區域128上的汲極指部電極122。於氮化物系化合物半導體層112與閘極指部電極124之界面,
被形成肖特基接觸(Schottky Contact)。於圖7所示構成例2表示金屬-半導體場效電晶體(MESFET:Metal Semiconductor Field Effect Transistor)。
作為沿圖5B之III-III線之模式斷面構成,分立式電晶體之構成例3,係如圖8所示,具備:半絕緣性基板110;氮化物系化合物半導體層112,配置於半絕緣性基板110上;配置於氮化物系化合物半導體層112上的鋁氮化鎵層(Alx
Ga1-x
N)(0.1≦x≦1)118;配置於鋁氮化鎵層(Alx
Ga1-x
N)(01≦x≦1)118上的源極指部電極120及汲極指部電極122;及閘極指部電極124,配置於鋁氮化鎵層(Alx
Ga1-x
N)(0.1≦x≦1)118上之凹口部。於氮化物系化合物半導體層112與鋁氮化鎵層(Alx
Ga1-x
N)(0.1≦x≦1)118之界面,被形成2DEG層116。於圖8所示構成例4係表示HEMT。
作為沿圖5B之III-III線之模式斷面構成,分立式電晶體之構成例4,係如圖9所示,具備:半絕緣性基板110;氮化物系化合物半導體層112,配置於半絕緣性基板110上;配置於氮化物系化合物半導體層112上的鋁氮化鎵層(Alx
Ga1-x
N)(0.1≦x≦1)118;配置於鋁氮化鎵層(Alx
Ga1-x
N)(0.1≦x≦1)118上的源極指部電極120及汲
極指部電極122;及閘極指部電極124,配置於鋁氮化鎵層(Alx
Ga1-x
N)(0.1≦x≦1)118上之2段凹口部。於氮化物系化合物半導體層112與鋁氮化鎵層(Alx
Ga1-x
N)(0.1≦x≦1)118之界面,被形成2DEG層116。於圖15所示構成例4係表示HEMT。
又,於上述構成例4,係以活化區域以外之氮化物系化合物半導體層112作為電性非活化之元件分離區域使用。其中活化區域係由:源極指部電極120、閘極指部電極124及汲極指部電極122正下方之2DEG層116;及源極指部電極120與閘極指部電極124間、以及汲極指部電極122與閘極指部電極124間之2DEG層116構成。於上述構成例4,係以該活化區域以外之氮化物系化合物半導體層112作為電性非活化之元件分離區域使用。
元件分離區域之其他形成方法,亦可直至鋁氮化鎵層(Alx
Ga1-x
N)(0.1≦x≦1)118及氮化物系化合物半導體層112之深度方向之一部分為止,藉由離子植入來形成。離子種可使用例如N(氮)、Ar(氬)、等。另外,離子植入伴隨之摻雜量可為例如約1×1014
(離子/cm2
),加速能量可為例如約100keV~200keV。
於元件分離區域上及裝置表面上形成鈍化用的絕緣層(未圖示)。該絕緣層可藉由例如PECVD(Plasma Enhanced Vapor Deposition)法沈積之Al2
O3
膜、SiO2
膜、SiON膜等形成。
源極指部電極120及汲極指部電極122,係由例如Ti/
Al等形成。閘極指部電極124,係由例如Ni/Au等形成。
另外,閘極指部電極124、源極指部電極120、及汲極指部電極122之長邊方向之圖案長度,係隨微波/毫米波/次毫米波與動作頻率之變為越高而設為越短。
依據第1實施形態可以大幅縮小電容器面積、引線長度,可實現微波/毫米波之積體電路尺寸之小型化。
依據第1實施形態,將複數個電晶體、複數個匹配電路、複數個偏壓電路分別配置、連接於封裝內,因此可以縮小作為封裝之元件之尺寸。
依據第1實施形態,將複數個電晶體、複數個匹配電路、複數個偏壓電路分別配置、連接於封裝內,因此可以降低作為封裝之元件之成本。
依據第1實施形態,將匹配電路形成於便宜之介電體基板上,可以提供實現高價位之半導體之尺寸之小型化,便宜之具有多晶片模組結構的高頻電路。
依據第1實施形態,可以提供實現微波/毫米波之積體電路尺寸之小型化,便宜之具有多晶片模組結構的高頻電路。
第2實施形態之具有多晶片模組結構的高頻電路30之模式平面圖案構成,係如圖10所示,具備:用於形成複數個分立式電晶體FET1~FET3的半導體基板160
;用於形成電容器C1~C4的第1介電體基板141
~144
;及用於形成匹
配電路的第2介電體基板181
~182
;複數個分立式電晶體FET1~FET3被串聯連接。
複數個分立式電晶體FET1~FET3,係被集積形成於同一之半導體基板160
上,因此和第1實施形態比較可以提升集積度。
半導體基板160
、第1介電體基板141
~144
、及第2介電體基板181
~182
,係於1個封裝基板10上被框架構件12包圍而配置,被收容於1個封裝內。
用於搭載分立式電晶體FET1~FET3的半導體基板160
,可以直接裝配於封裝基板10之表面上。
另外,半導體基板160
,可以僅包含分立式電晶體FET1~FET3,及分立式電晶體FET1~FET3之閘極端子電極G1~G3、源極端子電極S1~S3及汲極端子電極D1~D3作為電路要素。
圖10對應之多段放大電路之模式電路構成,係和圖2同樣表示。同樣地,3段之分立式電晶體FET1~FET3被串聯呈現級聯連接而構成多段放大器。
另外,第2實施形態之具有多晶片模組結構的高頻電路30使用的分立式電晶體FET1~FET3,係和第1實施形態同樣,例如可以適用FET、HEMT等。
如圖10所示,於輸入端子Pi被連接電容器C1,於輸出端子Po被連接電容器C4。
在介由電容器C1連接於輸入端子Pi的閘極輸入端子g1,係藉由閘極偏壓VGG
被供給閘極電壓Vgg1。
閘極輸入端子g1,係介由輸入傳送線路λ g1被連接於分立式電晶體FET1之閘極端子電極G1。
分立式電晶體FET1之汲極端子電極D1,係介由輸出傳送線路λ d1被連接於汲極輸出端子d1。
於汲極輸出端子d1,係藉由汲極偏壓VDD
被供給汲極電壓Vdd1。
於汲極輸出端子d1被連接電容器C2。
在汲極輸出端子d1介由電容器C2連接的閘極輸入端子g2,係藉由閘極偏壓VGG
被供給閘極電壓Vgg2。
閘極輸入端子g2,係介由輸入傳送線路λ g2被連接於分立式電晶體FET2之閘極端子電極G2。其中,輸入傳送線路λ g2,係配置於第1介電體基板144
上,因此和第1實施形態比較可提升集積度。
分立式電晶體FET2之汲極端子電極D2,係介由輸出傳送線路λ d2被連接於汲極輸出端子d2。其中,輸出傳送線路λ d2,係配置於第1介電體基板143
上,因此和第1實施形態比較可提升集積度。
於汲極輸出端子d2,係藉由汲極偏壓VDD
被供給汲極電壓Vdd2。
於汲極輸出端子d2被連接電容器C3。
於汲極輸出端子d2介由電容器C3被連接的閘極輸入端子g3,係藉由閘極偏壓VGG
被供給閘極電壓Vgg3。
閘極輸入端子g3,係介由輸入傳送線路λ g3被連接於分立式電晶體FET3之閘極端子電極G3。
分立式電晶體FET3之汲極端子電極D3,係介由輸出傳送線路λ d3被連接於汲極輸出端子d3。
於汲極輸出端子d3,係藉由汲極偏壓VDD
被供給汲極電壓Vdd3。
於汲極輸出端子d3被連接電容器C4,電容器C4被連接於輸出端子Po。
於此,複數個分立式電晶體FET1~FET3之中,相對於最終段使用之分立式電晶體FET3之閘極寬,使其前段使用之分立式電晶體FET2之閘極寬構成為較窄,如此而構成級聯連接之多段放大器亦可。
另外,複數個分立式電晶體FET1~FET3之中,相對於第2段使用之分立式電晶體FET2之閘極寬,使第1段使用之分立式電晶體FET1之閘極寬構成為較窄,如此而構成級聯連接之多段放大器亦可。
沿圖10之IV-IV線之模式斷面結構,係如圖11所示,具備:封裝基板10;配置於封裝基板10上的絕緣層20;配置於絕緣層20上的輸入帶狀線221
;配置於封裝基板10上的第1介電體基板141
、142
;及配置於封裝基板10上的半導體基板160
。
於第1介電體基板141
、142
分別配置電容器C1、C2,於半導體基板160
配置分立式電晶體FET1。
藉由調整第1介電體基板141
之厚度t可以第1介電體基板141
作為電容器形成用之基板使用。因為變化第1介電體基板141
之厚度可以變化電容器值。同樣,變化第1介電體
基板141
之介電率可以變化電容器值。
沿圖10之V-V線之模式斷面結構圖,係如圖12示,具備:封裝基板10;配置於封裝基板10上的絕緣層20;配置於絕緣層20上的輸出帶狀線222
;配置於封裝基板10上的第1介電體基板143
、144
;配置於封裝基板10上的半導體基板160
;及配置於封裝基板10上的第2介電體基板181
、182
。
於第1介電體基板143
、144
分別配置電容器C3、C4,於半導體基板163
配置分立式電晶體FET3。
於第2介電體基板181
、182
分別配置輸入匹配電路、輸出匹配電路。
如圖12所示,可以適當變更第1介電體基板143
、144
及第2介電體基板181
、182
之厚度。另外,變化介電率可以調整電容器值,可以調整配置之傳送線路之特性阻抗。同樣,可以大幅縮短電容器面積、所配置之引線長度。
第2實施形態之具有多晶片模組結構的高頻電路之中,適用之分立式電晶體FET3之一部分被擴大的模式平面圖案構成,係和圖5A、圖5B同樣表示,斷面結構亦和圖6~9同樣表示。另外,分立式電晶體FET1~FET2亦和分立式電晶體FET3為同樣之構成。
第2實施形態之具有多晶片模組結構的高頻電路30之中,自配置於同一半導體基板160
上的分立式電晶體FET1~FET3之輸入端子Pi至輸出端子Po為止之信號流之說明用的模式平面圖案構成,係如圖13所示。於圖13,於半導體基板160
之周邊部被圖示有第2介電體基板181
、182
,第1介電體基板141
~144
被省略圖示。另外,自汲極端子電極D1至閘極端子電極G2之信號傳送,雖被圖示於第2介電體基板182
上,但由圖10可知亦包含於省略之第1介電體基板142
、144
。同樣,自汲極端子電極D2至閘極端子電極G3之信號傳送,雖被圖示於第2介電體基板181
上,但由圖10可知亦包含於省略之第1介電體基板143
。
在分立式電晶體FET1~FET3之閘極端子電極G1~G3/汲極端子電極D1~D3間傳送之信號流程之說明用的模式平面圖案構成,係如圖14所示。
第2實施形態之具有多晶片模組結構的高頻電路30,係如圖13、14所示,具備:用於形成串聯連接之複數個分立式電晶體FET1~FET3的同一半導體基板160
;用於形成電容器的第1介電體基板(未圖示);用於形成匹配電路的第2介電體基板181
~182
;用於配置半導體基板160
、第1介電體基板、及第2介電體基板181
、182
的封裝基板10;及輸入端子Pi與輸出端子Po,被配置於封裝基板10之對向之邊;複數個分立式電晶體FET1~FET3之信號傳送方向,係依各段別呈現互異。
複數個分立式電晶體FET1~FET3之信號傳送方向係
對應於各段別呈現互異。亦即,如圖10、13~14所示,由分立式電晶體FET1之閘極端子電極G1至汲極端子電極D1之信號傳送方向,與由分立式電晶體FET2之閘極端子電極G2至汲極端子電極D2之信號傳送方向,係呈相反方向。由分立式電晶體FET2之閘極端子電極G2至汲極端子電極D2之信號傳送方向,與由分立式電晶體FET3之閘極端子電極G3至汲極端子電極D3之信號傳送方向,係呈相反方向。
第2實施形態之具有多晶片模組結構的高頻電路30之中,同一半導體基板160
上配置的分立式電晶體FET被配置成為奇數段(FET1~FET2k+1,其中k為1以上之整數)時,自輸入端子Pi至輸出端子Po為止的信號流之說明用的模式平面圖案構成,係如圖15所示。於圖15,於半導體基板160
之周邊部被圖示有第2介電體基板181
、182
,第1介電體基板141
~144
被省略圖示。另外,自汲極端子電極D1至閘極端子電極G2之信號傳送,雖被圖示於第2介電體基板182
上,但由圖13亦同樣可知包含於省略之第1介電體基板142
、144
。同樣,自汲極端子電極D2至閘極端子電極G3之信號傳送,雖被圖示於第2介電體基板181
上,但由圖13亦同樣可知包含於省略之第1介電體基板143
。
另外,第2實施形態之具有多晶片模組結構的高頻電路30,係如圖15所示,複數個分立式電晶體係具備奇數段(FET1、FET2、...、FET2k、FET2k+1,其中k為1以上之整數),第奇數段之閘極端子電極與汲極端子電極間
之信號傳送方向,係和配置有輸入端子Pi與輸出端子Po的邊呈垂直之方向,而且相等於輸入端子Pi與輸出端子Po間之輸出入信號傳送方向。
又,第2實施形態之具有多晶片模組結構的高頻電路30,係如圖15所示,第偶數段之分立式電晶體之閘極端子電極與汲極端子電極間之信號傳送方向,係和配置有輸入端子Pi與輸出端子Po的邊呈垂直之方向,而且和輸入端子Pi與輸出端子Po間之輸出入信號傳送方向呈相反方向。
自分立式電晶體FET1~FET2k+1之閘極端子電極G1~G2 k+1至汲極端子電極D1~D2 k+1的信號傳送方向,係對應於各段別呈互異.亦即,如圖15所示,由分立式電晶體FET1之閘極端子電極G1至汲極端子電極D1之信號傳送方向,與由分立式電晶體FET2之閘極端子電極G2至汲極端子電極D2之信號傳送方向,係呈相反方向。由分立式電晶體FET2之閘極端子電極G2至汲極端子電極D2之信號傳送方向,與由分立式電晶體FET3之閘極端子電極G3至汲極端子電極D3之信號傳送方向,係呈相反方向。可以同樣地擴張,由分立式電晶體FET2k之閘極端子電極G2至汲極端子電極D2之信號傳送方向,與由分立式電晶體FET2k+1之閘極端子電極G2k+1至汲極端子電極D2k+1之信號傳送方向,係呈相反方向。
依據第2實施形態,同一半導體基板160
上配置的分立式電晶體FET為奇數段(FET1~FET2k+1,其中k為1以上之整數)時,藉由將輸入端子Pi與輸出端子Po配置於封裝
基板10之對向邊,可以良好迴避輸出入信號間之串訊(cross-talk)。
第2實施形態之變形例之具有多晶片模組結構的高頻電路30之中,同一半導體基板160
上配置的分立式電晶體FET1~FET4之自輸入端子Pi至輸出端子Po為止的信號流之說明用的模式平面圖案構成,係如圖16所示。於圖16,係於半導體基板160
之周邊部被圖示有第2介電體基板181
、182
,第1介電體基板則被省略圖示。
另外,在分立式電晶體FET1~FET4之閘極端子電極/汲極端子電極間傳送的信號流之說明用的模式平面圖案構成,係如圖17所示。
第2實施形態之變形例之具有多晶片模組結構的高頻電路30,係如圖16、17所示,具備:用於形成串聯連接之複數個分立式電晶體FET1~FET4的同一半導體基板160
;用於形成電容器的第1介電體基板(未圖示);用於形成匹配電路的第2介電體基板181
~182
;用於配置半導體基板160
、第1介電體基板、及第2介電體基板181
、182
的封裝基板10;及輸入端子Pi與輸出端子Po,被配置於封裝基板10之對向之邊;複數個分立式電晶體FET1~FET3之信號傳送方向基於各段別呈現互異之點係和實施形態相同。
亦即,如圖16~17所示,分立式電晶體FET1之閘極端子電極G1至汲極端子電極D1之信號傳送方向,與分立式
電晶體FET2之閘極端子電極G2至汲極端子電極D2之信號傳送方向,係呈相反方向;分立式電晶體FET2之閘極端子電極G2至汲極端子電極D2之信號傳送方向,與分立式電晶體FET3之閘極端子電極G3至汲極端子電極D3之信號傳送方向,係呈相反方向;分立式電晶體FET3之閘極端子電極G3至汲極端子電極D3之信號傳送方向,與分立式電晶體FET4之閘極端子電極G4至汲極端子電極D4之信號傳送方向,係呈相反方向。
第2實施形態之變形例之具有多晶片模組結構的高頻電路30之中,同一半導體基板160
上配置的分立式電晶體FET為偶數段(FET1~FET2m,其中m為1以上之整數)時,自輸入端子Pi至輸出端子Po為止的信號流之說明用的模式平面圖案構成,係如圖18所示。於圖18,亦於半導體基板160
之周邊部圖示有第2介電體基板181
、182
,第1介電體基板等則省略圖示。
另外,第2實施形態之變形例之具有多晶片模組結構的高頻電路30之中,複數個分立式電晶體係具備偶數段(FET1~FET2m,其中m為1以上之整數),各段之閘極端子電極G1~G2m與汲極端子電極D1~D2m間之信號傳送方向,係和配置有輸入端子Pi與輸出端子Po的邊呈平行之方向,而且和輸入端子Pi與輸出端子Po間之輸出入信號傳送方向呈垂直之方向。
又,第奇數段分立式電晶體之閘極端子電極與汲極端子電極間之信號傳送方向,係和第偶數段之分立式電晶體
之閘極端子電極與汲極端子電極間之信號傳送方向,呈相反方向。
亦即,如圖18所示,分立式電晶體FET1之閘極端子電極G1至汲極端子電極D1之信號傳送方向,與分立式電晶體FET2之閘極端子電極G2至汲極端子電極D2之信號傳送方向,係呈相反方向;分立式電晶體FET2之閘極端子電極G2至汲極端子電極D2之信號傳送方向,與分立式電晶體FET3之閘極端子電極G3至汲極端子電極D3之信號傳送方向,係呈相反方向。可以同樣地擴張,由分立式電晶體FET2m-1之閘極端子電極G2m-1至汲極端子電極D2m-1之信號傳送方向,與由分立式電晶體FET2m之閘極端子電極G2m至汲極端子電極D2m之信號傳送方向,係呈相反方向。
依據第2實施形態之變形例,同一半導體基板160
上配置的分立式電晶體FET為偶數段(FET1~FET2m,其中m為1以上之整數)時,藉由將輸入端子Pi與輸出端子Po配置於封裝基板10之對向邊,可以良好迴避輸出入信號間之串訊(cross-talk)。
依據第2實施形態及變形例,可以大幅縮小電容器面積、引線長度,可實現微波/毫米波之積體電路尺寸之小型化。
依據第2實施形態及變形例,將複數個電晶體、複數個匹配電路、複數個偏壓電路分別配置、連接於封裝內,因此可以縮小作為封裝之元件之尺寸,另外,可以降低封
裝之成本。
依據第2實施形態及變形例,將匹配電路形成於便宜之介電體基板上,可以提供實現高價位之半導體之尺寸之小型化,便宜之具有多晶片模組結構的高頻電路。
依據第2實施形態及變形例,和第1實施形態比較,更能實現積體電路尺寸之小型化。
依據第2實施形態及變形例,可以提供實現微波/毫米波之積體電路尺寸之小型化,便宜之具有多晶片模組結構的高頻電路。
如上述本發明係針對第1-第2實施形態及變形例加以說明,但該揭示之一部分之論述及圖面僅為一例,並非用來限定本發明,可以作各種變更實施及運用。
又,第1~第2實施形態及變形例之具有多晶片模組結構的高頻電路,其適用之分立式電晶體並不限定於FET、HEMT,亦適用於LDMOS(Laterally Diffused Metal-Oxide-Semiconductor Field Effect Transistor)或異質接合雙極性電晶體(HBT:Hetero-junction Bipolar Transistor)等之放大元件,微電機系統(MEMS:Micro Electro Mechanical System)元件等。
另外,第1~第2實施形態及變形例之具有多晶片模組結構的高頻電路,其適用之分立式電晶體之級聯連接之段數不限定於3段,亦可為4段以上。
如上述說明,本發明亦包含上述說明中未記載之各種實施形態。
本發明之具有多晶片模組結構的高頻電路,可以適用於微波電力放大器、毫米波電力放大器、高頻MEMS元件等廣範圍之領域。
依本發明可以提供能縮小微波、毫米波中之積體電路尺寸、便宜的具有多晶片模組結構的高頻電路。
10‧‧‧封裝基板
12‧‧‧框架構件
160
、161
~163
‧‧‧半導體基板
141
~144
‧‧‧第1介電體基板
181
、182
‧‧‧第2介電體基板
20‧‧‧絕緣層
221
‧‧‧輸入帶狀線
222
‧‧‧輸出帶狀線
30‧‧‧高頻電路
110‧‧‧半絕緣性基板
112‧‧‧氮化物系化合物半導體層(GaN磊晶成長層)
116‧‧‧2次元電子氣體(2DEG)層
118‧‧‧鋁氮化鎵層(Alx
Ga1-x
N)(0.1≦x≦1)
120‧‧‧源極指部電極
122‧‧‧汲極指部電極
124‧‧‧閘極指部電極
126‧‧‧源極區域
128‧‧‧汲極區域
Pi‧‧‧輸入端子
Po‧‧‧輸出端子
FET1~FET2k、FET2k+1、FET2m-1、FET2m‧‧‧分立式電晶體
C1~C4‧‧‧電容器
λ g1~λ g3‧‧‧輸入傳送線路
λ d1~λ d3‧‧‧輸出傳送線路
Vgg1~Vgg3‧‧‧閘極電壓
Vdd1~Vdd3‧‧‧汲極電壓
VGG
‧‧‧閘極偏壓
VDD
‧‧‧汲極偏壓
S1~S3‧‧‧源極端子電極
SC3‧‧‧VIA導孔
D1~D2k、D2k+1、D2m-1、D2m‧‧‧汲極端子電極
G1~G2k、G2k+1、G2m-1、G2m‧‧‧閘極端子電極
g1~g3‧‧‧閘極輸入端子
d1~d3‧‧‧汲極輸入端子
圖1為本發明第1實施形態之具有多晶片模組結構的高頻電路之模式平面圖案構成。
圖2為對應於圖1,3段之分立式電晶體FET1~FET3串聯連接而構成多段放大電路之模式電路構成。
圖3為沿圖1之I-I線之模式斷面結構圖。
圖4為沿圖1之II-II線之模式斷面結構圖。
圖5A為本發明第1實施形態之具有多晶片模組結構的高頻電路所適用之分立式電晶體FET3之一部分被擴大的模式平面圖案構成。
圖5B為圖5A之J部分之擴大圖。
圖6為分立式電晶體之構成例1,係沿圖5B之III-III
線之模式斷面結構圖。
圖7為分立式電晶體之構成例2,係沿圖5B之III-III線之模式斷面結構圖。
圖8為分立式電晶體之構成例3,係沿圖5B之III-III線之模式斷面結構圖。
圖9為分立式電晶體之構成例4,係沿圖5B之III-III線之模式斷面結構圖。
圖10為本發明第2實施形態之具有多晶片模組結構的高頻電路之模式平面圖案構成。
圖11為沿圖10之IV-IV線之模式斷面結構圖。
圖12為沿圖10之V-V線之模式斷面結構圖。
圖13為本發明第2實施形態之具有多晶片模組結構的高頻電路之中,配置於同一半導體基板160
上的分立式電晶體FET1~FET3之輸入端子Pi至輸出端子Po為止的信號流之說明用的模式平面圖案構成。
圖14為本發明第2實施形態之具有多晶片模組結構的高頻電路之中,配置於同一半導體基板160
上的分立式電晶體FET1~FET3之傳送於閘極端子電極G1~G3/汲極端子電極D1~D3間的信號流之說明用的模式平面圖案構成。
圖15為本發明第2實施形態之具有多晶片模組結構的高頻電路之中,配置於同一半導體基板160
上的分立式電晶體以奇數段配置時,輸入端子Pi至輸出端子Po為止的信號流之說明用的模式平面圖案構成。
圖16為本發明第2實施形態之變形例之具有多晶片模組結構的高頻電路之中,配置於同一半導體基板160
上的分立式電晶體FET1~FET4之輸入端子Pi至輸出端子Po為止的信號流之說明用的模式平面圖案構成。
圖17為本發明第2實施形態之變形例之具有多晶片模組結構的高頻電路之中,配置於同一半導體基板160
上的分立式電晶體FET1~FET4之傳送於閘極端子電極/汲極端子電極間的信號流之說明用的模式平面圖案構成。
圖18為本發明第2實施形態之具有多晶片模組結構的高頻電路之中,配置於同一半導體基板160
上的分立式電晶體以偶數段配置時,輸入端子Pi至輸出端子Po為止的信號流之說明用的模式平面圖案構成。
10‧‧‧封裝基板
12‧‧‧框架構件
160
、161
~163
‧‧‧半導體基板
141
~144
‧‧‧第1介電體基板
181
、182
‧‧‧第2介電體基板
FET1~FET3‧‧‧分立式電晶體
C1~C4‧‧‧電容器
Pi‧‧‧輸入端子
D1~D3‧‧‧汲極端子電極
S1~S3‧‧‧源極端子電極
G1~G3‧‧‧閘極端子電極
VGG
‧‧‧閘極偏壓
VDD
‧‧‧汲極偏壓
g1~g3‧‧‧閘極輸入端子
d1~d3‧‧‧汲極輸入端子
30‧‧‧高頻電路
Claims (13)
- 一種具有多晶片模組結構的高頻電路,係包含:半導體基板,用於形成複數個分立式電晶體;第1介電體基板,用於形成電容器;及第2介電體基板,用於形成匹配電路;上述複數個分立式電晶體被串聯連接;上述半導體基板、上述第1介電體基板及上述第2介電體基板,係配置於1個封裝基板上,收容於1個封裝內,而且搭載上述分立式電晶體的上述半導體基板,係直接裝配於(mount)上述封裝基板之表面上。
- 如申請專利範圍第1項之具有多晶片模組結構的高頻電路,其中上述複數個分立式電晶體被形成於同一之上述半導體基板上。
- 如申請專利範圍第1項之具有多晶片模組結構的高頻電路,其中上述複數個分立式電晶體分別被形成於複數個之個別之上述半導體基板上。
- 如申請專利範圍第1~3項中任一項之具有多晶片模組結構的高頻電路,其中上述半導體基板,係僅包含上述分立式電晶體、上述分立式電晶體之閘極端子電極、源極端子電極及汲極端子電極作為電路要素。
- 如申請專利範圍第1~3項中任一項之具有多晶片模 組結構的高頻電路,其中上述複數個分立式電晶體之中,相對於最終段使用之分立式電晶體之閘極寬,其前段使用之分立式電晶體之閘極寬較窄。
- 如申請專利範圍第1~3項中任一項之具有多晶片模組結構的高頻電路,其中上述複數個分立式電晶體之閘極端子電極與汲極端子電極間之信號傳送方向,係依各段別而呈互異。
- 一種具有多晶片模組結構的高頻電路,係包含:同一半導體基板,用於形成被串聯連接的複數個分立式電晶體;第1介電體基板,用於形成電容器;第2介電體基板,用於形成匹配電路;封裝基板,用於配置上述半導體基板、上述第1介電體基板、與上述第2介電體基板;及輸入端子與輸出端子,被配置於上述封裝基板之對向之邊;上述複數個分立式電晶體之閘極端子電極與汲極端子電極間之信號傳送方向,係依各段別而呈互異。
- 如申請專利範圍第7項之具有多晶片模組結構的高頻電路,其中上述複數個分立式電晶體係具備奇數段,第奇數段之閘極端子電極與汲極端子電極間之信號傳送方向,係和上述輸入端子與上述輸出端子被配置之邊呈垂直之方向,而 且相等於上述輸入端子與上述輸出端子間之輸出入信號傳送方向。
- 如申請專利範圍第8項之具有多晶片模組結構的高頻電路,其中第偶數段分立式電晶體之之閘極端子電極與汲極端子電極間之信號傳送方向,係和上述輸入端子與上述輸出端子被配置之邊呈垂直之方向,而且和上述輸出入信號傳送方向呈相反方向。
- 如申請專利範圍第7項之具有多晶片模組結構的高頻電路,其中上述複數個分立式電晶體係具備偶數段,各段之閘極端子電極與汲極端子電極間之信號傳送方向,係和上述輸入端子與上述輸出端子被配置之邊呈平行之方向,而且和上述輸入端子與上述輸出端子間之輸出入信號傳送方向呈垂直之方向。
- 如申請專利範圍第10項之具有多晶片模組結構的高頻電路,其中第奇數段分立式電晶體之之閘極端子電極與汲極端子電極間之信號傳送方向,係和第偶數段分立式電晶體之閘極端子電極與汲極端子電極間之信號傳送方向呈相反方向。
- 如申請專利範圍第1~3或7~11項中任一項之具有多晶片模組結構的高頻電路,其中上述複數個分立式電晶體,係具備: 半絕緣性基板;閘極指部電極、源極指部電極及汲極指部電極,配置於上述半絕緣性基板之第1表面,分別具有複數個指部;複數個閘極端子電極、複數個源極端子電極及複數個汲極端子電極,配置於上述半絕緣性基板之第1表面,依上述閘極指部電極、上述源極指部電極及上述汲極指部電極類別將複數個指部分別捆綁而形成;VIA導孔,配置於上述源極端子電極下部;及接地電極,配置於上述半絕緣性基板之第1表面相反側的第2表面,介由上述VIA導孔被連接於上述源極端子電極。
- 如申請專利範圍第12項之具有多晶片模組結構的高頻電路,其中上述半絕緣性基板為,GaAs基板、SiC基板、GaN基板、SiC基板上形成有GaN磊晶層的基板、SiC基板上形成有GaN/AlGaN構成之異質接合磊晶層的基板、藍寶石基板、或鑽石基板之其中任一。
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JP6003238B2 (ja) * | 2012-05-30 | 2016-10-05 | 住友電気工業株式会社 | 半導体装置 |
JP6338832B2 (ja) | 2013-07-31 | 2018-06-06 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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- 2010-05-24 EP EP10250964.3A patent/EP2287905A3/en not_active Withdrawn
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JP5631607B2 (ja) | 2014-11-26 |
KR20110020162A (ko) | 2011-03-02 |
KR101148351B1 (ko) | 2012-05-21 |
JP2011066380A (ja) | 2011-03-31 |
US20110044016A1 (en) | 2011-02-24 |
EP2287905A2 (en) | 2011-02-23 |
EP2287905A3 (en) | 2016-06-22 |
US8345434B2 (en) | 2013-01-01 |
TW201108389A (en) | 2011-03-01 |
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