TWI478255B - 回銲前銲料凸塊之清除 - Google Patents

回銲前銲料凸塊之清除 Download PDF

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Publication number
TWI478255B
TWI478255B TW101124371A TW101124371A TWI478255B TW I478255 B TWI478255 B TW I478255B TW 101124371 A TW101124371 A TW 101124371A TW 101124371 A TW101124371 A TW 101124371A TW I478255 B TWI478255 B TW I478255B
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Taiwan
Prior art keywords
solder bump
exposing
cleaning process
solder
wet chemical
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Application number
TW101124371A
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English (en)
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TW201308457A (zh
Inventor
Reiner Willeke
Original Assignee
Globalfoundries Us Inc
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Publication of TW201308457A publication Critical patent/TW201308457A/zh
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Publication of TWI478255B publication Critical patent/TWI478255B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/008—Soldering within a furnace
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
    • B23K1/206—Cleaning
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    • B23K2101/00—Articles made by soldering, welding or cutting
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Description

回銲前銲料凸塊之清除
本揭示內容大體有關於精密積體電路，且更特別的是，有關於形成無鉛銲料凸塊於半導體晶片的接觸層上的方法。
在製造現代積體電路時，通常需要在構成微型電子裝置的各種半導體晶片之間加上電氣連接。取決於晶片的類型與整體的裝置設計要求，可用各種方法實現這些電氣連接，例如，打線接合法、卷帶式自動接合法(TAB)，覆晶接合法及其類似者。近年來，利用覆晶技術，其中半導體晶片用由所謂銲料凸塊形成的銲球來附著至基板、載體或其他晶片，已變成半導體加工工業的重要方面。在覆晶技術中，銲球形成於待連接晶片中的至少一的接觸層上，例如，在形成於包含多個積體電路的半導體晶片的最後金屬化層上方的電介質鈍化層上。同樣，有適當大小及定位的接合墊形成於另一晶片上，例如，承載封裝件，各個接合墊對應至形成於半導體晶片上的銲球。然後，這兩種單元(亦即，半導體晶片與承載封裝件)的電氣連接通過“翻轉”半導體晶片以及使銲球與接合墊物理接觸，以及進行“回銲”製程使得每個銲球粘著至對應接合墊。通常有數百甚至數千個銲料凸塊可分佈於整個晶片區域，由此提供，例如，現代半導體晶片所要求的輸入及輸出性能，而現代半導體晶片經常包括複雜的電路，例如微處理器、儲存電路、三維(3D)晶片及其類似者，及/或形成完整複雜電路系統的 多個積體電路。
過去，用來形成使用於覆晶技術的銲球的材料包括各種所謂錫/鉛(Sn/Pb)銲料中的任一。在最常見的商用Sn/Pb銲料合金中，錫(Sn)的數量可在約5原子重量百分比至約70原子重量百分比之間改變，以及銲料合金的平衡物(balance)為鉛(Pb)。此外，Sn/Pb銲料合金的熔化溫度會隨著確切的合金構造而改變，此因素對整體加工參數有點影響。在半導體加工工業中，最常用的Sn/Pb銲料為5/95銲料(亦即，5%錫與95%鉛)，60/40銲料(亦即，60%錫與40%鉛)，以及63/37銲料(亦即，63%錫與37%鉛，或所謂的“共晶”混合物)。共晶Sn/Pb銲料的優點是Sn/Pb銲料(183℃)的最低熔化溫度為真正的一點，而其他非共晶Sn/Pb合金所展現的是一範圍。
不過，近年來，製造工業大體已放棄使用Sn/Pb銲料於大部份的商業應用，包括半導體加工。因此，已開發出無鉛銲接材料，例如Sn/Ag(錫-銀)、Sn/Cu(錫-銅)、Sn/Ag/Cu(錫-銀-銅，或SAC)銲料及其類似者，作為用於形成銲料凸塊的替代合金。不過，這些替代銲接材料通常有比大部份常用Sn/Pb銲料高一點的熔化溫度。此外，這些無鉛銲接材料中至少有一些顯出與製程有關的其他難題而在半導體裝置製造期間必須予以處理，這在下文有更詳細的討論。
第1圖的加工流程圖根據一背景技術銲料凸塊製程圖示包含形成無鉛銲料凸塊步驟的不同步驟順序。一般而言， 圖示於第1圖的示範背景技術製程順序包括形成凸塊下金屬化(UBM)層的第一製程步驟110，之後，在步驟130的銲料電鍍製程之前，進行形成光阻遮罩的製程步驟120。之後，在製程步驟140剝除光阻遮罩，在製程步驟150蝕刻UBM層，以及最後，在製程步驟160進行銲料凸塊回銲製程。標示於第1圖以及上文以大體方式描述的每個製程步驟分別圖示於第1a圖至第1f圖，這在下文會加以詳述。
第1a圖示意圖示第1圖的製程步驟110，其中形成凸塊下金屬化(UBM)層104。凸塊下金屬化層104可形成於帶圖案鈍化層103上，而帶圖案鈍化層103可形成於半導體裝置100的最後金屬化層101上方。取決於整體裝置架構要求，半導體裝置100可包含多個積體電路元件，例如電晶體、電容器、電阻器、導線、接觸元件及其類似者。另外，帶圖案鈍化層103可包含開口103a，其經定位成可暴露形成於最後金屬化層101的上半部的導電接觸墊102，它可提供至半導體裝置100的多個積體電路元件中之一或更多的電氣接點。
如第1a圖所示，UBM層104可以實質共形的方式形成於帶圖案鈍化層103上方以便覆蓋導電接觸墊102的暴露上表面，開口103a的側壁表面，以及鈍化層103的上表面。取決於整體加工流程及裝置要求，UBM層104可包含多個個別層，其中各層可經個別設計成可提供整體UBM層104的必要黏性、阻障、保護及導電特性。例如，UBM層104可包含但不必受限於：鈦-鎢/鉻-銅/銅(TiW/CrCu/Cu)疊 層、鉻/鉻-銅/銅(Cr/CrCu/Cu)疊層、鈦-鎢/銅(TiW/Cu)疊層、鈦/銅/鎳(Ti/Cu/Ni)疊層、鈦-鎢/鎳-釩/銅(TiW/NiV/Cu)疊層及其類似者，其中最終銅層在隨後進行的電鍍製程(參考製程步驟130與第1c圖)中可用作電流分佈層(current distribution layer)。可用經適當設計的沈積順序111來形成UBM層104，取決於材料種類與所使用的層數，可包含濺鍍沈積製程、化學氣相沈積(CVD)製程及其類似者，或該等製程的組合。
第1b圖示意圖示在後續製造步驟期間的第1a圖的半導體裝置100。更特別的是，第1b圖圖示第1圖的製程步驟120，其中形成帶圖案光阻遮罩105於UBM層104上方。取決於想要的整合方案，帶圖案光阻遮罩105可用製程順序121形成，包括基於本領域技術人員所熟知的傳統微影技術的多個步驟。如第1b圖所示，帶圖案光阻遮罩105可包含形成於帶圖案鈍化層103的開口103a上方的開口105a，由此定義銲料凸塊106在剛鍍成狀態(as-plated condition)下的位置及初始形狀，這在下文有更完整的描述。
如第1c圖所示，在製程步驟130期間繼續進一步加工第1b圖的半導體裝置100，其中各自形成無鉛銲料凸塊106於帶圖案鈍化層103與光阻遮罩105的開口103a、105a中。如前述，凸塊下金屬化層104在電化學沈積製程131(例如，電鍍製程)期間可用作電流分佈層，由此協助用來形成銲料凸塊106的銲接材料的電化學沈積。該銲料凸塊材料 可為本技術所熟知的數種無鉛銲接材料中的任一，例如Sn/Ag、Sn/Cu、Sn/Ag/Cu(SAC)及其類似者。此外，取決於裝置要求及/或想要的加工方案，銲料凸塊106可形成於包含經電化學沈積的銅(Cu)或鎳(Ni)的底下柱體及其類似者上。例如，在至少一具體實施例中，銲料凸塊106可形成於鎳柱體上，以及可由銀含量約在1.8至3.0重量百分比的範圍內的錫/銀(Sn/Ag)合金銲接材料構成，而該銲料合金的平衡物可為實質錫。取決於不同的加工考量，例如回銲溫度及其類似者，也可使用有其他重量百分比的銀及/或銅來與錫結合。
第1d圖示意圖示在第1圖的製程步驟140期間的第1c圖的半導體裝置100，其中移除在UBM層104上方的帶圖案光阻遮罩105。如第1d圖所示，可進行光阻剝除製程141以便對於凸塊下金屬化層104及剛鍍成銲料凸塊106的材料有選擇性地移除帶圖案光阻遮罩105。取決於所欲加工策略，光阻剝除製程141，例如，可為濕式化學去除製程或乾蝕刻製程，其處方為本技術領域所熟知。在製程步驟150期間，可圖案化UBM層104以便使銲料凸塊106與可能在用製程步驟110至140描述的製程順序期間同時形成的其他毗鄰銲料凸塊電氣隔離。如第1e圖所示，取決於構成UBM層104的任何子層的數目與材料多樣性，UBM層104的圖案化可通過進行蝕刻順序151，它可包含多個濕及/或乾式蝕刻技術。
之後，包含半導體裝置100的基板可輸送至爐具(未 圖示)，在此隨後會進行凸塊回銲製程步驟160。不過，在裝載包含半導體裝置100的基板於爐具(未圖示)內之前，裝置100可暴露於周遭大氣狀態，在此期間，原生氧化錫層107可能形成於新成形銲料凸塊106的暴露表面上，如第1e圖所示。
在凸塊回銲製程步驟160期間，第1e圖的半導體裝置100可暴露於回銲製程161，如第1f圖所示，其使第1e圖的銲料凸塊106變形成為實質圓形銲球108。回銲製程161可在例如有電阻加熱器或紅外線(IR)燈的可編程烤箱或爐子中進行，而且取決於包含銲料凸塊106的銲接材料的組合物，可以約在200至300℃範圍內的回銲溫度完成。例如，對於銀含量在1.8至3.0重量百分比範圍內的Sn/Ag銲料凸塊，回銲製程161可在約225℃至250℃之間完成。另外，可用適於特定銲接材料組合物的持續時間來完成回銲製程161以便改善銲料合金材料的整體均勻度，此外，可使銲料凸塊材料擴散至UBM層104內，由此形成讓圓形銲球108有高機械韌性(mechanical toughness)的介金屬化合物(intermetallic compound)。
如上述，原生氧化錫層107可能在製程步驟150與160之間形成於銲料凸塊106的暴露表面上。通常在回銲製程161期間移除此原生氧化錫層107使得在經回銲的銲球108的表面上不會有氧化物層。因此，可在經設計成可移除可能存在於銲料凸塊106的暴露表面上的任何原生氧化錫層107的實質還原性環境中進行回銲製程161。在某些具體實 施例中，該還原性環境可包含氣態蟻酸(CH2 O2 )，其在回銲製程161期間通過與銲料凸塊106表面上的氧化錫(SnO)化學反應以形成錫副產品，例如Sn(CHO2 )2 (甲酸亞錫，tin II formate)及其類似者，來移除原生氧化錫層107。
不過，也應注意，在正常基板加工期間，在製程步驟150(UBM蝕刻)與製程步驟160(凸塊回銲)之間可能出現顯著的等待時間，有時這約有數小時，甚至一天或更多。儘管有如此長的等待時間，以及銲料凸塊對應漫長地暴露於周遭狀態，通常不會損害錫-鉛(Sn/Pb)銲料凸塊，有極高重量百分比錫濃度的銲料合金(例如，Sn/Ag銲料)可能明顯高於典型Sn/Pb銲料的表面氧化率。因此，必須從由Sn/Ag合金銲料製成的銲料凸塊106表面移除的氧化錫數量會成比例地更大。此外，在回銲製程161期間形成的任何錫副產品傾向優先沈積於爐具及排氣管的內表面上，而且隨著時間推移，可能由表面剝落而再沈積於裝置100的暴露表面(包括經回銲的銲球108)上成為粒子缺陷109，如第1f圖所示。粒子缺陷109也可能干擾在半導體晶片上的銲球108與封裝件載體上的接合墊間得到的的電氣連接，從而可能減少裝置可靠性。為了避免出現此類粒子缺陷109，必須周期性地定期清洗回銲製程161在其中進行的爐具。
在一方面，通過增加工具清洗頻率可提高裝置可靠性，亦即，縮短工具清洗周期，不過，代價是工具停機時間以及整體生產率對應地減少。另一方面，通過減少工具清洗 頻率可提供生產率，亦即，加長工具清洗周期，不過，代價是粒子缺陷增加以及整體裝置可靠性對應地減少。因此，及鑒於上述，有必要實現新的設計策略以應付與形成無鉛銲料凸塊於半導體晶片上有關的製造問題。本揭示內容是有關於加工方案用以避免或至少減少上述問題中的一或更多的影響。
下文為本揭示內容的簡化摘要供基本瞭解揭示於本文的一些方面。此摘要並非本揭示內容的詳盡概述，也不是要用來區別本發明專利標的的關鍵或重要元件，也不是描述本發明揭示標的的範疇。反之，唯一的目的是要以簡化的形式提出一些概念作為以下詳細說明內容的前言。
本發明大體有關於用以形成現代精密半導體裝置的方法，且更特別的是，可在半導體晶片的接觸層上方形成實質無鉛銲料凸塊的方法。揭示於本文的一示範方法包括下列步驟：形成銲料凸塊於半導體裝置的金屬化層上方，移除在該銲料凸塊的表面上的氧化物膜，以及在移除該氧化物膜後，在還原性環境中進行銲料凸塊回銲製程以回銲該銲料凸塊。
本揭示內容的另一示範具體實施例為包括下列步驟的方法：在形成於半導體裝置上方的最後金屬化層上方形成銲料凸塊，以及暴露該銲料凸塊於含氧環境。除了別的以外，本方法更包括：暴露該銲料凸塊於濕式化學清洗製程以實質移除在該銲料凸塊的表面上的原生氧化物膜，以 及在暴露該銲料凸塊於該濕式化學清洗製程後，在包含蟻酸的回銲環境中回銲該銲料凸塊。
本文也揭示一種方法，除了別的以外，包括下列步驟：在半導體裝置的凸塊下金屬化層上方形成實質無鉛銲料凸塊，進行濕式化學清洗製程以通過暴露該銲料凸塊於包含蟻酸及鹽酸中的一者的酸性溶液來移除在該銲料凸塊的表面上的氧化物膜，以及進行回銲製程以在包含蟻酸的環境中回銲該銲料凸塊。
以下描述本發明的各種示範具體實施方式。為了清楚說明，本專利說明書沒有描述實際具體實作的所有特徵。當然，應瞭解，在開發任一此類的實際具體實施方式時，必需做許多與具體實作有關的決策以達成開發人員的特定目標，例如遵循與系統相關及商務有關的限制，這些都會隨著每一個具體實作而有所不同。此外，應瞭解，此類開發即複雜又花時間，決不是本技術領域一般技術人員在閱讀本揭示內容後即可實作的例行工作。
此時以參照附圖來描述本發明。示意圖示於附圖的各種結構及裝置是僅供解釋以及避免本領域技術人員所熟知的細節混淆本揭示內容。儘管如此，仍納入附圖用來描述及解釋本揭示內容的示範實施例。應使用與相關技術領域技術人員所熟悉的意思一致的方式理解及解釋用於本文的字彙及片語。本文沒有特別定義的用語或片語(亦即，與本領域技術人員所理解的普通慣用意思不同的定義)是想要 用用語或片語的一致用法來暗示。在這個意義上，希望用語或片語具有特定的意思時(亦即，不同於本領域技術人員所理解的意思)，則會在本專利說明書中以直接明白地提供特定定義的方式清楚地陳述用於該用語或片語的特定定義。
一般而言，本發明提供用以形成無鉛銲料凸塊(例如，Sn/Ag銲料凸塊及其類似者)的製造技術而可減少包含在已進行銲料凸塊回銲製程後由錫副產品引起的粒子缺陷的可能性。例如，在進行銲料凸塊回銲製程之前可進行中間清洗步驟以便實質移除在暴露銲料凸塊於周遭大氣狀態期間可能形成於新成形銲料凸塊的表面上的任何原生氧化物。在一些具體實施例中，該中間清洗步驟，例如，可為濕式清洗製程，其經設計成可移除實質所有原生氧化物，以及可立即在進行回銲製程之前執行。該中間清洗製程減少與以下事項有關的整體加工問題：在凸塊下金屬化層蝕刻及圖案化之後與在進行銲料凸塊回銲製程之前可能發生長時間的等待時間。此外，在回銲製程期間存在於銲料凸塊表面上的原生氧化物層減少有助於對以下情形有較高耐受性：在進行回銲製程時，還原性環境可能無意中存在自由氧。此外，由於在任何給定回銲製程迴圈期間需要由銲料凸塊移除較少的原生氧化物，因此回銲製程爐具也可實現較長的清洗周期，因為有較少數量的反應材料(形式為錫副產品及其類似者)在給定回銲迴圈期間可能沈積於爐具的內表面上。
應注意，在適當的情況下，用於描述第2圖及第2a圖至第2c圖示範具體實施例中的各種元件的元件符號在適當的情況下實質對應至用於以上描述第1圖及第1a圖至第1f圖中的相關元件的元件符號，除了圖中元件符號的前頭數目字由“1”換成“2”以外。例如，製程步驟“130”對應至製程步驟“230”，半導體裝置“100”對應至半導體裝置“200”，最後金屬化層“101”對應至最後金屬化層“201”，銲料凸塊“106”對應至銲料凸塊“206”，等等。因此，用於識別本揭示內容中的一些元件的元件符號可能圖示於第2圖及第2a圖至第2c圖，但是不一定具體描述於以下說明。在此情況下，應瞭解，以下未詳述而圖示於第2a圖至第2c圖的帶符號元件是與圖示於第1圖有類似元件符號以及描述於以上所提出的相關揭示內容的對應物實質對應。
此外，也應瞭解，除非另有特定說明，可用於以下說明的任何相對位置或方向用語，例如“上”、“下”、“上面”、“鄰近”、“上方”、“下方”、“之上”、“之下”、“頂面”、“底面”、“垂直”、“水平”及其類似者，應被視為是按照該用語的正常及日常意思來描述附圖的元件或元件。例如，請參考第1C圖的半導體裝置100的示意橫截面，應瞭解，帶圖案鈍化層103形成於最後金屬化層101“上方”，以及導電接觸墊102位於凸塊下金屬化(UBM)層104“下方”或“之下”。同樣，也應注意，在該等具體實施例中，銲料凸塊106可位在UBM層104“上 面”，其中沒有其他層或結構介於其間。
第2圖的加工流程圖根據本發明的一示範具體實施例圖示包含形成無鉛銲料凸塊步驟的一步驟順序。一般而言，圖示於第2圖的示範製程順序包括形成凸塊下金屬化(UBM)層的第一製程步驟210，之後，在製程步驟220形成光阻遮罩，接著是步驟230的銲料電鍍製程。之後，在製程步驟240剝除光阻遮罩，以及在製程步驟250蝕刻UBM層。不過，在比較第2圖的製程順序與第1圖的背景技術加工流程順序時，可注意到，第2圖的順序包括附加凸塊清洗製程步驟255，用來移除在UBM蝕刻製程步驟250、凸塊回銲製程步驟260之間可能形成於銲料凸塊上的原生氧化物。在凸塊清洗製程步驟255後，在製程步驟260回銲銲料凸塊。第2圖中的製程步驟250、255及260分別圖示於第2A圖至第2C圖，以下會加以詳述。
如第2a圖所示的製程步驟250實質對應至圖示於第1e圖的上述製程步驟150。更特別的是，在製程步驟250期間，可圖案化UBM層204以便使銲料凸塊206與可能已在製程步驟210至240的製程順序期間同時形成的其他毗鄰銲料凸塊電氣隔離。如第2a圖所示，UBM層204的圖案化可通過進行本技術領域一般技術人員所熟知的蝕刻順序251。之後，包含半導體裝置200的基板可輸送至爐具(未圖示)，在此是隨後會進行凸塊回銲製程步驟260。在一些示範具體實施例中，在蝕刻UBM層204的製程步驟250與凸塊回銲製程步驟260之間的時間可能出現顯著的等待時 間，在此期間，銲料凸塊206可能暴露於周遭大氣狀態，以及原生氧化錫層207可能形成於新成形銲料凸塊206的暴露表面上，如第2a圖所示。
如第2b圖所示，在有些示範具體實施例中，在進行凸塊回銲製程步驟260之前，可進行凸塊清洗製程步驟255。例如，銲料凸塊206可暴露於濕式清洗製程256，其設計成可用莫耳濃度約在0.05M至4.0M的範圍內的適當酸性溶液以在15至330秒範圍內的時間來移除原生氧化錫層207。在一些具體實施例中，用於濕式清洗製程256的酸性物質可包含，例如，甲基磺酸(或甲磺酸；CH3 SO3 H)、蟻酸(CH2 O2 )、硝酸(HNO3 )、或鹽酸(HCl)。在至少一些示範具體實施例中，可用莫耳濃度在0.3M至0.5M之間的蟻酸或鹽酸以約20至120秒的持續時間來完成濕式清洗製程256。
在本揭示內容的一些具體實施例中，隨後可進行凸塊回銲製程步驟260，其中第2b圖的半導體裝置200的洗淨銲料凸塊206可暴露於回銲製程261。如第2c圖所示，回銲製程261使第2b圖的銲料凸塊206變形成為實質圓形銲球208，以及可實質完成，如以上在說明製程步驟160及第1f圖時所述。
如前述，包含相對高重量百分比的錫的無鉛銲接合金材料(例如，Sn/Ag銲料合金及其類似者)對於氧有較高的親和力，因此有相對高的表面氧化率。因此，在有些示範具體實施例中，在凸塊清洗製程步驟250完成後約12小時內，洗淨銲料凸塊206可經受銲料凸塊回銲製程步驟260 以便限制可能形成於洗淨銲料凸塊206表面上的原生氧化錫數量。接著，這可減少粒子缺陷(例如，圖示於第1F圖的粒子缺陷109)再沈積於經回銲的銲球208的表面上的可能性，以及爐具(回銲製程261在其中進行)可增加在清洗周期之間的時間。
結果，本發明可提供用以形成無鉛銲料凸塊於半導體晶片的接觸層上而可減少粒子缺陷的可能性的製造技術。另外，本發明方法使得工具在清洗周期之間有較長的運行時間，從而提高整體裝置的生產率。
以上所揭示的特定具體實施方式均僅供圖解說明，因為本領域技術人員在受益於本文的教導後顯然可以不同但等價的方式來修改及實施本發明。例如，可用不同的順序完成以上所提出的製程步驟。此外，除非在以下申請專利範圍有提及，不希望本發明受限於本文所示的構造或設計的細節。因此，顯然可改變或修改以上所揭示的特定具體實施方式而所有此類變體都被認為仍然是在本發明的範疇與精神內。因此，本文提出以下的申請專利範圍尋求保護。
100、200‧‧‧半導體裝置
101、201‧‧‧最後金屬化層
102‧‧‧導電接觸墊
103‧‧‧帶圖案鈍化層
103a、105a‧‧‧開口
104、204‧‧‧凸塊下金屬化層
105‧‧‧帶圖案光阻遮罩
106、206‧‧‧銲料凸塊
107、207‧‧‧原生氧化錫層
108、208‧‧‧銲球
109‧‧‧粒子缺陷
110、120、130、140、150、160、210、220、230、240、250、255、260‧‧‧步驟
111‧‧‧沈積順序
121‧‧‧製程順序
131‧‧‧電化學沈積製程
141‧‧‧光阻剝除製程
151、251‧‧‧蝕刻順序
161、261‧‧‧回銲製程
256‧‧‧濕式清洗製程
參考以下結合附圖的說明可明白本揭示內容，其中類似的元件是以相同的元件符號表示。
第1圖的加工流程圖根據背景技術銲料凸塊製程圖示包含形成無鉛銲料凸塊步驟的步驟順序；第1a圖至第1f圖示意圖示概要列於第1圖的製程步驟； 第2圖的加工流程圖根據本發明的一示範具體實施例圖示包含形成無鉛銲料凸塊步驟的步驟順序；以及第2a圖至第2c圖示意圖示概要列於第2圖的一些製程步驟。
儘管本發明容易做成各種修改及替代形式，本文仍以附圖為例圖示幾個本發明的特定具體實施方式且詳述其中的細節。不過，應瞭解本文所描述的特定具體實施方式不是想要把本發明限定成本文所揭示的特定形式，反而是，本發明是要涵蓋落在如隨附申請專利範圍所界定的本發明精神及範疇內的所有修改、等價及替代性陳述。
200‧‧‧半導體裝置
201‧‧‧最後金屬化層
204‧‧‧凸塊下金屬化層
206‧‧‧銲料凸塊
207‧‧‧原生氧化錫層
208‧‧‧銲球
250、255、260‧‧‧步驟
251‧‧‧蝕刻順序
261‧‧‧回銲製程
256‧‧‧濕式清洗製程

Claims (17)

  1. 一種製造積體電路之方法，係包含：形成銲料凸塊於半導體裝置的金屬化層上方；從該銲料凸塊的表面上移除氧化物膜；以及在移除該氧化物膜後，在還原性環境中進行銲料凸塊回銲製程，以回銲該銲料凸塊，其中，移除該氧化物膜包括：進行濕式化學清洗製程，以及其中，進行該濕式化學清洗製程包括：暴露該銲料凸塊的該表面於酸性溶液，該酸性溶液的莫耳濃度約在0.3M至0.5M的範圍內。
  2. 如申請專利範圍第1項所述的方法，其中，在該還原性環境中進行該銲料凸塊回銲製程包括：在包含蟻酸的環境中進行該銲料凸塊回銲製程。
  3. 如申請專利範圍第1項所述的方法，更包括：在移除該氧化物膜之前，暴露該銲料凸塊的該表面於氧化性環境。
  4. 如申請專利範圍第1項所述的方法，其中，進行該濕式化學清洗製程包括：暴露該銲料凸塊的該表面於包含甲基磺酸、蟻酸、硝酸及鹽酸中的一者的酸性溶液。
  5. 如申請專利範圍第1項所述的方法，其中，進行該濕式化學清洗製程包括：暴露該銲料凸塊的該表面於該酸性溶液持續一段約15秒至約330秒的範圍內的時間。
  6. 如申請專利範圍第1項所述的方法，其中，進行該濕式化學清洗製程包括：暴露該銲料凸塊的該表面於包含蟻 酸及鹽酸中的一者的酸性溶液。
  7. 如申請專利範圍第1項所述的方法，其中，進行該濕式化學清洗製程包括：暴露該銲料凸塊的該表面於該酸性溶液持續一段約20秒至約120秒的範圍內的時間。
  8. 一種製造積體電路之方法，係包含：在形成於半導體裝置上方的最後金屬化層上方形成銲料凸塊；暴露該銲料凸塊於含氧環境；暴露該銲料凸塊於濕式化學清洗製程，以實質從該銲料凸塊的該表面移除原生氧化物膜；以及在暴露該銲料凸塊於該濕式化學清洗製程後，在包含蟻酸的回銲環境中回銲該銲料凸塊其中，暴露該銲料凸塊於該濕式化學清洗製程包括：暴露該銲料凸塊的該表面於酸性溶液，該酸性溶液的莫耳濃度約在0.3M至0.5M的範圍內。
  9. 如申請專利範圍第8項所述的方法，其中，在暴露於該含氧環境期間，該原生氧化物膜形成於該銲料凸塊的該表面上。
  10. 如申請專利範圍第8項所述的方法，其中，暴露該銲料凸塊於濕式化學清洗製程包括：暴露該銲料凸塊於包含蟻酸及鹽酸中的一者的酸性溶液。
  11. 如申請專利範圍第10項所述的方法，其中，暴露該銲料凸塊於該濕式化學清洗製程包括：暴露該銲料凸塊的該表面於該酸性溶液持續一段約20秒至約120秒的範 圍內的時間。
  12. 如申請專利範圍第8項所述的方法，更包括：形成附加原生氧化物膜，該附加原生氧化物膜係於暴露該銲料凸塊於該濕式化學清洗製程後形成於該銲料凸塊的該表面上，以及在回銲該銲料凸塊時移除該附加原生氧化物膜。
  13. 如申請專利範圍第8項所述的方法，其中，形成該銲料凸塊包括：由包含錫、銀及銅中的至少一者的實質無鉛材料形成該銲料凸塊。
  14. 如申請專利範圍第13項所述的方法，其中，由實質無鉛材料形成該銲料凸塊包括：由包含錫及約1.8至3.0重量百分比的銀的合金形成該銲料凸塊。
  15. 一種製造積體電路之方法，係包含：在半導體裝置的凸塊下金屬化層上方形成實質無鉛銲料凸塊；進行濕式化學清洗製程，以藉由暴露該銲料凸塊於包含蟻酸及鹽酸中的一者的酸性溶液來從該銲料凸塊的表面移除氧化物膜；以及進行回銲製程，以在包含蟻酸的環境中回銲該銲料凸塊，其中，該酸性溶液的莫耳濃度約在0.3M至0.5M的範圍內。
  16. 如申請專利範圍第15項所述的方法，其中，在該銲料凸塊暴露於含氧環境中時，該氧化物膜形成於該銲料凸 塊的該表面上。
  17. 如申請專利範圍第15項所述的方法，其中，在進行該濕式化學清洗製程之後約12小時內，進行該回銲製程。
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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9142520B2 (en) * 2011-08-30 2015-09-22 Ati Technologies Ulc Methods of fabricating semiconductor chip solder structures
US20130249076A1 (en) 2012-03-20 2013-09-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces
JP5661957B1 (ja) * 2014-01-22 2015-01-28 オリジン電気株式会社 カルボン酸ガス濃度の推定方法及び半田付け装置
CN106536124B (zh) * 2014-08-29 2018-03-20 千住金属工业株式会社 软钎料材料、焊料接头及软钎料材料的制造方法
CN104485293B (zh) * 2014-12-12 2017-08-11 通富微电子股份有限公司 一种提高金属凸块在真空回流工艺中的成球率的方法
DE102015008480B4 (de) * 2015-07-01 2018-07-26 Ika-Werke Gmbh & Co. Kg Dispergiervorrichtung
US10115716B2 (en) * 2015-07-18 2018-10-30 Semiconductor Components Industries, Llc Die bonding to a board
US9847310B2 (en) 2015-07-18 2017-12-19 Semiconductor Components Industries, Llc Flip chip bonding alloys
CN110707013A (zh) * 2019-09-24 2020-01-17 浙江集迈科微电子有限公司 一种电镀法制作大锡球方法
CN113410125B (zh) * 2021-06-03 2023-06-16 抚州华成半导体科技有限公司 Oj型整流二极管酸洗工艺
US11465225B1 (en) * 2021-08-31 2022-10-11 Yield Engineering Systems, Inc. Method of using processing oven
CN115070252B (zh) * 2022-06-22 2023-11-03 四川航天长征装备制造有限公司 一种锁底焊接接头

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080128476A1 (en) * 2006-12-04 2008-06-05 Semiconductor Manufacturing International (Shanghai) Corporation Fluxless Reflow Process for Bump Formation
US20090302469A1 (en) * 2007-10-22 2009-12-10 Naomi Masuda Semiconductor device and method for manufacturing thereof

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5238500A (en) * 1990-05-15 1993-08-24 Semitool, Inc. Aqueous hydrofluoric and hydrochloric acid vapor processing of semiconductor wafers
ATE168820T1 (de) 1990-05-15 1998-08-15 Semitool Inc Vorrichtung zur herstellung von halbleiterschichten mit dynamischer dampfbehandlung und teilchenverflüchtigung
US5404265A (en) * 1992-08-28 1995-04-04 Fujitsu Limited Interconnect capacitors
JP4260405B2 (ja) * 2002-02-08 2009-04-30 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US7319341B1 (en) * 2003-08-28 2008-01-15 Altera Corporation Method of maintaining signal integrity across a capacitive coupled solder bump
US7332424B2 (en) * 2004-08-16 2008-02-19 International Business Machines Corporation Fluxless solder transfer and reflow process
DE102005035772A1 (de) * 2005-07-29 2007-02-01 Advanced Micro Devices, Inc., Sunnyvale Technik zum effizienten Strukturieren einer Höckerunterseitenmetallisierungsschicht unter Anwendung eines Trockenätzprozesses
CN100452335C (zh) 2006-02-24 2009-01-14 中芯国际集成电路制造(上海)有限公司 焊料凸点的无助焊剂制作工艺
KR101030764B1 (ko) 2006-09-29 2011-04-27 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치의 제조 방법 및 제조 장치
WO2009096216A1 (ja) 2008-01-30 2009-08-06 Nec Corporation 電子部品の実装構造、電子部品の実装方法、並びに電子部品実装用基板

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080128476A1 (en) * 2006-12-04 2008-06-05 Semiconductor Manufacturing International (Shanghai) Corporation Fluxless Reflow Process for Bump Formation
US20090302469A1 (en) * 2007-10-22 2009-12-10 Naomi Masuda Semiconductor device and method for manufacturing thereof

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