TWI488244B - 具有凸塊結構的基板及其製造方法 - Google Patents

具有凸塊結構的基板及其製造方法 Download PDF

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Publication number
TWI488244B
TWI488244B TW103125555A TW103125555A TWI488244B TW I488244 B TWI488244 B TW I488244B TW 103125555 A TW103125555 A TW 103125555A TW 103125555 A TW103125555 A TW 103125555A TW I488244 B TWI488244 B TW I488244B
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Taiwan
Prior art keywords
layer
bump
nickel
thickness
copper
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TW103125555A
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English (en)
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TW201604979A (zh
Inventor
Fei Jain Wu
Tsang Sheng Liao
Ching Yi Huang
Chun Te Lee
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Chipbond Technology Corp
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Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Priority to TW103125555A priority Critical patent/TWI488244B/zh
Priority to CN201420500399.5U priority patent/CN204067341U/zh
Priority to CN201410441271.0A priority patent/CN105280508B/zh
Priority to KR1020140113820A priority patent/KR20160012857A/ko
Priority to JP2014182182A priority patent/JP2016032090A/ja
Priority to US14/529,246 priority patent/US9177830B1/en
Priority to SG10201407629YA priority patent/SG10201407629YA/en
Application granted granted Critical
Publication of TWI488244B publication Critical patent/TWI488244B/zh
Publication of TW201604979A publication Critical patent/TW201604979A/zh

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

具有凸塊結構的基板及其製造方法
本發明是關於一種具有凸塊結構的基板及其製造方法，特別是一種具有銅層及鎳層組成凸塊結構的基板，藉由控制鎳層厚度，以使該凸塊結構在退火後的硬度可符合要求。
在覆晶封裝技術中，是在一晶片的一主動面上形成至少一凸塊，再藉由該凸塊使該晶片覆晶結合於一玻璃基板，該凸塊的材質可為金或銅，然由於黃金價格攀升，因此以該凸塊的材質以銅為主流，然由於銅的硬度相較於金的硬度高，因此當該晶片以該銅凸塊覆晶結合於該玻璃基板時，會造成該玻璃基板破裂。
本發明之主要目的在於提供一種具有凸塊結構的基板及其製造方法，其藉由控制形成於一銅層上的一鎳層厚度，以使該銅層與該鎳層所組成的一凸塊結構在退火後，該凸塊結構的硬度可符合要求，其可避免該具有凸塊的基板覆晶結合於一玻璃基板時，造成該玻璃基板的破裂。
本發明之一種具有凸塊結構的基板製造方法，包含提供一半導體基板、形成一凸塊下金屬層、形成一光阻層、圖案化該光阻層、形成一銅層、形成一鎳層、移除該光阻層以及移除該凸塊下金屬層的待移除部，在「提供一半導體基板」的步驟中，該半導體基板具有一本體、至少一導接墊及一保護層，該導接墊形成於該本體，該保護層覆蓋該本體，該保護層具有至少一第一開口，該第一開口顯露出該導接墊，在「形成一凸塊下金屬層」的步驟中，該凸塊下金屬層覆蓋該保護層及該導接墊，該凸塊下金屬層並與該導接墊電性連接，該凸塊下金屬層包含有一待保留部及一待移除部，在「形成一光阻層」的步驟中，該光阻層覆蓋該凸塊下金屬層，在「圖案化該光阻層」的步驟中，經圖案化之該光阻層具有至少一第二開口，該第二開口顯露出該凸塊下金屬層的該待保留部，在「形成一銅層」的步驟中，是在該光阻層的該第二開口中形成該銅層，該銅層與該凸塊下金屬層的該待保留部電性連接，在「形成一鎳層」的步驟中，在該光阻層的該第二開口中形成該鎳層，該鎳層形成於該銅層上方，且該鎳層與該銅層電性連接，該鎳層與該銅層組成一凸塊結構，該鎳層具有一上表面及一下表面，該上表面至該下表面之間的垂直距離為該鎳層的厚度，其中該鎳層的厚度由計算式「H=12.289D+96.674」決定，〝H〞為退火後該凸塊結構硬度，該凸塊結構退火後的硬度單位為〝Hv〞，〝D〞為該鎳層的厚度，該鎳層的厚度單位為〝微米(um)〞，在「移除該光阻層」的步驟中，是顯露出該凸塊下金屬層的該待移除部，最後在「移除該凸塊下金屬層的待移除部」的步驟中，是以該凸塊結構為遮罩，將該凸塊下金屬層的該待移除部移除，僅保留該凸塊下金屬層的該待保留部。
本發明是藉由控制該凸塊結構的鎳層厚度，以使該凸塊結構在退 火後的硬度可符合要求，以避免該具有凸塊的基板覆晶結合於一玻璃基板時，造成該玻璃基板的破裂。
100‧‧‧具有凸塊結構的基板
110‧‧‧半導體基板
111‧‧‧本體
112‧‧‧導接墊
113‧‧‧保護層
114‧‧‧第一開口
120‧‧‧凸塊下金屬層
121‧‧‧待保留部
122‧‧‧待移除部
130‧‧‧光阻層
131‧‧‧第二開口
140‧‧‧銅層
141‧‧‧頂面
142‧‧‧底面
150‧‧‧鎳層
151‧‧‧上表面
152‧‧‧下表面
160‧‧‧接合層
200‧‧‧玻璃基板
210‧‧‧接點
A‧‧‧凸塊結構
D‧‧‧鎳層的厚度
D1‧‧‧銅層的厚度
H‧‧‧凸塊結構退火後硬度
第1A至1H圖：本發明具有凸塊結構的基板製造方法的步驟剖視圖。
第2圖：本發明具有凸塊結構的基板覆晶結合於一玻璃基板的剖視圖。
請參閱第1A至1H圖，其揭露一種具有凸塊結構的基板製造方法，其包含第1A圖的「提供一半導體基板」步驟、第1B圖的「形成一凸塊下金屬層」步驟、第1C圖的「形成一光阻層」步驟、第1D圖的「圖案化該光阻層」步驟、第1E圖的「形成一銅層」步驟、第1F圖的「形成一鎳層」步驟、第1G圖的「移除該光阻層」步驟，以及第1H圖的「移除該凸塊下金屬層的待移除部」步驟。
首先，請參閱第1A圖，在「提供一半導體基板」步驟中，該半導體基板110具有一本體111、至少一導接墊112及一保護層113，該導接墊112形成於該本體111，該保護層113覆蓋該本體111，該保護層113具有至少一第一開口114，該第一開口114顯露出該導接墊112，該導接墊112可選自於銅(Cu)、鋁(Al)、銅合金、或其他導電材料。
接著，請參閱第1B圖，在「形成一凸塊下金屬層」步驟中，該凸塊下金屬層120覆蓋該保護層113及該導接墊112，該凸塊下金屬層120並與該導接墊112電性連接，該凸塊下金屬層120包含有一待保留部121及一待移除部 122，該待保留部121連接該導接墊112。
接著，請參閱第1C圖，在「形成一光阻層」步驟中，該光阻層130覆蓋該凸塊下金屬層120。該光阻層130可選自於正光阻膜或為負光阻膜，該光阻層130可經由塗佈及固化(curing)等步驟形成該凸塊下金屬層120上。
接著，請參閱第1D圖，在「圖案化該光阻層」步驟中，以微影技術、蝕刻技術(乾蝕刻製程或濕蝕刻製程)圖案化該光阻層130，經圖案化之該光阻層130具有至少一第二開口131，該第二開口131顯露出該凸塊下金屬層120的該待保留部121。
接著，請參閱第1E圖，在「形成一銅層」步驟中，以電鍍、無電電鍍、印刷、濺鍍或化學氣相沈積(CVD)法，在該光阻層130的該第二開口131中形成該銅層140，該銅層140具有一頂面141及一底面142，該銅層140與該凸塊下金屬層120的該待保留部121電性連接，在本實施例中，該銅層140的該底面142接觸該凸塊下金屬層120的該待保留部121。
接著，請參閱第1F圖，在「形成一鎳層」步驟中，可選擇以電鍍、無電電鍍、印刷、濺鍍或化學氣相沈積(CVD)法，在該光阻層130的該第二開口131中形成該鎳層150，該鎳層150形成於該銅層140上方，且該鎳層150與該銅層140電性連接，在本實施例中該鎳層150接觸該銅層140的該頂面141，該鎳層150與該銅層140組成一凸塊結構A，在形成該鎳層150的步驟中，該鎳層150的厚度由計算式「H=12.289D+96.674」決定，其中〝H〞為退火後該凸塊結構硬度，〝D〞為該鎳層150的厚度，該凸塊結構A退火後的硬度單位為〝Hv〞，該鎳層150具有一上表面151及一下表面152，該上表面151至該下表面152之間的垂直距離為該鎳層150的厚度D，該鎳層150的厚度單位為〝微米(um)〞。
請再請參閱第1F圖，在「形成一鎳層」步驟中，若欲使退火後凸塊結構A的硬度達到使用者需求，可藉由計算式「H=12.289D+96.674」控制該鎳層150的厚度D，其可避免生產者於形成該鎳層150時，因該鎳層150厚度不足或厚度太厚，而影響退火後凸塊結構A的硬度無法達到使用者需求的問題，且可避免以猜測方式決定該鎳層150的厚度後，造成退火後凸塊結構A的硬度無法控制的問題，此外，該銅層140的該頂面141及該底面142之間的垂直距離為該銅層140的厚度D1，較佳地，該銅層140的厚度D1不小於該鎳層150的厚度D。
請再請參閱第1F圖，在本實施例中，其中在形成該鎳層150後，可選擇以電鍍、無電電鍍、印刷、濺鍍或化學氣相沈積(CVD)法，在該光阻層130的該第二開口131中形成一接合層160，該接合層160形成於該鎳層150的該上表面151，該接合層160可選自於含金(Au)、錫(Sn)、錫鉛(SnPb)、銀(Ag)、或其他相似的材料。
接著請參閱第1G圖，在「移除該光阻層」步驟中，該光阻層130被移除，以顯露出該凸塊下金屬層120的該待移除部122。
最後，請參閱第1H圖，在「移除該凸塊下金屬層的待移除部」步驟中，是以該凸塊結構A為遮罩，將該凸塊下金屬層120的該待移除部122移除，僅保留該凸塊結構A下的該待保留部121，以形成一具有凸塊結構的基板100。
請參閱第2圖，將該具有凸塊結構的基板100覆晶接合於一包含有至少一接點210的玻璃基板200上，由於該凸塊結構A的該鎳層150的厚度由計算式「H=12.289D+96.674」決定該凸塊結構A退火後的硬度，因此可避免該具有凸塊結構的基板100覆晶接合於該玻璃基板200時，因該凸塊結構A退火後的硬度不符合該玻璃基板200的需求，而造成該玻璃基板200在覆晶接合時破裂。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
100‧‧‧具有凸塊結構的基板
110‧‧‧半導體基板
111‧‧‧本體
112‧‧‧導接墊
113‧‧‧保護層
114‧‧‧第一開口
121‧‧‧待保留部
140‧‧‧銅層
150‧‧‧鎳層
160‧‧‧接合層
200‧‧‧玻璃基板
210‧‧‧接點

Claims (6)

  1. 一種具有凸塊結構的基板製造方法，包含：提供一半導體基板，該半導體基板具有一本體、至少一導接墊及一保護層，該導接墊形成於該本體，該保護層覆蓋該本體，該保護層具有至少一第一開口，該第一開口顯露出該導接墊；形成一凸塊下金屬層，該凸塊下金屬層覆蓋該保護層及該導接墊，該凸塊下金屬層並與該導接墊電性連接，該凸塊下金屬層包含有一待保留部及一待移除部；形成一光阻層，該光阻層覆蓋該凸塊下金屬層；圖案化該光阻層，經圖案化之該光阻層具有至少一第二開口，該第二開口顯露出該凸塊下金屬層的該待保留部；形成一銅層，在該光阻層的該第二開口中形成該銅層，該銅層與該凸塊下金屬層的該待保留部電性連接；形成一鎳層，在該光阻層的該第二開口中形成該鎳層，該鎳層形成於該銅層上方，且該鎳層與該銅層電性連接，該鎳層與該銅層組成一凸塊結構，該鎳層具有一上表面及一下表面，該上表面至該下表面之間的垂直距離為該鎳層的厚度，其中該鎳層的厚度由計算式「H=12.289D+96.674」決定，〝H〞為退火後該凸塊結構硬度，該凸塊結構退火後的硬度單位為〝Hv〞，〝D〞為該鎳層的厚度，該鎳層的厚度單位為〝微米(um)〞；移除該光阻層，以顯露出該凸塊下金屬層的該待移除部；以及移除該凸塊下金屬層的該待移除部，以該凸塊結構為遮罩，將該凸塊下金屬層的該待移除部移除，僅保留該凸塊下金屬層的該待保留部。
  2. 如申請專利範圍第1項所述之具有凸塊結構的基板製造方法，其中該銅層具有一頂面及一底面，該頂面至該底面之間的垂直距離為該銅層的厚度，其中該銅層的厚度不小於該鎳層的厚度。
  3. 如申請專利範圍第1項所述之具有凸塊結構的基板製造方法，其中在形成一鎳層的步驟後及在移除該光阻層前，在該光阻層的該第二開口中形成一接合層，且該接合層形成於該鎳層的該上表面。
  4. 一種具有凸塊結構的基板，其中凸塊結構具有一預定的退火後硬度，該具有凸塊結構的基板包含：一半導體基板，具有一本體、至少一導接墊及一保護層，該導接墊形成於該本體，該保護層覆蓋該本體，該保護層具有至少一第一開口，該第一開口顯露出該導接墊；一凸塊下金屬層，電性連接該導接墊；以及一凸塊結構，包含一銅層及一鎳層，該銅層位於該凸塊下金屬層與該鎳層之間，該銅層與該凸塊下金屬層電性連接，該鎳層具有一上表面及一下表面，該上表面至該下表面之間的垂直距離為該鎳層的厚度，其中該鎳層的厚度由計算式「H=12.289D+96.674」決定，該凸塊結構退火後硬度為〝H〞，該凸塊結構退火後的硬度單位為〝Hv〞，該鎳層的厚度為〝D〞，該鎳層的厚度單位為〝微米(um)〞。
  5. 如申請專利範圍第4項所述之具有凸塊結構的基板，其中該銅層具有一頂面及一底面，該頂面至該底面之間的垂直距離為該銅層的厚度，其中該銅層的厚度不小於該鎳層的厚度。
  6. 如申請專利範圍第4項所述之具有凸塊結構的基板，其另包含一接合層 ，該接合層形成於該鎳層的該上表面。
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CN107481988B (zh) * 2017-07-28 2020-09-01 永道无线射频标签(扬州)有限公司 一种未使用导电胶的覆晶芯片封装产品及其制作工艺
US10692830B2 (en) * 2017-10-05 2020-06-23 Texas Instruments Incorporated Multilayers of nickel alloys as diffusion barrier layers
US11127704B2 (en) 2017-11-28 2021-09-21 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with bump structure and method of making semiconductor device
TW201930646A (zh) * 2018-01-05 2019-08-01 頎邦科技股份有限公司 具凸塊結構之半導體裝置及其製造方法
CN110310939B (zh) * 2018-03-27 2021-04-30 矽品精密工业股份有限公司 基板结构及其制法及导电凸块

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201138040A (en) * 2010-04-22 2011-11-01 Taiwan Semiconductor Mfg Integrated circuit devices and method of forming a bump structure
JP2013042005A (ja) * 2011-08-17 2013-02-28 Sony Corp 半導体装置、半導体装置の製造方法、及び、電子機器
US20130228918A1 (en) * 2012-03-05 2013-09-05 Yi-An Chen Three-dimensional integrated circuit which incorporates a glass interposer and method for fabricating the same
TW201413900A (zh) * 2012-09-18 2014-04-01 Taiwan Semiconductor Mfg Co Ltd 凸塊導線直連結構與其形成方法、晶片對晶片結構
TWM490108U (en) * 2014-07-25 2014-11-11 Chipbond Technology Corp Substrate with bump structure

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0797587B2 (ja) * 1987-03-12 1995-10-18 株式会社東芝 半導体装置の製造方法
JP2000323510A (ja) * 1999-05-11 2000-11-24 Shinko Electric Ind Co Ltd 柱状電極付き半導体ウエハ及びその製造方法並びに半導体装置
JP2003037129A (ja) * 2001-07-25 2003-02-07 Rohm Co Ltd 半導体装置およびその製造方法
TWI252546B (en) 2004-11-03 2006-04-01 Advanced Semiconductor Eng Bumping process and structure thereof
JP2007287906A (ja) * 2006-04-17 2007-11-01 Elpida Memory Inc 電極と電極の製造方法、及びこの電極を備えた半導体装置
US8269345B2 (en) 2007-10-11 2012-09-18 Maxim Integrated Products, Inc. Bump I/O contact for semiconductor device
TW201019440A (en) 2008-11-03 2010-05-16 Int Semiconductor Tech Ltd Bumped chip and semiconductor flip-chip device applied from the same
US8736050B2 (en) 2009-09-03 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Front side copper post joint structure for temporary bond in TSV application
US8592995B2 (en) * 2009-07-02 2013-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for adhesion of intermetallic compound (IMC) on Cu pillar bump
US8659155B2 (en) 2009-11-05 2014-02-25 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps
US8546254B2 (en) 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
TW201227898A (en) 2010-12-24 2012-07-01 Unimicron Technology Corp Package substrate and fabrication method thereof
TWI440150B (zh) 2011-05-20 2014-06-01 Chipbond Technology Corp 凸塊製程及其結構
CN102800599B (zh) 2011-05-25 2015-03-25 颀邦科技股份有限公司 凸块工艺及其结构
US9978656B2 (en) 2011-11-22 2018-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming fine-pitch copper bump structures
JP6076020B2 (ja) 2012-02-29 2017-02-08 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
TWI488244B (zh) * 2014-07-25 2015-06-11 Chipbond Technology Corp 具有凸塊結構的基板及其製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201138040A (en) * 2010-04-22 2011-11-01 Taiwan Semiconductor Mfg Integrated circuit devices and method of forming a bump structure
JP2013042005A (ja) * 2011-08-17 2013-02-28 Sony Corp 半導体装置、半導体装置の製造方法、及び、電子機器
US20130228918A1 (en) * 2012-03-05 2013-09-05 Yi-An Chen Three-dimensional integrated circuit which incorporates a glass interposer and method for fabricating the same
TW201413900A (zh) * 2012-09-18 2014-04-01 Taiwan Semiconductor Mfg Co Ltd 凸塊導線直連結構與其形成方法、晶片對晶片結構
TWM490108U (en) * 2014-07-25 2014-11-11 Chipbond Technology Corp Substrate with bump structure

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