TWI475614B - 溝渠裝置結構及製造 - Google Patents

溝渠裝置結構及製造 Download PDF

Info

Publication number
TWI475614B
TWI475614B TW098110268A TW98110268A TWI475614B TW I475614 B TWI475614 B TW I475614B TW 098110268 A TW098110268 A TW 098110268A TW 98110268 A TW98110268 A TW 98110268A TW I475614 B TWI475614 B TW I475614B
Authority
TW
Taiwan
Prior art keywords
semiconductor material
gate
layer
conductivity type
trench
Prior art date
Application number
TW098110268A
Other languages
English (en)
Other versions
TW201032278A (en
Inventor
Richard A Blanchard
Jun Zeng
Original Assignee
Maxpower Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Maxpower Semiconductor Inc filed Critical Maxpower Semiconductor Inc
Publication of TW201032278A publication Critical patent/TW201032278A/zh
Application granted granted Critical
Publication of TWI475614B publication Critical patent/TWI475614B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/086—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/408—Electrodes ; Multistep manufacturing processes therefor with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)

Description

溝渠裝置結構及製造
本申請案係關於半導體裝置，且更特定言之，係關於溝渠裝置結構及製造。
現今製造的溝渠MOSFET(metal oxide semiconductor field effect transistor；金氧半導體場效電晶體)裝置使其源極區係藉由植入所需摻雜物物種來形成。
應注意，下文論述的觀點可反映自所揭示發明獲得的事後之見，且不必承認係先前技術。
參考圖1，顯示一垂直DMOS(diffusion metal oxide semiconductor；擴散金氧半導體)電晶體。此圖係來自美國專利第5,663,079號，其係以引用方式併入本申請案中。閘極區12係形成於一閘極介電層17內。p-本體區18係擴散至epi(epitaxial；磊晶)層(或基板)10中。沈積一第二多晶矽層11。該第二多晶矽層11係使用磷、砷或銻摻雜之N型。
二氧化矽層19係沈積於該多晶矽11與該矽基板10之曝露部分上。該第二多晶矽層11中的n型摻雜物形成擴散的n型源極區14。p型摻雜物係引入並擴散至所需深度形成p+區16，其係顯示為比p-本體區18淺，但可以係與p-本體區18一樣深或比其深。分離的接觸區13、15係透過絕緣層19敞開至該多晶矽層以電接觸該源極區14。此結構允許至該源極多晶矽之接觸係離該矽中之擴散的源極區一距離進行。
一種溝渠閘極式MOSFET包括一溝渠，其含有在其底部上及至少部分地在其側上之一介電層。此介電層(其向下延伸至第一傳導性類型半導體材料)將此第一傳導性類型半導體材料與該閘極導體分離，該閘極導體可以係多晶矽、一多晶矽化金屬或一矽化物。一磷矽酸鹽玻璃層係定位於該導電閘極材料之上並且一摻雜磷的多晶矽層係定位於該磷矽酸鹽玻璃層之上。相反傳導性類型之源極與本體擴散係鄰近該溝渠之一側壁予以定位。一漂移區係定位以接收已藉由該源極注入的多數載流子，並且其已通過該本體擴散。一汲極區係定位以接收已通過該漂移區的多數載流子。該閘極係電容性耦合至該半導體材料以控制該本體擴散之一部分的反轉。作為一替代，可使用一介電層取代該摻雜玻璃，其中永久或固定電荷係定位於該介電層中。
在各種具體實施例中，所揭示創新提供至少以下優點之一或多者。然而，並非所有此等優點係得自所揭示創新之每一者，並且此優點清單並不限制各種主張發明。
‧實現一DMOS結構，該DMOS結構使其源極接點在該溝渠側壁上。
‧實現DMOS電晶體之製造，該等DMOS電晶體具有一更小間距或單元大小並因此具有一更低的每單位面積之開啟電阻。
將參考當前較佳具體實施例來說明本申請案之許多創新 教導(經由舉例而非限制)。本申請案說明數個發明，並且一般而言下文陳述無一應係視為限制申請專利範圍。
揭示一溝渠MOSFET結構與程序，其使其源極摻雜物係自摻雜多晶矽透過該溝渠之側壁引入。此外，可選擇該本體區中的摻雜物濃度以使得該裝置之崩潰電壓係藉由遠離該通道區的本體區中之淨摻雜物濃度來設定。下文在圖式中顯示該程序流程與所得結構。
以下說明係關於一n通道裝置。針對一p通道裝置，顛倒傳導性類型。
參考圖2至8，斷面結構圖繪示依據一具體實施例的一裝置製程中之階段。如圖2所示，在一N+晶圓102上沈積一n型磊晶層104。沈積一p型磊晶層106或引入一p型摻雜物。(為簡單起見，僅顯示一個p型本體區。熟習此項技術者知道可形成額外p或p+區，其具有比橫跨該第一p型區之部分或全部的第一本體淺、與其一樣深或比其深的分佈)。在該晶圓表面上形成一介電層或夾層107。可使用一遮罩來蝕刻溝渠110。形成一閘極氧化物或介電夾層108。雖然可藉由一種以上程序來形成該介電層108，但可能不能區分在該等溝渠之頂部邊角處的氧化物之間的任何邊界。
在圖3中，藉由沈積多晶矽來填充該等溝渠110。接著各向異性地蝕刻該多晶矽以留下一多晶矽閘極電極112。(將自此圖式之平面向外進行至該多晶矽閘極之接觸，故在該等圖式中不顯示此接觸所需之結構。)
在圖4中，已如層108之上部部分移除圖2中的介電夾層107之上部層(亦可僅使層108變薄)。
在圖5中，已藉由類似於用以形成閘極電極112之該沈積與蝕刻程序的一沈積與蝕刻程序來在該閘極112之上形成諸如磷矽酸鹽玻璃(PSG)111的含有一n型摻雜物之一摻雜氧化物層。
在圖6中，再次藉由類似於用以形成該閘極電極之該沈積與蝕刻程序的一沈積與蝕刻程序已在PSG層111之上形成一摻雜磷、摻雜砷或摻雜銻多晶矽層113。該摻雜多晶矽之頂部可在該矽表面之下、該矽表面處或該矽表面之上。
在圖7中，使用一熱擴散程序，透過該等溝渠壁在該本體區106中形成來自該多晶矽113之一更重摻雜的N+擴散115與來自該摻雜氧化物膜PSG 111之一N擴散117。
在圖8中，於該本體區106之頂部處植入(或以其他方式形成)一P+層119。
參考圖9，顯示一超高密度場效電晶體之模擬斷面。
參考圖10，一圖表繪示沿圖9之A-A'線的摻雜分佈。
參考圖11，顯示一超高密度場效電晶體之額外模擬資料。
參考圖12，顯示一繪示具有一N型輕摻雜擴散(LDD)228之單元結構。依據一具體實施例，此斷面結構圖繪示一超高密度場效電晶體。一汲極區202鄰接一漂移區204。顯示一絕緣溝渠208係形成而具有一導電閘極212，其頂部上具有磷矽酸鹽玻璃(PSG)。一閘極介電層接觸一LDD 228、一本體206及該漂移區204。一閘極電極212係定位於該絕緣溝渠208內以在該本體206內產生一反轉層而在源極226與該漂移區204之間建立一電荷流。一本體接觸區220提供該源極226與本體206之間的連接。一多晶矽層214提供至該源極226與該金屬化層218之連接。圖13繪示一類似單元結構，其不具有該N型輕摻雜擴散。
參考圖14，依據一具體實施例，一斷面結構圖繪示一超高密度場效電晶體。一汲極區202鄰接一漂移區204。一絕緣溝渠208係由一介電層形成，其接觸一LDD 228、一本體206及該漂移區204。一閘極電極212係定位於該絕緣溝渠208內以在該本體206內產生一反轉層，從而允許載流子在源極226與該漂移204之間流動。一第二電極210係定位於該絕緣溝渠208內並通常係連接至該源極226。一本體接觸區220提供該源極226與本體206之間的連接。一多晶矽或多晶矽化金屬層214提供至該源極226與該金屬化層218之連接。
圖15顯示類似於圖14之具體實施例的一具體實施例，在該閘極212上具有一多晶矽化金屬層230。
圖16顯示類似於圖14之具體實施例的一具體實施例，不具有該第二閘極電極210。
圖17(a)顯示包括自該閘極212與一從下面露出的源極226延伸的於由諸如氧化物之介電材料形成之一絕緣溝渠207的表面處之永久電荷222的一具體實施例。此永久電荷222在該本體之鄰近區中形成一感應反轉層。圖17(b)顯示類似於圖17(a)之一具體實施例，其中該絕緣溝渠207延伸至該漂移區204中。圖17(c)顯示類似於圖17(b)之一具體實施例，其包括一分離閘極212與210。
對於最大密度而言，需要一較小本體接觸面積。可藉由在源極擴散期間保持該摻雜多晶矽遠離該台面之頂部來獲得此小本體接觸面積。此目標係藉由蝕刻該n型摻雜多晶矽使其低於該半導體之表面來完成，如圖6中之虛線所示。摻雜多晶矽與矽玻璃係n+側壁摻雜物來源，其產生極高的密度。可在該PSG層或一氮氧化物之下使用一密封物氧化物。砷矽酸鹽、n型鍺矽酸鹽或銻矽酸鹽玻璃或該等玻璃之混合物係對該PSG之替代物。
該等圖式顯示一離散溝渠MOSFET之製造。亦考慮作為一積體電路之部分的此等裝置之製造。
依據各種具體實施例，提供：一種用於製造一垂直電流場效電晶體之一方法，其包含以下動作：在半導體材料之一本體中形成至少一溝渠；在該至少一溝渠內形成一閘極電極，其中藉由一絕緣材料將該半導體材料與該閘極電極分離；在該閘極電極之上形成一摻雜玻璃層；以及在該摻雜矽玻璃層之上形成一摻雜多晶矽材料層。
依據各種具體實施例，提供：一垂直電流裝置，其包括一溝渠，該溝渠包括一絕緣閘極並且向下延伸至第一傳導性類型半導體材料中。一摻雜玻璃層係定位於該絕緣閘極之上並且一摻雜多晶矽層係定位於該摻雜玻璃層之上。相反傳導性類型之源極與本體擴散係鄰近該溝渠之一側壁予以定位。一漂移區係定位以接收已藉由該源極注入的多數載流子，並且其已通過該本體擴散。一汲極區係定位以接收已通過該漂移區的多數載流子。該閘極係電容性耦合以控制該本體區之一部分的反轉。
依據各種具體實施例，提供：一垂直電流裝置，其包含：一溝渠，其包括一絕緣閘極；一摻雜玻璃層，其在該絕緣閘極之上；以及一摻雜多晶矽層，其在該摻雜玻璃層之上。
依據各種具體實施例，提供：一垂直電流裝置，其包含：一溝渠，其包括一絕緣閘極；一介電層(例如氧化物)，其在該絕緣閘極之上；一摻雜玻璃層，其在該介電層之上；以及一摻雜多晶矽層，其在該摻雜玻璃層之上。
依據各種具體實施例，提供：操作一垂直電流半導體裝置之一方法，其包含以下動作：使用一溝渠中之一絕緣閘極來控制一本體擴散之反轉，該溝渠含有一摻雜玻璃層與一摻雜多晶矽層；在一漂移區中，接收已藉由一源極注入的多數載流子，並且其已通過該本體擴散；以及在一汲極區中，接收已通過該漂移區的多數載流子；其中該閘極係電容性地耦合以控制該本體區之一部分的反轉。
依據各種具體實施例，提供：一高密度垂直電流裝置，其包含：一溝渠，其包括一絕緣閘極；一介電材料層(例如，氧化物)，其在該絕緣閘極之上；永久電荷，其於鄰近該介電層之矽表面處形成一反轉層；以及一摻雜多晶矽層，其在該介電層之上。
依據各種具體實施例，提供：一高密度垂直電力裝置，其包含：至少一主動裝置區域；至少一埋入式閘極電極，其在該主動裝置區域內之一圖案化溝渠中，其係電容性地耦合以在位於該溝渠旁邊之一源極與位於該溝渠之下之一汲極之間控制通過鄰近該埋入式閘極電極之至少部分的半導體材料之垂直電流；以及至少一埋入式源極接觸電極，其在該圖案化溝渠中，其接觸該源極；其中該埋入式閘極電極與該埋入式源極接觸電極具有與該等主動裝置區域內相同但在別處不同的圖案。
修改與變更
熟習此項技術者將認識到，可在一極大的應用範圍內修改與改變本申請案中說明的創新概念，並因此專利標的之範疇並不受所提供的特定範例性教示之任一者限制。旨在涵蓋在隨附申請專利範圍之精神與廣泛範疇內的所有此類替代、修改及變更。
視需要地，可作為替代使用其他半導體材料，例如矽-鍺；鍺、碳、銀及任何其他適合的材料。
針對另一範例，可視需要地使用對源極幾何形狀之其他修改，包括摻雜物密度之額外分級及/或額外植入物。
針對另一範例，可視需要地使用對汲極幾何形狀之其他修改，包括(例如)場板、摻雜物密度之額外分級(例如，由於一磷與砷雙物種源極擴散所致)、額外植入物及/或於該汲極之半導體表面處以調整表面傳導的永久電荷。
針對另一範例，可視需要地使用一雙閘極結構，例如其中一下部閘極端子具有一更厚氧化物並係連接至源極電壓，並在該切換閘極112下面。結合在該溝渠之下部部分上具有更厚氧化物的具體實施例，此可尤其有利，如(例如)圖16之外部範例所示。此亦可協作地結合一溝渠閘極，其係接近其底部邊角畫出輪廓，或具有永久電荷以修改傳導。
如所熟知，在垂直DMOS技術之領域中，一裝置之起伏性係藉由深P+區來改良，該等區在任何其他崩潰機制發生之前達到突崩崩潰。在一些實例中，此P+區係包括於由單元構成之一裝置中的每一單元中，而在其他實例中，此P+區係包括於每一第n個單元中。在一交叉結構中，可沿該源極之整個長度包括該P+區，或可每幾微米存在該P+區。
此發明揭示內容中未論述該裝置之邊緣終端。然而，如所熟知，該裝置必須係藉由一終端結構包圍，該終端結構於大於該裝置內部中的崩潰之一電壓進入電壓崩潰狀態。此要求允許在崩潰中發生的電流直接流向該等端子，從而最小化會損壞該裝置的可能性。
以下申請案可含有額外資訊與替代修改：代理人檔案號碼MXP-15P，2008年6月2日申請的序號第61/058,069號，且標題為「針對含有永久電荷之裝置的邊緣終端(Edge Termination for Devices Containing Permanent Charge)」；代理人檔案號碼MXP-16P，2008年6月11日申請的序號第61/060,488號，且標題為「MOSFET開關(MOSFET Switch)」；代理人檔案號碼MXP-17P，2008年6月20日申請的序號第61/074,162號，且標題為「MOSFET開關(MOSFET Switch)」；代理人檔案號碼MXP-18P，2008年6月30日申請的第61/076,767號，且標題為「溝渠閘極電力裝置(Trench-Gate Power Device)」；代理人檔案號碼MXP-19P，2008年7月15日申請的序號第61/080,702號，且標題為「MOSFET開關(A MOSFETS witch)」；代理人檔案號碼MXP-20P，2008年7月30日申請的序號第61/084,639號，且標題為「含有永久電荷之橫向裝置(Lateral Devices Containing Permanent Charge)」；代理人檔案號碼MXP-21P，2008年7月30日申請的序號第61/084,642號，且標題為「含有永久電荷之絕緣物上矽裝置(Silicon on Insulator Devices Containing Permanent Charge)」；代理人檔案號碼MXP-22P，2008年2月11日申請的序號第61/027,699號，且標題為「在溝渠側壁中使用永久電荷以製造無閘極電流源、閘極電流源及肖特基二極體(Use of Permanent Charge in Trench Sidewalls to Fabricate Un-Gated Current Sources,GateCurrent Sources,and Schottky Diodes)」；代理人檔案號碼MXP-14P，2008年4月29日申請序號的第61/125,892號，且標題為「針對具有次微米接面深度之PN接面的邊緣終端(Edge Termination for PN Junction Having Sub-Micron Junction Depth)」；代理人檔案號碼MXP-24P，2008年2月14日申請的序號第61/028,783號，且標題為「用於引入與調整一溝渠MOSFET中之摻雜物分佈以獲得改良裝置特性的技術(Techniques for Introducing and Adjusting the Dopant Distribution in a Trench MOSFET to Obtain Improved Device Characteristics)」；代理人檔案號碼MXP-25P，2008年8月25日申請的序號第61/091,442號，且標題為「含有永久電荷之裝置(Devices Containing Permanent Charge)」；代理人檔案號碼MXP-26P，2008年7月7日申請的序號第61/134,149號，且標題為「具有電荷感應接面之半導體裝置(Semiconductor Devices Having Charge Induced Junctions)」；代理人檔案號碼MXP-27P，2008年12月1日申請的序號第61/118,664號，且標題為「改良功率MOSFET及其邊緣終端(An Improved Power MOSFET and Its Edge Termination)」；代理人檔案號碼MXP-28P，2008年12月16日申請的序號第61/122,794號，且標題為「電力MOSFET電晶體(A Power MOSFET Transistor)」。
本申請案中之說明無一應係讀取為暗示任何特定元件、步驟或功能係必須包括於以下申請專利範圍範疇中之一基本元件：專利標的之範疇僅係藉由允許的請求項來定義。此外，除非確切詞語「用於...之構件」係跟隨一分詞，此等請求項無一旨在引用35 USC第112章之第六段。
所歸檔的申請案旨在儘可能綜合，並且無標的係有意放棄、專用或廢止。
10．．．Epi(磊晶)層/矽基板
11．．．第二多晶矽層
12．．．閘極區
13．．．接觸區
14．．．擴散的n型源極區
15．．．接觸區
16．．．所需深度形成p+區
17．．．閘極介電層
18．．．P本體區
19．．．二氧化矽層/絕緣層
102．．．N+晶圓
104．．．n型磊晶層
106．．．p型磊晶層
107．．．介電層或夾層
108．．．閘極氧化物或介電夾層/介電層
110．．．溝渠
111．．．磷矽酸鹽玻璃(PSG)
112．．．多晶矽閘極電極
113．．．摻雜磷、摻雜砷或摻雜銻多晶矽層
115．．．更重摻雜的N+擴散
117．．．N擴散
119．．．P+層
202．．．汲極區
204．．．漂移區
206．．．本體
207．．．絕緣溝渠
208．．．絕緣溝渠
210．．．第二閘極電極
212．．．導電閘極
214．．．多晶矽層
218．．．金屬化層
220．．．本體接觸區
222．．．永久電荷
226．．．源極
228．．．N型輕摻雜擴散(LDD)
230．．．多晶矽化金屬層
已參考附圖說明所揭示發明，該等附圖顯示本發明之重要樣本具體實施例並係以引用方式併入其說明書中，其中：圖1係使其源極摻雜物係自一摻雜多晶矽層擴散的一垂直DMOS電晶體之一斷面圖；
圖2係依據一具體實施例繪示的針對一半導體裝置之一製程中的一階段之一斷面結構圖；
圖3係依據一具體實施例繪示的針對一半導體裝置之一製程中的一階段之一斷面結構圖；
圖4係依據一具體實施例繪示的針對一半導體裝置之一製程中的一階段之一斷面結構圖；
圖5係依據一具體實施例繪示的針對一半導體裝置之一製程中的一階段之一斷面結構圖；
圖6係依據一具體實施例繪示的針對一半導體裝置之一製程中的一階段之一斷面結構圖；
圖7係依據一具體實施例繪示的針對一半導體裝置之一製程中的一階段之一斷面結構圖；
圖8係依據一具體實施例繪示的針對一半導體裝置之一製程中的一階段之一斷面結構圖；
圖9係依據一具體實施例繪示的針對一半導體裝置之一製程中的一階段之一斷面結構圖；
圖10係依據一具體實施例的一超高密度FET上的模擬資料之一圖表；
圖11係依據一具體實施例的一摻雜分佈之一圖表；
圖12係繪示依據一具體實施例的具有一n型輕摻雜擴散(N-LDD)之一單元結構的一斷面結構圖；
圖13係繪示依據一具體實施例的不具有一n型輕摻雜擴散(N-LDD)之一單元結構的一斷面結構圖；
圖14係繪示依據一具體實施例之一分離閘極的一斷面結構圖；
圖15係繪示依據一具體實施例的具有多晶矽化金屬之一分離閘極的一斷面結構圖；
圖16係繪示依據一具體實施例之一BOX(buried oxide；埋入式氧化物)閘極的一斷面結構圖；
圖17(a)係繪示依據一具體實施例的其中固定或永久電荷提供一反轉表面以用於載流子傳導之一裝置的一斷面結構圖；
圖17(b)係繪示依據一具體實施例的具有一較厚底部氧化物且其中固定電荷提供一反轉表面以用於載流子傳導之一裝置的一斷面結構圖；以及
圖17(c)係繪示依據一具體實施例的其中固定電荷提供一反轉表面以用於載流子傳導之一分離閘極裝置的一斷面結構圖。
102．．．N+晶圓
104．．．n型磊晶層
106．．．p型磊晶層
108．．．閘極氧化物或介電夾層
111．．．磷矽酸鹽玻璃(PSG)
112．．．多晶矽閘極電極
113．．．摻雜磷、摻雜砷或摻雜銻多晶矽層
115．．．更重摻雜的N+擴散
117．．．N擴散
119．．．P+層

Claims (12)

  1. 一種垂直電流裝置，其包含：一溝渠，延伸進入一半導體材料之中，包括一絕緣閘極；一介電層，其包含一半導體材料之第一傳導性類型之摻雜物，在該絕緣閘極之上；及在該半導體材料中之第一及第二傳導性類型之源極與本體擴散，其鄰近該溝渠之側壁中之至少之一；在該半導體材料中之一漂移區，其係定位以接收已藉由該源極注入的多數載流子，並且該等多數載流子已通過該本體擴散；在該半導體材料中之該第一傳導性類型之一汲極區，其係定位以接收已通過該漂移區的多數載流子；該第一傳導性類型之一輕摻雜擴散，在該半導體材料之中，自行向該介電層對齊；及一摻雜多晶矽層，其在該介電層之上。
  2. 如請求項1之垂直電流裝置，其中該絕緣閘極係一分離閘極。
  3. 如請求項2之垂直電流裝置，其中該絕緣閘極包括一多晶矽層。
  4. 如請求項1之垂直電流裝置，其進一步包含在該介電層中之永久電荷。
  5. 一種操作一垂直電流半導體裝置的方法，其包含以下動作： 使用一溝渠中之一絕緣閘極來控制一本體在一半導體材料中擴散之反轉，該溝渠包括一玻璃層與一摻雜多晶矽層；在該半導體材料中之一漂移區中，接收已藉由一第一傳導性類型之源極注入的多數載流子，並且該等多數載流子已通過該本體擴散且通過自行向該玻璃層對齊之輕摻雜第一傳導性類型區域；及在該半導體材料中之一第一傳導性類型汲極區中，接收已通過該漂移區的多數載流子；其中該本體擴散具有一第二傳導性類型，且該閘極係電容性耦合以控制該本體擴散之一部分的反轉；其中該玻璃層含有一為該半導體材料之第一傳導性類型摻雜物之物種，且其在該半導體材料中，在該源極與該本體擴散之間，形成一輕摻雜之第一傳導性類型擴散；且其中該摻雜之多晶矽層亦包含一為該半導體材料之一第一傳導性類型摻雜物之物種。
  6. 如請求項5之方法，其中該等多數載流子係電子。
  7. 如請求項5之方法，其中該絕緣閘極係一分離閘極。
  8. 如請求項5之方法，其進一步包含在該玻璃層中之永久電荷。
  9. 如請求項7之方法，其中該分離閘極包括一多晶矽層。
  10. 如請求項5之方法，其中該第一傳導性類型摻雜物係一n型摻雜物。
  11. 如請求項5之方法，其中該第二傳導性類型係一p型。
  12. 如請求項10之方法，其中該n型摻雜物係磷、砷或銻。
TW098110268A 2009-02-24 2009-03-27 溝渠裝置結構及製造 TWI475614B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/391,450 US7989293B2 (en) 2009-02-24 2009-02-24 Trench device structure and fabrication

Publications (2)

Publication Number Publication Date
TW201032278A TW201032278A (en) 2010-09-01
TWI475614B true TWI475614B (zh) 2015-03-01

Family

ID=42630434

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098110268A TWI475614B (zh) 2009-02-24 2009-03-27 溝渠裝置結構及製造

Country Status (2)

Country Link
US (1) US7989293B2 (zh)
TW (1) TWI475614B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI632685B (zh) * 2015-12-21 2018-08-11 台灣積體電路製造股份有限公司 功率金屬氧化物半導體場效電晶體及用於製造其之方法
TWI685899B (zh) * 2018-04-05 2020-02-21 美商帕可科技有限公司 金屬氧化物半導體閘極式裝置之單元佈線及製造技術之強化

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8278702B2 (en) * 2008-09-16 2012-10-02 Fairchild Semiconductor Corporation High density trench field effect transistor
US8575688B2 (en) * 2009-02-24 2013-11-05 Maxpower Semiconductor, Inc. Trench device structure and fabrication
US8198678B2 (en) * 2009-12-09 2012-06-12 Infineon Technologies Austria Ag Semiconductor device with improved on-resistance
WO2011087994A2 (en) * 2010-01-12 2011-07-21 Maxpower Semiconductor Inc. Devices, components and methods combining trench field plates with immobile electrostatic charge
US8390060B2 (en) 2010-07-06 2013-03-05 Maxpower Semiconductor, Inc. Power semiconductor devices, structures, and related methods
US8884369B2 (en) 2012-06-01 2014-11-11 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical power MOSFET and methods of forming the same
US9087920B2 (en) 2012-06-01 2015-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Vertical power MOSFET and methods of forming the same
US9048214B2 (en) * 2012-08-21 2015-06-02 Semiconductor Components Industries, Llc Bidirectional field effect transistor and method
US11189702B2 (en) * 2019-01-30 2021-11-30 Vishay SIliconix, LLC Split gate semiconductor with non-uniform trench oxide
US11217541B2 (en) 2019-05-08 2022-01-04 Vishay-Siliconix, LLC Transistors with electrically active chip seal ring and methods of manufacture
US11218144B2 (en) 2019-09-12 2022-01-04 Vishay-Siliconix, LLC Semiconductor device with multiple independent gates
CN112382572B (zh) * 2021-01-15 2021-11-02 龙腾半导体股份有限公司 Ono屏蔽栅的sgt结构及其制造方法
TWI798899B (zh) * 2021-10-28 2023-04-11 力晶積成電子製造股份有限公司 半導體元件及其製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200703561A (en) * 2005-05-26 2007-01-16 Fairchild Semiconductor Trench-gate field effect transistors and methods of forming the same
TW200705680A (en) * 2005-06-10 2007-02-01 Fairchild Semiconductor Charge balance field effect transistor
TW200816370A (en) * 2006-09-28 2008-04-01 Semiconductor Components Ind Method of forming a semiconductor device having trench charge compensation regions

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5282018A (en) * 1991-01-09 1994-01-25 Kabushiki Kaisha Toshiba Power semiconductor device having gate structure in trench
JP3307785B2 (ja) * 1994-12-13 2002-07-24 三菱電機株式会社 絶縁ゲート型半導体装置
US5637898A (en) * 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
KR19980014820A (ko) * 1996-08-16 1998-05-25 김광호 트랜치 게이트형 모스 전계효과 트랜지스터 및 그 제조방법
JPH10256550A (ja) * 1997-01-09 1998-09-25 Toshiba Corp 半導体装置
JP3191747B2 (ja) * 1997-11-13 2001-07-23 富士電機株式会社 Ｍｏｓ型半導体素子
US6069372A (en) * 1998-01-22 2000-05-30 Mitsubishi Denki Kabushiki Kaisha Insulated gate type semiconductor device with potential detection gate for overvoltage protection
KR100295063B1 (ko) 1998-06-30 2001-08-07 김덕중 트렌치게이트구조의전력반도체장치및그제조방법
GB9815021D0 (en) * 1998-07-11 1998-09-09 Koninkl Philips Electronics Nv Semiconductor power device manufacture
US5998833A (en) * 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
US6191447B1 (en) * 1999-05-28 2001-02-20 Micro-Ohm Corporation Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same
US6285060B1 (en) * 1999-12-30 2001-09-04 Siliconix Incorporated Barrier accumulation-mode MOSFET
JP4363736B2 (ja) * 2000-03-01 2009-11-11 新電元工業株式会社 トランジスタ及びその製造方法
US20030007328A1 (en) * 2000-03-16 2003-01-09 Ulrich Fischer Cooling device for electronic components
US6541820B1 (en) * 2000-03-28 2003-04-01 International Rectifier Corporation Low voltage planar power MOSFET with serpentine gate pattern
KR100794811B1 (ko) * 2000-05-13 2008-01-15 엔엑스피 비 브이 트렌치 게이트 반도체 장치 및 그 제조 방법
US6818946B1 (en) * 2000-08-28 2004-11-16 Semiconductor Components Industries, L.L.C. Trench MOSFET with increased channel density
US6525372B2 (en) * 2000-11-16 2003-02-25 Silicon Wireless Corporation Vertical power devices having insulated source electrodes in discontinuous deep trenches
US6710403B2 (en) * 2002-07-30 2004-03-23 Fairchild Semiconductor Corporation Dual trench power MOSFET
US6677641B2 (en) 2001-10-17 2004-01-13 Fairchild Semiconductor Corporation Semiconductor structure with improved smaller forward voltage loss and higher blocking capability
TW543146B (en) * 2001-03-09 2003-07-21 Fairchild Semiconductor Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and miller charge
US20020179968A1 (en) * 2001-05-30 2002-12-05 Frank Pfirsch Power semiconductor component, compensation component, power transistor, and method for producing power semiconductor components
US6686244B2 (en) * 2002-03-21 2004-02-03 General Semiconductor, Inc. Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step
US7183610B2 (en) * 2004-04-30 2007-02-27 Siliconix Incorporated Super trench MOSFET including buried source electrode and method of fabricating the same
US7465986B2 (en) * 2004-08-27 2008-12-16 International Rectifier Corporation Power semiconductor device including insulated source electrodes inside trenches
US7544571B2 (en) * 2006-09-20 2009-06-09 Fairchild Semiconductor Corporation Trench gate FET with self-aligned features
US8278702B2 (en) * 2008-09-16 2012-10-02 Fairchild Semiconductor Corporation High density trench field effect transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200703561A (en) * 2005-05-26 2007-01-16 Fairchild Semiconductor Trench-gate field effect transistors and methods of forming the same
TW200705680A (en) * 2005-06-10 2007-02-01 Fairchild Semiconductor Charge balance field effect transistor
TW200816370A (en) * 2006-09-28 2008-04-01 Semiconductor Components Ind Method of forming a semiconductor device having trench charge compensation regions

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI632685B (zh) * 2015-12-21 2018-08-11 台灣積體電路製造股份有限公司 功率金屬氧化物半導體場效電晶體及用於製造其之方法
TWI685899B (zh) * 2018-04-05 2020-02-21 美商帕可科技有限公司 金屬氧化物半導體閘極式裝置之單元佈線及製造技術之強化

Also Published As

Publication number Publication date
US7989293B2 (en) 2011-08-02
US20100214016A1 (en) 2010-08-26
TW201032278A (en) 2010-09-01

Similar Documents

Publication Publication Date Title
TWI475614B (zh) 溝渠裝置結構及製造
US8310001B2 (en) MOSFET switch with embedded electrostatic charge
US8294235B2 (en) Edge termination with improved breakdown voltage
US7279743B2 (en) Closed cell trench metal-oxide-semiconductor field effect transistor
EP1033759B1 (en) MOS-gated device having a buried gate and process for forming same
US7989886B2 (en) Alignment of trench for MOS
US10861965B2 (en) Power MOSFET with an integrated pseudo-Schottky diode in source contact trench
US20180315846A1 (en) Scalable sgt structure with improved fom
US9837358B2 (en) Source-gate region architecture in a vertical power semiconductor device
WO2004061975A1 (en) Trench mis device having implanted drain-drift region and thick bottom oxide and process for manufacturing the same
KR100762545B1 (ko) Ｌｍｏｓｆｅｔ 및 그 제조 방법
US8575688B2 (en) Trench device structure and fabrication
CN112117332A (zh) Ldmos器件及工艺方法
JP2002026323A (ja) トレンチ底部に厚いポリシリコン絶縁層を有するトレンチゲート型ｍｉｓデバイスの製造方法
US11664434B2 (en) Semiconductor power devices having multiple gate trenches and methods of forming such devices
JP2003518749A (ja) ゲートのブレークダウン保護機能付きのシリコンカーバイトｌｍｏｓｆｅｔ
US11444167B2 (en) Method of manufacturing trench type semiconductor device
CN116207149A (zh) 半导体器件及其制作方法
US20120299109A1 (en) Trench power mosfet structure with high switching speed and fabrication method thereof
US8072027B2 (en) 3D channel architecture for semiconductor devices
CN108321206B (zh) Ldmos器件及其制造方法
JP2000315792A (ja) 半導体装置及びその製造方法
KR100405450B1 (ko) 포켓형 접합층 구조를 가지는 dmos 트랜지스터 및그 제조 방법
CN115763526A (zh) 半导体结构及其形成方法
CN116978945A (zh) 绝缘体上硅横向器件及其制造方法