TWI451549B - 嵌埋半導體元件之封裝結構及其製法 - Google Patents

嵌埋半導體元件之封裝結構及其製法 Download PDF

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TWI451549B
TWI451549B TW099139081A TW99139081A TWI451549B TW I451549 B TWI451549 B TW I451549B TW 099139081 A TW099139081 A TW 099139081A TW 99139081 A TW99139081 A TW 99139081A TW I451549 B TWI451549 B TW I451549B
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layer
dielectric layer
opening
package structure
semiconductor device
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TW099139081A
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TW201220457A (en
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Paohung Chou
Chih Hao Hsu
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Unimicron Technology Corp
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Description

嵌埋半導體元件之封裝結構及其製法
  本發明係有關一種封裝結構及其製法,尤指一種無核心板之嵌埋半導體元件之封裝結構及其製法。
  隨著半導體封裝技術的演進,半導體裝置(Semiconductor device)已開發出不同的封裝型態,而該半導體裝置主要係在一封裝基板(package substrate)裝置晶片,且將晶片電性連接在該封裝基板上,接著再以膠體進行封裝;而為降低封裝高度,遂有將晶片嵌埋在一封裝基板中,而此種封裝件能縮減整體半導體裝置之體積並提昇電性功能,遂成為一種封裝的趨勢。
  請參閱第1A至1E圖,係為習知嵌埋半導體元件之封裝結構的剖視示意圖。
  如第1A圖所示,首先,提供一具有貫穿之開口100之核心板10,於該核心板10之上、下兩側具有內層線路101,且於該核心板10中形成貫穿之導電通孔102,以電性連接上、下兩側之內層線路101。
  如第1B圖所示,於該核心板10底側設置一具有介電材120a之承載板14,以將一具有複數電極墊110之半導體晶片11容置於該開口100中,且藉由黏著層11a將該半導體晶片11設於該介電材120a上。
  如第1C圖所示,於該核心板10上側及半導體晶片11上壓合另一介電材120b,以使兩介電材120a,120b形成介電層12,且該介電層12填入於該開口100之孔壁與半導體晶片11之間的間隙中,以將該半導體晶片11固定於該開口100中。接著,移除該承載板14。
  如第1D圖所示,於該上、下兩側之介電層12上形成線路層13,且該線路層13具有位於該介電層12中並電性連接該電極墊110與內層線路101之導電盲孔130,又該上側線路層13具有電性接觸墊130a,而下側線路層13具有植球墊130b。
  如第1E圖所示,於該上、下兩側之介電層12及線路層13上形成防焊層15,且於該防焊層15中形成開孔150,以露出電性接觸墊130a及植球墊130b。
  惟,習知技術中,需於該核心板10中形成開口100,以將該核心板10兩側之介電層12壓擠該半導體晶片11,導致該半導體晶片11產生偏移(如第1C圖所示,該半導體晶片11與該開口100之孔壁的左右間距分別為t,s,其中t<s),使該半導體晶片11之成型偏移量約為+/-100μm,因而不易準確定位於該開口100中。因此,當該半導體晶片11產生偏移時,該半導體晶片11之電極墊110不易與該導電盲孔130精準對應以達成電性連接,如第1D圖所示,而容易產生電性連接之品質不良或失效的情況,導致降低產品的良率。
  再者,該半導體晶片11嵌埋於該核心板10之開口100中,並無任何導熱及散熱的結構,使該半導體晶片11之散熱不易,容易導致該半導體晶片11因過熱而損壞。
  又,厚度較薄之半導體晶片11需嵌埋於厚度較厚之核心板10中,使整體結構之厚度因該核心板10而大幅增加,導致產品的厚度增加,難以達到薄小化之目的。
  另外,需於該核心板10之兩側進行線路製程,因而需製作該導電通孔102以導通兩側內層線路101與線路層13,不僅導致成本增加,且提高製作難度。
  因此,如何避免習知技術中之種種缺失,實已成為目前亟欲解決的課題。
  鑑於上述習知技術之種種缺失,本發明之一目的係在提供一種對位較準之嵌埋半導體元件之封裝結構及其製法。
  本發明之又一目的係在提供一種提高散熱性之嵌埋半導體元件之封裝結構及其製法。
  本發明之再一目的係在提供一種薄小化之嵌埋半導體元件之封裝結構及其製法。
  本發明之另一目的係在提供一種降低成本之嵌埋半導體元件之封裝結構及其製法。
  為達上述及其他目的,本發明揭露一種嵌埋半導體元件之封裝結構,係包括:第一介電層,係具有相對之第一表面及第二表面;半導體晶片,係凸出嵌設於該第一介電層之第二表面,該半導體晶片具有相對之作用面及非作用面,且於該作用面上具有位於該第一介電層中之電極墊,而該非作用面及其相鄰之部分側面係凸出於該第一介電層之第二表面;第一線路層,係設於該第一介電層之第一表面上,並於該第一介電層中形成電性連接該第一線路層與該電極墊之複數第一導電盲孔;增層結構,係設於該第一介電層之第一表面及該第一線路層上;以及絕緣保護層,係設於該增層結構上,並於該絕緣保護層中形成複數開孔,以令該增層結構之部分表面外露於該開孔中。
  前述之封裝結構復包括金屬層,係設於該介電層之第二表面上,且該金屬層具有開口,以令該半導體晶片位於該開口中,以令該金屬層作為散熱件。又包括承載層,係設於該金屬層及該半導體晶片之非作用面上,以令該承載層作為散熱件,且形成該承載層之材質係為銅。
  前述之封裝結構中,該增層結構係具有至少一第二介電層、設於該第二介電層上之第二線路層、及設於該第二介電層中且電性連接該第一與第二線路層之第二導電盲孔,且令該增層結構之部分第二線路層表面外露於該開孔中。
  前述之封裝結構復包括表面處理層,係設於該開孔中之增層結構之外露表面上,且形成該表面處理層之材料係選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金(ENIG)、化鎳鈀浸金(ENEPIG)、化學鍍錫(Immersion Tin)及有機保焊劑 (OSP)所組成之群組中之其中一者。
  本發明復提供一種嵌埋半導體元件之封裝結構之製法,係包括:提供一具有相對之兩表面之核心板,且於該核心板之兩表面上具有承載層;於該承載層上形成具有開口之金屬層,以令該承載層之部分表面外露於該開口中;於該開口中之承載層上設置半導體晶片,該半導體晶片具有相對之作用面及非作用面,於該作用面上具有電極墊,且該半導體晶片係以該非作用面結合至該開口中之承載層上;於該金屬層及該半導體晶片上形成第一介電層,且該第一介電層具有外露之第一表面及結合至該金屬層上之第二表面;於該第一介電層之第一表面上形成第一線路層,且於該第一介電層中形成複數電性連接該第一線路層與該電極墊之第一導電盲孔;於該第一介電層之第一表面及該第一線路層上形成增層結構;於該增層結構上形成絕緣保護層,且於該絕緣保護層中形成複數開孔,以令該增層結構之部分表面外露於該開孔中;以及移除該核心板,以外露出該承載層。
  前述之製法中,該核心板之兩表面與該承載層之間具有離形層,以藉由該離形層移除該核心板。
  前述之製法中,形成該承載層之材質係為銅。
  前述之製法中,形成該金屬層之製程係包括:於該承載層上形成阻層,且於該阻層上形成開口區,以令該承載層之部分表面外露於該開口區;於該開口區之承載層上形成該金屬層;以及移除該阻層,以形成該開口。
  前述之製法中,該增層結構係具有至少一第二介電層、設於該第二介電層上之第二線路層、及設於該第二介電層中且電性連接該第一與第二線路層之第二導電盲孔,以令該增層結構之部分第二線路層表面外露於該開孔中。
  前述之製法中,於移除該核心板之後,該承載層及該金屬層係作為散熱件。
  前述之製法中,於移除該核心板之後,再移除該承載層及該金屬層,以外露出該介電層之第二表面,且該非作用面及其相鄰之部分側面係凸出於該介電層之第二表面。
  前述之製法中,於該開孔中之增層結構之外露表面上形成表面處理層,且形成該表面處理層之材料係選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金(ENIG)、化鎳鈀浸金(ENEPIG)、化學鍍錫(Immersion Tin)及有機保焊劑 (OSP)所組成之群組中之其中一者。
  由上可知,本發明嵌埋半導體元件之封裝結構及其製法,藉由半導體晶片設於該承載層上,可提升對位之準確性。再者,藉由移除該核心板、及僅需於該第一介電層之其中一表面上進行線路增層之製程,可降低整體結構之厚度,以達到薄小化之目的。又,因無需進行貫穿整體結構兩側之導電通孔製程,故可降低成本,且使製程簡易。另外,藉由該半導體晶片凸出於該介電層或覆蓋金屬層,可提高半導體晶片之散熱性,有效避免該半導體晶片過熱而損壞。
  以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
  請參閱第2A至2H圖,係為本發明嵌埋半導體元件之封裝結構的製法之剖視示意圖。
  如第2A圖所示,提供一具有相對之兩表面20a之核心板20,且於該核心板20之兩表面20a上依序具有離形層200及係為銅材之承載層21。
  如第2B圖所示,於該承載層21上形成阻層22後,以曝光顯影之方式形成開口區220,且該承載層21之部分表面外露於該阻層22;接著,於該承載層21上電鍍形成亦為銅材之金屬層23。
  如第2C圖所示,移除該阻層22,以形成具有開口230之金屬層23,且令該承載層21之部分表面外露於該開口230中,其中,該開口230係定義為晶片承載區。
  如第2D圖所示,於該開口230中之承載層21上設置半導體晶片24,該半導體晶片24具有相對之作用面24a及非作用面24b,於該作用面24a上具有電極墊240,且該半導體晶片24係以該非作用面24b結合至該開口230中之承載層21上。其中,藉由該阻層22之曝光顯影之方式,可使半導體晶片24之位置準確度等同於曝光對位準確度,以提高對位之準確性(成型偏移量約為+/-10μm)相較於習知製法明顯提高許多。
  接著,於該金屬層23及該半導體晶片24上形成第一介電層25,且該第一介電層25具有外露之第一表面25a及結合至該金屬層23上之第二表面25b。
  如第2E圖所示,於該第一介電層25之第一表面25a上形成第一線路層26,且於該第一介電層25中形成複數電性連通該第一線路層26與該電極墊240之第一導電盲孔260。其中,該第一介電層25之厚度可依欲形成之第一導電盲孔260之雷射鑽孔之孔徑作調整。
  接著,於該第一介電層25之第一表面25a及該第一線路層26上形成增層結構27,該增層結構27係具有至少一第二介電層270、設於該第二介電層270上之第二線路層271、及設於該第二介電層270中且電性連通該第一線路層26與第二線路層271之第二導電盲孔272。
  再於該增層結構27上形成絕緣保護層28,且於該絕緣保護層28中形成複數開孔280,以令該增層結構27之部分第二線路層271表面外露於該開孔280中。
  又於該開孔280中之第二線路層271之外露表面上形成表面處理層29,且形成該表面處理層29之材料係選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金(ENIG)、化鎳鈀浸金(ENEPIG)、化學鍍錫(Immersion Tin)及有機保焊劑 (OSP)所組成之群組中之其中一者。
  如第2F圖所示,藉由該離形層200以移除該核心板20,而成為無核心板(coreless)之封裝結構,以降低整體封裝結構之厚度,有效達到薄小化之目的。
  如第2G圖所示,移除該承載層21及該金屬層23,以外露出該第一介電層25之第二表面25b,且該半導體晶片24之非作用面24b及其相鄰之部分側面係凸出於該第一介電層25之第二表面25b,以提高散熱性,俾能免除該半導體晶片24過熱而損壞。
  再者,電鍍該金屬層23之高度即為該半導體晶片24凸出該第一介電層25之第二表面25b之高度,故可依需求藉由該金屬層23之高度控制凸出之高度,使該半導體晶片24嵌埋深度可自行控制,以便於該第一導電盲孔260之雷射鑽孔之製程調整參數。
  如第2H圖所示,於後續製程中,可於該增層結構27之第二線路層271之外露表面上形成焊球30,以藉該些焊球30接置於一印刷電路板31上。
  本發明藉由該阻層22之曝光顯影之方式,可使半導體晶片24之成型偏移量約為+/-10μm,相較於習知技術中之成型偏移量為+/-100μm,本發明之準確性明顯提高。
  再者,本發明係為無核心板(coreless)之封裝結構,且僅需於該第一介電層25之第一表面25a上進行線路增層之製程,而不需於該第一介電層25之第二表面25b上進行線路增層之製程,故相較於習知技術中之於核心板兩側進行線路增層之製程,本發明有效降低整體結構之厚度。
  又,因本發明無需進行如習知技術之導電通孔之製程,不僅降低成本,且使製程簡易。
  另外,該半導體晶片24凸出於該第一介電層25之第二表面25b,以提高散熱性,俾能免除該半導體晶片24過熱而損壞,有效克服習知技術之半導體晶片散熱不易之問題。
  於另一實施例中,如第2H’圖所示,於第2F圖之移除該核心板20之製程後,係保留該承載層21及該金屬層23以作為散熱件,亦能提高散熱以避免該半導體晶片24過熱而損壞。接著,於該第二線路層271之外露表面上形成焊球30,再將該些焊球30接置於一印刷電路板31上。
  本發明復提供一種嵌埋半導體元件之封裝結構,係包括:具有相對之第一表面25a及第二表面25b之第一介電層25、凸出嵌設於該第一介電層25之第二表面25b之半導體晶片24、設於該第一介電層25之第一表面25a上之第一線路層26、設於該第一介電層25之第一表面25a及該第一線路層26上之增層結構27、以及設於該增層結構27上之絕緣保護層28。
  所述之半導體晶片24具有相對之作用面24a及非作用面24b,且於該作用面24a上具有位於該第一介電層25中之電極墊240,而該非作用面24b及其相鄰之部分側面係凸出於該第一介電層25之第二表面25b。
  所述之第一線路層26於該第一介電層25中形成電性連通該電極墊240之複數第一導電盲孔260。
  所述之增層結構27係具有至少一第二介電層270、設於該第二介電層270上之第二線路層271、及設於該第二介電層270中且電性連通該第一與第二線路層26,271之第二導電盲孔272。
  所述之絕緣保護層28於其中形成複數開孔280,以令該增層結構27之部分第二線路層271表面外露於該開孔280中,而使焊球30係設於該第二線路層271之外露表面上,以接置於一印刷電路板31上。
  所述之封裝結構復包括金屬層23,係設於該第一介電層25之第二表面25b上,且該金屬層23具有開口230,以令該半導體晶片24位於該開口230中,以令該金屬層23作為散熱件。該封裝結構又包括承載層21,係設於該金屬層23及該半導體晶片24之非作用面24b上,以令該承載層21亦作為散熱件。其中,形成該承載層21之材質係為銅。
  所述之封裝結構復包括表面處理層29,係設於該開孔280中之增層結構27之第二線路層271之外露表面上,且形成該表面處理層29之材料係選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金(ENIG)、化鎳鈀浸金(ENEPIG)、化學鍍錫(Immersion Tin)及有機保焊劑 (OSP)所組成之群組中之其中一者。
  綜上所述,本發明嵌埋半導體元件之封裝結構及其製法藉由阻層曝光顯影之方式,可使半導體晶片之成型偏移量優於習知技術中之成型偏移量,有效提升對位之準確性。
  再者,藉由移除該核心板,以成為無核心板(coreless)之封裝結構,且因僅需於該第一介電層之其中一表面上進行線路增層之製程,故大幅降低整體結構之厚度,而達到薄小化之目的。
  又,藉由僅於該第一介電層之其中一表面上進行線路增層之製程,故無需進行貫穿整體結構兩側之導電通孔製程,因而有效降低成本,且使製程簡易。
  另外,藉由該半導體晶片凸出於該介電層及覆蓋金屬層,因而提高半導體晶片之散熱性,有效避免該半導體晶片過熱而損壞。
  上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
10,20...核心板
100,230...開口
101...內層線路
102...導電通孔
11,24...半導體晶片
11a...黏著層
110,240...電極墊
12...介電層
120a,120b...介電材
13...線路層
130...導電盲孔
130a...電性接觸墊
130b...植球墊
14...承載板
15...防焊層
150,280...開孔
20a...表面
200...離形層
21...承載層
22...阻層
220‧‧‧開口區
23‧‧‧金屬層
24a‧‧‧作用面
24b‧‧‧非作用面
25‧‧‧第一介電層
25a‧‧‧第一表面
25b‧‧‧第二表面
26‧‧‧第一線路層
260‧‧‧第一導電盲孔
27‧‧‧增層結構
270‧‧‧第二介電層
271‧‧‧第二線路層
272‧‧‧第二導電盲孔
28‧‧‧絕緣保護層
29‧‧‧表面處理層
30‧‧‧焊球
31‧‧‧印刷電路板
t,s‧‧‧間距
  第1A至1E圖係為習知嵌埋半導體元件之封裝結構之製法的剖視示意圖;以及
  第2A至2H圖係為本發明嵌埋半導體元件之封裝結構之製法的剖視示意圖;其中,第2H’圖係為第2H圖之另一實施態樣。
24...半導體晶片
24a...作用面
24b...非作用面
240...電極墊
25...第一介電層
25a...第一表面
25b...第二表面
26...第一線路層
260...第一導電盲孔
27...增層結構
270...第二介電層
271...第二線路層
272...第二導電盲孔
28...絕緣保護層
280...開孔
29...表面處理層

Claims (15)

  1. 一種嵌埋半導體元件之封裝結構,係包括:第一介電層,係具有相對之第一表面及第二表面;半導體晶片,係凸出嵌設於該第一介電層之第二表面,該半導體晶片具有相對之作用面及非作用面,且於該作用面上具有位於該第一介電層中之電極墊,而該非作用面及其相鄰之部分側面係凸出於該第一介電層之第二表面;第一線路層,係設於該第一介電層之第一表面上,並於該第一介電層中形成電性連接該第一線路層與該電極墊之複數第一導電盲孔;增層結構,係設於該第一介電層之第一表面及該第一線路層上;絕緣保護層,係設於該增層結構上,並於該絕緣保護層中形成複數開孔,以令該增層結構之部分表面外露於該開孔中;以及金屬層,係設於該第一介電層之第二表面上,且該金屬層具有開口,以令該半導體晶片位於該開口中,以令該金屬層作為散熱件,該金屬層係齊平於該非作用面,該金屬層之開口係供該半導體晶片對位。
  2. 如申請專利範圍第1項所述之嵌埋半導體元件之封裝結構,復包括承載層,係設於該金屬層及該半導體晶片之非作用面上,以令該承載層作為散熱件。
  3. 如申請專利範圍第2項所述之嵌埋半導體元件之封裝結構,其中,形成該承載層之材質係為銅。
  4. 如申請專利範圍第1項所述之嵌埋半導體元件之封裝結構,其中,該增層結構係具有至少一第二介電層、設於該第二介電層上之第二線路層、及設於該第二介電層中且電性連接該第一與第二線路層之第二導電盲孔,且令該增層結構之部分第二線路層表面外露於該開孔中。
  5. 如申請專利範圍第1項所述之嵌埋半導體元件之封裝結構,復包括表面處理層,係設於該開孔中之增層結構之外露表面上。
  6. 如申請專利範圍第5項所述之嵌埋半導體元件之封裝結構,其中,形成該表面處理層之材料係選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金(ENIG)、化鎳鈀浸金(ENEPIG)、化學鍍錫(Immersion Tin)及有機保焊劑(OSP)所組成之群組中之其中一者。
  7. 一種嵌埋半導體元件之封裝結構之製法,係包括:提供一具有相對之兩表面之核心板,且於該核心板之兩表面上具有承載層;於該承載層上形成具有開口之金屬層,以令該承載層之部分表面外露於該開口中;於該開口中之承載層上設置半導體晶片,該半導體晶片具有相對之作用面及非作用面,於該作用面上具有電極墊,且該半導體晶片係以該非作用面結合至該開口中之承載層上;於該金屬層及該半導體晶片上形成第一介電層,且該第一介電層具有外露之第一表面及結合至該金屬層上之第二表面;於該第一介電層之第一表面上形成第一線路層,且於 該第一介電層中形成複數電性連接該第一線路層與該電極墊之第一導電盲孔;於該第一介電層之第一表面及該第一線路層上形成增層結構;於該增層結構上形成絕緣保護層,且於該絕緣保護層中形成複數開孔,以令該增層結構之部分表面外露於該開孔中;以及移除該核心板,以外露出該承載層。
  8. 如申請專利範圍第7項所述之嵌埋半導體元件之封裝結構之製法,其中,該核心板之兩表面與該承載層之間具有離形層,以藉由該離形層移除該核心板。
  9. 如申請專利範圍第7項所述之嵌埋半導體元件之封裝結構之製法,其中,形成該承載層之材質係為銅。
  10. 如申請專利範圍第7項所述之嵌埋半導體元件之封裝結構之製法,其中,形成該金屬層之製程係包括:於該承載層上形成阻層,且於該阻層上形成開口區,以令該承載層之部分表面外露於該開口區;於該開口區之承載層上形成該金屬層;以及移除該阻層,以形成該開口。
  11. 如申請專利範圍第7項所述之嵌埋半導體元件之封裝結構之製法,其中,該增層結構係具有至少一第二介電層、設於該第二介電層上之第二線路層、及設於該第二介電層中且電性連接該第一與第二線路層之第二導電盲孔,以令該增層結構之部分第二線路層表面外露於該開孔中。
  12. 如申請專利範圍第7項所述之嵌埋半導體元件之封裝結構之製法,其中,於移除該核心板之後,該承載層及該金屬 層係作為散熱件。
  13. 如申請專利範圍第7項所述之嵌埋半導體元件之封裝結構之製法,復包括於移除該核心板之後,再移除該承載層及該金屬層,以外露出該介電層之第二表面,且該非作用面及其相鄰之部分側面係凸出於該介電層之第二表面。
  14. 如申請專利範圍第7項所述之嵌埋半導體元件之封裝結構之製法,復包括於該開孔中之增層結構之外露表面上形成表面處理層。
  15. 如申請專利範圍第14項所述之嵌埋半導體元件之封裝結構之製法,其中,形成該表面處理層之材料係選自由電鍍鎳/金、化學鍍鎳/金、化鎳浸金(ENIG)、化鎳鈀浸金(ENEPIG)、化學鍍錫(Immersion Tin)及有機保焊劑(OSP)所組成之群組中之其中一者。
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