201039415 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝結構及其製法，尤指一種具有 細線路間距之佈局的封裝基板結構及其製法暨覆晶封裝結 構及其製法。 【先前技術】 隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功 能、高性能的研發方向。目前用以承載半導體晶片之封裝 基板係包括有打線式封裝基板、晶片尺寸封裝（CSP)基板及 覆晶基板(FCBGA)等；且為因應微處理器、晶片組、與繪 圖晶片之運算需要，佈有線路之封裝基板亦需提昇其傳遞 晶片訊號之品質、改善頻見、控制阻抗專功能’以因應而 I/O數封裝件的發展。 在現行覆晶技術中，係將半導體晶片電性接置於封裝 基板上，該半導體積體電路(1C)晶片的表面上配置有電極 墊（electronic pad )，而該封裝基板具有相對應之電性連 接墊，且於該半導體晶片以及封裝基板之間可以適當地設 置焊錫凸塊或其他導電黏者材料，使該半導體晶片以電性 接觸面朝下的方式設置於該封裝基板上，以藉該焊錫凸塊 或導電黏著材料使該半導體晶片電性連接至封裝基板，並 在該半導體晶片與封裝基板間填充底部填膠（Underfill resin)，以藉該底部填膠減少半導體晶片與封裝基板之間因 熱膨脹差異所產生的熱應力。習知覆晶封裝結構之製法係 示於第1A至1E圖。 4 111184 201039415 首先，如第1A圖所示，提供一具有至少一表面10a 之基板本體10，於該基板本體10之表面10a上形成線路 層11，且該線路層11具有複數電性接觸墊112。 如第1B圖所示，於該表面10a及線路層11上形成防 焊層12,且該防焊層12中形成複數開孔120,俾令各該電 性接觸墊112對應外露於各該開孔120中。 如第1C圖所示，接著，於各該開孔120中之電性接 觸墊112上形成預焊料14。 〇 如第1D圖所示，於該基板本體10上之預焊料14經 迴焊及整平而形成高度一致的焊料凸塊14a後，再接置一 具有複數電極凸塊151之半導體晶片15。 最後，如第1E圖所示，進行迴焊製程，令焊料凸塊 14a包覆電極凸塊151而形成導電凸塊155,並於該基板本 體10與半導體晶片15之間填入底部填膠16,藉以減少該 半導體晶片15與封裝基板10之間因熱膨脹差異所產生的 0熱應力。 惟，上述之覆晶封裝製程中，於進行高密度佈線之細 間距的佈局，例如：各該焊料凸塊14a之間距在100 // m 以下，其對位精度小於10//m，且該防焊層12之開孔120 的孔徑為50//m以下，易造成對位及形成該防焊層12之 開孔120的困難，亦增加製程設備的成本。 再者，於細間距佈局中，常因該防焊層12之開孔120 細小，而使該預焊料14不易填入該開孔120 ;又該些電性 接觸墊112的間距狹窄，導致各該開孔120的間距狹窄， 5 111184 201039415 於迴焊製程中易造成該焊料凸塊14a溢流而產生橋接 (bridge)現象，致使電性導接短路。 又，習知覆晶方式係先於單顆的基板本體10上之預 焊料14經迴焊及整平而形成高度一致的焊料凸塊14a後， 接著接置一具有複數電極凸塊151之半導體晶片15,再進 行後續製程；其中，具有複數個基板本體1〇的板材平整性 較差，不易形成高度一致的焊料凸塊14a以進行大版面 (panel )封裝，致使習知覆晶封裝結構僅能進行單顆封 裝，而耗費製程步驟及成本。 另外，該基板本體10與半導體晶片15之間必須填入 底部填膠16，而在細間距之製程中，因間距縮小，導致該 焊料凸塊14a隨之縮小，遂致迴焊後形成之導電凸塊155 高度也隨之縮減，致使該半導體晶片15與基板本體10之 防焊層12之間的距離縮短，因而該半導體晶片15與防焊 層12之間的間隔狹窄，致使該底部填膠16不易流入填滿， 且容易產生空隙，而於後續製程中易產生可靠度問題。 因此，如何提供一種封裝基板、覆晶封裝及其製法， 以於高密度佈線之細間距佈局中，克服進行線路對位、形 成防焊層開孔、及預焊料填入開孔的困難性等，且可避免 在迴焊製程中產生焊料凸塊橋接短路及底部填膠不易填入 等缺失，實已成爲目前業界亟待克服之課題。 【發明内容】 鑑於上述習知技術之缺失，本發明之主要目的係提供 一種封裝基板結構及其製法暨覆晶封裝結構及其製法，能 6 111184 201039415 有效克服細線路製程中進行線路對位、形成防焊層開孔及 預焊料填入開孔的困難性，並免除迴焊製程中產生橋接短 路之缺失。 為達上述及其他目的，本發明提供一種封裝基板結 構，係包括：基板本體，係具有第一表面；第一線路層， 係形成於該第一表面上，且具有複數電性接觸墊；絕緣薄 膜，係形成於該基板本體及第一線路層上，並形成有複數 第一開孔，令該些電性接觸墊對應外露於各該第一開孔， 〇且該絕緣薄膜之厚度係低於該第一線路層之厚度；第一防 焊層，係形成於該絕緣薄膜上，且該第一防焊層中形成開 口，令部份之絕緣薄膜及該些電性接觸墊露出於該開口； 以及異方性導電膠，係形成於該第一防焊層之開口中的絕 緣薄膜及電性接觸墊上。 本發明復提供一種覆晶封裝結構，係包括：基板本 體，係具有第一表面，於該第一表面上形成第一線路層， 0且該第一線路層具有複數電性接觸墊；絕緣薄膜，係形成 於該基板本體及第一線路層上，並形成有複數第一開孔， 令該些電性接觸墊對應外露於各該第一開孔，且該絕緣薄 膜之厚度係低於該第一線路層之厚度；第一防焊層，係形 成於該絕緣薄膜上，且該第一防焊層中形成開口，令部份 之絕緣薄膜及該些電性接觸墊露出於該開口；以及表面處 理層，係對應形成於各該第一開孔中之電性接觸墊上；異 方性導電膠，係形成於該第一防焊層之開口中的絕緣薄膜 及電性接觸墊上；以及半導體晶片，係壓合於該異方性導 7 111184 201039415 電膠上5並具有複數電極凸塊’使該電極凸塊對應各該電 性接觸墊，以令各該電極凸塊與電性接觸墊之間的異方性 導電膠形成導電通路，俾使該電極凸塊藉由該異方性導電 膠所形成之導電通路電性連接至該電性接觸墊。 依上述之封裝基板結構暨覆晶封裝結構，該電極凸塊 係可壓合於該異方性導電膠上，或該電極凸塊經壓合後係 可嵌埋於該異方性導電膠中。 依上述之封裝基板結構暨覆晶封裝結構，復包括表面 處理層，係對應形成於各該第一開孔中之電性接觸墊上， 且形成該表面處理層之材料係選自由化學鍍鎳/金、化鎳浸 金、化鎳鈀浸金、化學鍍錫及有機保焊劑所組成之群组中 之其中一者。 此外’依上述之封裝基板結構及覆晶封裝結構5該基 板本體復具有相對於該第一表面之第二表面及形成於該第 二表面上之第二線路層，該第二線路層並具有複數植球 墊；又該封裝結構復包括形成於該第二表面及第二線路層 上之第二防焊層，該第二防焊層中並形成複數第二開孔， 令該些植球塾對應外露於各該第二開孔。 本發明再提供一種封裝基板結構之製法，係包括：提 供一基板本體，係具有第一表面，於該基板本體之第一表 面上形成第一線路層，且該第一線路層具有複數電性接觸 墊；於該第一表面及第一線路層上形成絕緣薄膜，且該絕 緣薄膜之厚度係低於該第一線路層之厚度，該絕緣薄膜並 形成複數第一開孔，令該些電性接觸墊對應露出於各該第 8 111184 201039415 一開孔；於該絕緣薄膜上形成第—^ 層中形成開口，令部份之絕緣薄*防烊層，且該第一防焊 於該開口；以及於該第一防焊層、及忒些電性接觸墊露出 該第一開孔t之電性接觸墊上7之，σ中的絕緣薄膜及各 本發明復提供-種覆枝導電摩。 供一基板本體，係具有第—表χ、’’°構之製法，係包括：提 面上形成第一線路層，且該 於該基板本體之第一表 Ο =，於該第—表面 線路層具有複數電性接觸 厚度係低於該第上形成絕緣薄膜，且該絕 γ赞數第1孔 層之厚度，該絕緣薄 第〜開孔.妖 各該電性接艋埶拟由， 焊層中形成：絕緣薄膜上形成第-防J 於各該 ，讀I Γ令部份之絕綠_且該第一防 〇電〜， 第、心中：該第-防焊層之開口t:'性接觸塾露 4方健“電性接觸塾切^ 的、％緣薄膜及各該 W上壓料導體 導4 ’以及於該 袼鬼與電性ΓΓ應各該電性接觸塾，以： 难電技雙麵凸塊藉由導電谬形成導電通 、故電性接觸藝異方性導電谬所形成之導電通 電麵A 4¾ #封裝基板結構#覆s # # 髮，4,合於該異方:導二Γ其製法，該 心依、2於料林導電極凸翻 ^ ^ 5 令裳基板結構及复制、、本批 I祛於各該第—n :衣〆旦覆晶封裝結構及 開孔中之電性接觸塾上形成表 9 電趣λ ""，使讀電極日日，該半導體晶片具有藉溆 電=對應各該電性接觸塾，以I: ’生接觸墊之間 墊以令各該 U1184 201039415 面處理層，且形成該表面處理層之材料係可選自由化學鍍 鎳/金、化錄浸金、化鎳把浸金、化學鑛錫及有機保焊劑所 組成之群組中之其中一者。 又依上述之封裝基板結構暨覆晶封裝結構及其製 法，該基板本體復具有相對應於該第一表面之第二表面， 且於該第二表面上形成第二線路層，該第二線路層並具有 複數植球墊，又於該第二表面及第二線路層上形成第二防 焊層，並於該第二防焊層中形成複數第二開孔，令該些植 球墊對應外露於各該第二開孔。 本發明之封裝基板結構及其製法暨覆晶封裝結構及 其製法，主要係於該基板本體之第一表面及第一線路層上 先形成絕緣薄膜，並於該絕緣薄膜中形成複數第一開孔以 對應露出各該第一線路層之電性接觸墊，接著於該絕緣薄 膜上形成第一防焊層，且該第一防焊層中形成開口，以露 出部份之絕緣薄膜及該些電性接觸墊，於該電性接觸墊上 形成表面處理層，再於該第一防焊層之開口中的絕緣薄膜 及表面處理層上形成異方性導電膠，然後將該半導體晶片 壓合於該異方性導電膠上，令該半導體晶片之電極凸塊與 基板本體之電性接觸墊對應壓合，而於該異方性導電膠中 形成導電通路，俾令該電極凸塊經由該導電通路以電性連 接至該電性接觸墊。 由上可知，本發明於細間距佈局中，可有效克服習知 進行線路對位、形成防焊層開孔及預焊料填入開孔的困難 性，並能避免習知迴焊製程中產生焊料凸塊橋接短路之缺 10 111184 201039415 失；再者，該絕緣薄膜之厚度低於該第一線路層之厚度， 相較於習知之防焊層厚度均高於線路層，可提供足夠的高 度差（線路層高於絕緣薄膜），使該異方性導電膠填入後易 於分散，而有效包覆該基板本體之電性接觸墊，不致產生 空隙，再使該半導體晶片之電極凸塊係對應壓合於該異方 性導電膠上，或者嵌入該異方性導電膠中，俾有效避免習 知底部填膠易產生空隙之問題，進而避免於後續製程中產 生之可靠度問題。 ^ 又，相較於習知技術，本發明不用焊錫材料，更無需 形成高度一致的焊料凸塊，而係藉由該異方性導電膠覆蓋 該基板本體之表面，以包覆該電性接觸墊，再將複數個半 導體晶片壓合於該異方性導電膠，以同時對位於具複數個 基板本體的板材’使該些晶片的電極凸塊對應各該基板本 體的電性接觸墊，即可進行大版面（panel )封裝，俾有效 節省製程步驟及成本；再者，依實際製程需要，亦可進行 ^單顆封裝。 此外，本發明藉由該異方性導電膠作為導電元件，無 須進行習知迴焊而使焊料凸塊包覆電極凸塊以形成導電凸 塊之製程，且本發明無須使用焊料凸塊，因而未形成較高 之電極凸塊，俾有效降低整體封裝結構的厚度。 【實施方式】 以下係藉由特定的具體實例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 暸解本發明之其他優點與功效。 11 111184 201039415 請參閱第2A至2E圖，係為本發明封裝基板結構及其 製法暨覆晶封裝結構及其製法的示意圖。 如第2A圖所示，提供一具有内層線路（圖式中未表 示）之基板本體20，係具有相對應之第一表面20a及第二 表面20b，於該基板本體20之第一表面20a及第二表面20b 上分別形成第一線路層21a及第二線路層21b，且藉由該 基板本體20中之内層線路的導電通孔（圖式中未表示）及 導電盲孔（圖式中未表示），令該第一線路層21a電性連 接至該第二線路層21b，且該第一線路層21a具有複數電 性接觸墊211，而該第二線路層21b具有複數植球墊212。 如第2B圖所示，於該第一表面20a及第一線路層21a 上形成絕緣薄膜22，該絕緣薄膜22中並形成複數第一開 孔220，令該些電性接觸墊211對應外露於各該第一開孔 220，又該絕緣薄膜22之厚度係低於該第一線路層21a之 厚度；其中，該絕緣薄膜22之厚度係為0.1至5μιη;另外， 該絕緣薄膜22係以高分子材料製成。 如第2C圖所示，於該絕緣薄膜22上形成第一防焊層 23a，且該第一防焊層23a中形成開口 230a，令部份之絕 緣薄膜22及該些電性接觸墊211露出於該開口 230a ;又 於該第二表面20b及第二線路層21b上形成第二防焊層 23b，於該第二防焊層23b中形成複數第二開孔230b，令 該些植球墊212對應外露於各該第二開孔230b。 如第2D圖所示，於該絕緣薄膜22之各該第一開孔 220中的電性接觸墊211上形成表面處理層24 ;其中，形 12 111184 201039415 成該表面處理層24之材料係選自由化學鍍鎳/金（Ni/Au， 係先形成錄，之後再形成金）、化鎳浸金（Electroless Ni & Immersion Gold, ENIG )、化鎳把浸金（Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG)、 化學鍍錫（Immersion Tin)及有機保焊劑（〇SP)所組成之 群組中之其中一者；相對於習知技術，本發明無需使用導 電凸塊，因而較習知結構之高度低。 如第2E圖所示，於該第一防焊層23a之開口 230a中 〇的絕緣薄膜22及各該第一開孔220中之電性接觸墊211 上形成異方性導電膠（Anisotropic Conductive Film, ACF)26。 本發明之絕緣薄膜22之厚度低於該第一線路層21a 之厚度，相較於習知防焊層厚度高於線路層之結構，本發 明可提供足夠的高度差（該第一線路層2la高於該絕緣薄 膜22)，令該異方性導電膠26填入後易於分散，而有效包 〇覆該基板本體20之電性接觸塾211，以避免產生空隙。 所述之異方性導電膠(ACF，俗稱異方導電膜）26，主 要由黏接劑(Binder)與導電粒子組成，其可提供兩種接合物 體僅於單一方向作電性導通，於本實施例中，係作垂直方 向電性導通，而對於水平方向則具有絕緣效果。 本發明復提供一種封裝基板結構’係包括··基板本體 2〇’係具有第一表面2〇a;第一線路層21a，係形成於該第 一表面2〇a上’且具有複數電性接觸墊211 ;絕緣薄膜22， 係形成於該基板本體2〇之第一表面2〇a及第一線路層2u 111184 201039415 上，並形成複數第一開孔220，令該些電性接觸墊211對 應外露於各該第一開孔220,且該絕緣薄膜22之厚度係低 於該第一線路層21a之厚度；第一防焊層23a，係形成於 該絕緣薄膜22上，且該第一防焊層23a中形成開口 230a， 令部份之絕緣薄膜22及該些電性接觸墊211露出於該開口 230a ;以及異方性導電膠26，係形成於該第一防焊層23a 之開口 230a中的絕緣薄膜22及電性接觸墊211上；以及 表面處理層24,係形成於該電性接觸墊211及異方性導電 膠26之間。 依上述之封裝基板結構，形成該表面處理層24之材 料係選自由化學鍍鎳/金（Ni/Au)、化鎳浸金（ENIG)、 化鎳把浸金（ENEPIG)、化學鍍錫（Immersion Tin)及 有機保焊劑（OSP)所組成之群組中之其中一者。 依上所述，該基板本體20具有相對於該第一表面20a 之第二表面20b，於該第二表面20b上係形成第二線路層 21b，該第二線路層21b並具有複數植球墊212 ;該封裝基 板結構復包括形成於該第二表面20b及第二線路層21b上 之第二防焊層23b，且該第二防焊層23b形成複數第二開 孔230b，令該些植球墊212對應外露於各該第二開孔230b。 請參閱第3及3’圖，係為本發明之封裝基板上壓合半 導體晶片之實施例；如圖所示，於該異方性導電膠26上壓 合半導體晶片27,該半導體晶片27具有複數電極凸塊 271，使該電極凸塊271對應各該電性接觸墊211，以令各 該電極凸塊271與電性接觸墊211之間的異方性導電膠26 14 111184 201039415 ===俾該電極凸塊271藉由該導電通路- 電極凸塊厂/妾㈣211，其中，該半導體晶片27之 条；亦或，如S合於該異方性導電膠％上，如第3圖所 坡於該異方性導電=;;’。該電極凸塊271經壓合後係嵌 Ο Ο 科2發明不需使用焊錫材料，更無需形成高度—致的焊 《第鱗由該異方性導電勝26覆蓋該基板本體20 肀導曰μ a以包覆各該電性接觸墊211，再將複數個 具塘^\ 27壓合於該異方性導電膠26上，俾能同時於 晶片27*1 -板本體20的板材各別進行對位，使該些半導體 每觸塾211電極凸塊Μ準確對應各該基板本體20的電性 製程步進行歧面（panel)縣，俾有效節省 射裝二驟及成本；再者，依實際製程需要，亦可進行單顆 如于㈣異綠導電膠26作料電元件，無須 之制二厂而使焊料凸塊包覆電極凸塊以形成導電凸塊 因而本發明之半導體晶片27無須使用高度較高之 凸塊，俾有效降低整體封裝結構的厚度。 2 «晶封裝結構，係包括··基板本體 緣腺= 表面施’於該第—表面⑽上形成第一 21].θ 21a’且該第一線路層…具有複數電性接觸塾 ’絕緣㈣22 ’係形成於該基板本體2G及第一線路層 1拟跡成有複數第—開孔22G，令該些電性接觸塾 對應外露於各該第一開孔咖，且該絕緣薄膜22之厚 111184 15 201039415 係 度係低於該第一線路層21a之厚产… 形成於該絕緣薄膜22上，且〜防焊層23a 咖a，令部份之絕緣薄膜22及該些電中形成開口 該開口 23〇a;表面處理層24，係對應觸塾212露出於 22〇中之電性接觸塾21【上；異方::二於各該第-開孔 該第一防烊層23a之開口 23如的=膠26 ’係形成於 理層此半導體晶片27,係壓===面處 上，並具有複數電極凸塊271 , =異方性導電膠26 各該電性接觸墊2n，以令各該雷：電極凸塊271對應 塾211之間的異方性導電膠26妒= 鬼271與電性接觸 電極凸塊271萨由該導雷^成導電通路260,俾使該 ^ 211 · J: φ 6〇電性連接至該電性接觸 塾=其中，該電極凸塊271係壓合於該異方性 26上或嵌埋於該異方性導電層％中。 〆 依上狀覆晶職結構，形㈣表面處理層Μ之材 抖係選自由化學鐘鎳/金㈤Au)、化錦浸金（腦G)、 化錄把浸金⑽酬）、化學㈣（im_iQnTm)& 有機保焊劑（OSP)所組成之群組中之其中一者。 依上所述，該基板本體2〇具有相對於該第一表面施 之第二表面20b，於該第二表面2%上係形成第二線路層 21b，該第二線路層21b並具有複數植球塾212 ;該封裝基 板結構復包括形成於該第二表面2%及第二線路層⑽上 之防焊層23,且該防焊層23中形成複數第二開孔23〇，令 該植球墊212對應外露於各該第二開孔2 3 〇。 藉由前述實施例之說明，即知，本發明之特徵在於該 111184 16 201039415 基板本體20之第一表面20a及第一線路層21a上先形成絕 緣薄膜22，且該絕緣薄膜22中形成複數第一開孔220以 對應露出各該電性接觸墊211，接著於該電性接觸墊211 上形成表面處理層24，再於該絕緣薄膜22及電性接觸墊 211上形成異方性導電膠26,接著將該半導體晶片27壓合 於該異方性導電膠26上，令該半導體晶片27之電極凸塊 271與基板本體20之電性接觸墊211對應壓合，而於該異 方性導電膠26中形成導電通路260，俾令該電極凸塊271 ® 經由該導電通路260以電性連接至該電性接觸墊211。俾 於細間距佈局中，能有效克服習知進行線路對位、形成防 焊層開孔及預焊料填入開孔的困難性，並能避免習知迴焊 製程中產生焊料凸塊橋接短路之缺失。 再者，藉由該異方性導電膠26包覆該基板本體20之 電性接觸墊211，且該半導體晶片27之電極凸塊271對應 壓合於該異方性導電膠26上或嵌入該異方性導電膠26 Q 中，俾能有效避免習知底部填膠易產生空隙之問題，進而 避免於後續製程中產生之可靠度問題。 又，本發明係藉由該異方性導電膠26覆蓋該基板本 體20之第一表面20a，以包覆各該電性接觸墊211，再將 複數個半導體晶片27壓合於該異方性導電膠26，令該些 半導體晶片27能同時各別對位具有複數個基板本體20的 板材5使該些半導體晶片2 7的電極凸塊2 71對應各該基板 本體20的電性接觸墊211，因而能進行大版面（panel)封 裝，俾以有效節省製程步驟及成本；再者，依實際製程需 17 111184 201039415 要，亦可進行單顆封裝。 上述實施例僅例示性說明本發 非用於㈣本發明。任㈣f 原1及其功效’而 北1 項技蟄之人士均可扃π、土 月本發明之精神及範疇下，對 硬 ^ 门， 上加例進行修飾盥改 、文。因此，本發明之權利保護範園 一 __。 W應、如後叙中請專利 【圖式簡單說明】 第1A至1E圖係為習知覆晶封裝結構製法之剖視示意 圖； 〜 第2A至2E圖係為本發明之封裝基板結構及其製法之 剖視示意圖；以及 第3及3,圖係為本發明之覆晶封裝結構之剖視示意 圖。 【主要元件符號說明】 10 ' 20 基板本體 10a 表面 112 、 211 電性接觸墊 11 線路層 12 防焊層 120 開孔 14 預焊料 14a 焊料凸塊 15、27 半導體晶片 151 、 271 電極凸塊 111184 18 201039415 155 導電凸塊 16 底部填膠 20a 第一表面 20b 第二表面 21a 第一線路層 21b 第二線路層 212 植球墊 22 絕緣薄膜 Ο 220 第一開孔 23a 第一防焊層 230a 開口 23b 第二防焊層 230b 第二開孔 24 表面處理層 26 異方性導電膠 ❹ 260 導電通路 19 111184201039415 VI. Description of the Invention: [Technical Field] The present invention relates to a package structure and a method of manufacturing the same, and more particularly to a package substrate structure having a fine line pitch layout, a method of manufacturing the same, a flip chip package structure, and a method of fabricating the same. [Prior Art] With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. At present, a package substrate for carrying a semiconductor wafer includes a wire-bonded package substrate, a chip-scale package (CSP) substrate, and a flip-chip substrate (FCBGA); and is required for operation of a microprocessor, a wafer set, and a graphics chip. The packaged substrate with wiring also needs to improve the quality of the transmitted chip signal, improve the frequency, and control the specific function of the impedance 'in response to the development of I / O number of packages. In the current flip chip technology, the semiconductor wafer is electrically connected to the package substrate, and the surface of the semiconductor integrated circuit (1C) wafer is provided with an electronic pad, and the package substrate has corresponding electric power. a soldering pad, and a solder bump or other conductive adhesive material may be appropriately disposed between the semiconductor wafer and the package substrate, so that the semiconductor wafer is disposed on the package substrate with an electrical contact surface facing downward to borrow The solder bump or the conductive adhesive material electrically connects the semiconductor wafer to the package substrate, and fills an underfill resin between the semiconductor wafer and the package substrate to reduce the semiconductor wafer and the package substrate by the underfill Thermal stress due to differences in thermal expansion. The method of manufacturing a conventional flip chip package structure is shown in Figures 1A to 1E. 4111184 201039415 First, as shown in FIG. 1A, a substrate body 10 having at least one surface 10a is provided, a wiring layer 11 is formed on the surface 10a of the substrate body 10, and the circuit layer 11 has a plurality of electrical contact pads 112. . As shown in FIG. 1B, a solder resist layer 12 is formed on the surface 10a and the circuit layer 11, and a plurality of openings 120 are formed in the solder resist layer 12, so that the respective electrical contact pads 112 are correspondingly exposed to the respective openings. In the hole 120. As shown in Fig. 1C, a pre-solder 14 is then formed on the electrical contact pads 112 in each of the openings 120. As shown in Fig. 1D, after the pre-solder 14 on the substrate body 10 is reflowed and leveled to form solder bumps 14a of uniform height, a semiconductor wafer 15 having a plurality of electrode bumps 151 is attached. Finally, as shown in FIG. 1E, a reflow process is performed such that the solder bumps 14a cover the electrode bumps 151 to form the conductive bumps 155, and the underfill 16 is filled between the substrate body 10 and the semiconductor wafer 15. In order to reduce the thermal stress caused by the difference in thermal expansion between the semiconductor wafer 15 and the package substrate 10. However, in the flip chip packaging process described above, in the fine pitch layout of the high-density wiring, for example, the distance between the solder bumps 14a is less than 100 // m, and the alignment accuracy is less than 10//m, and the alignment accuracy is less than 10/m. The aperture 120 of the solder resist layer 12 has a hole diameter of 50/m or less, which is liable to cause alignment and difficulty in forming the opening 120 of the solder resist layer 12, and also increases the cost of the process equipment. Moreover, in the fine pitch layout, the opening 120 of the solder resist layer 12 is often small, so that the pre-solder 14 is not easily filled into the opening 120; and the spacing of the electrical contact pads 112 is narrow, resulting in The spacing of the opening 120 is narrow, and the 5111184 201039415 is likely to cause the solder bump 14a to overflow in the reflow process to cause a bridge phenomenon, causing the electrical conduction to be short-circuited. Moreover, the conventional flip chip method is to form a highly uniform solder bump 14a after the solder pre-solder 14 on the single substrate body 10 is reflowed and leveled, and then a semiconductor having a plurality of electrode bumps 151 is attached. The wafer 15 is subjected to a subsequent process; wherein the plate having a plurality of substrate bodies 1〇 is poor in flatness, and it is difficult to form a solder bump 14a of uniform height for large-panel packaging, so that the conventional flip-chip package structure can only be used. It takes a single package and costs process steps and costs. In addition, the underfill 16 must be filled between the substrate body 10 and the semiconductor wafer 15, and in the fine pitch process, the solder bumps 14a are reduced due to the narrowing of the pitch, resulting in conductive formation after reflow. The height of the bump 155 is also reduced, so that the distance between the semiconductor wafer 15 and the solder resist layer 12 of the substrate body 10 is shortened, so that the interval between the semiconductor wafer 15 and the solder resist layer 12 is narrow, so that the underfill is filled. 16 is not easy to flow into the filling, and is prone to voids, which is liable to cause reliability problems in subsequent processes. Therefore, how to provide a package substrate, a flip chip package and a method for manufacturing the same, in order to overcome the difficulty of performing line alignment, forming a solder mask opening, and pre-solder filling holes in a fine pitch layout of high-density wiring It can avoid the defects such as solder bump bridging short circuit and bottom filling not easy to be filled in the reflow process, which has become an urgent problem to be overcome in the industry. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the main object of the present invention is to provide a package substrate structure, a method for manufacturing the same, a flip chip package structure and a method for fabricating the same, and the utility model can effectively overcome the line alignment in the fine line process, 6 111184 201039415 The difficulty of forming the solder mask opening and the pre-solder filling into the opening is eliminated, and the lack of bridging short circuit in the reflow process is eliminated. To achieve the above and other objects, the present invention provides a package substrate structure, comprising: a substrate body having a first surface; a first circuit layer formed on the first surface and having a plurality of electrical contact pads; and insulation The film is formed on the substrate body and the first circuit layer, and a plurality of first openings are formed, so that the electrical contact pads are exposed to the first openings, and the thickness of the insulating film is low. a thickness of the first circuit layer; a first solder resist layer formed on the insulating film, and an opening is formed in the first solder resist layer, so that a portion of the insulating film and the electrical contact pads are exposed And an anisotropic conductive paste formed on the insulating film and the electrical contact pad in the opening of the first solder resist layer. The present invention provides a flip chip package structure, comprising: a substrate body having a first surface, a first circuit layer is formed on the first surface, and the first circuit layer has a plurality of electrical contact pads; and the insulating film Forming on the substrate body and the first circuit layer, and forming a plurality of first openings, wherein the electrical contact pads are correspondingly exposed to the first openings, and the thickness of the insulating film is lower than the a first soldering layer is formed on the insulating film, and an opening is formed in the first solder resist layer to expose a portion of the insulating film and the electrical contact pads to the opening; And a surface treatment layer corresponding to the electrical contact pads formed in each of the first openings; the anisotropic conductive paste is formed on the insulating film and the electrical contact pads in the opening of the first solder resist layer; The semiconductor wafer is press-fitted to the anisotropic conductor 7 111184 201039415 on the electro-adhesive 5 and has a plurality of electrode bumps ' such that the electrode bumps correspond to the respective electrical contact pads, so that the electrode bumps are in electrical contact with each other Anisotropy between pads The electro-glue forms a conductive path, and the electrode bump is electrically connected to the electrical contact pad by a conductive path formed by the anisotropic conductive paste. According to the package substrate structure and the flip chip package structure, the electrode bump can be pressed onto the anisotropic conductive paste, or the electrode bump can be embedded in the anisotropic conductive paste after being pressed. . According to the above package substrate structure and flip chip package structure, the surface treatment layer is further included on the electrical contact pads formed in each of the first openings, and the material forming the surface treatment layer is selected from electroless nickel plating/ One of a group consisting of gold, nickel immersion gold, nickel-palladium immersion gold, electroless tin plating, and organic solder retention. In addition, according to the above package substrate structure and flip chip package structure 5, the substrate body has a second surface opposite to the first surface and a second circuit layer formed on the second surface, the second circuit layer has a plurality of ball-forming pads; the package structure further includes a second solder resist layer formed on the second surface and the second circuit layer, wherein the second solder resist layer forms a plurality of second openings, so that the ball-planting The 塾 is correspondingly exposed to each of the second openings. The invention further provides a method for fabricating a package substrate structure, comprising: providing a substrate body having a first surface, forming a first circuit layer on the first surface of the substrate body, and the first circuit layer has a plurality of electrical properties a contact pad; an insulating film is formed on the first surface and the first circuit layer, and the thickness of the insulating film is lower than a thickness of the first circuit layer, and the insulating film forms a plurality of first openings, so that the electricity The contact pads are exposed to an opening of each of the 8111184 201039415; an opening is formed in the first layer formed on the insulating film to make a portion of the insulating thin* anti-caries layer, and the first solder resist is in the opening And the first solder mask, and the electrical contact pads exposing the first contact hole t of the electrical contact pad 7, the insulating film in σ and each of the inventions provide a kind of coating conductive. Providing a substrate body having a first surface structure and a ''° structure method, comprising: forming a first circuit layer on the surface, and the first surface of the substrate body = on the first surface line The layer has a plurality of electrical contact thicknesses lower than the first upper insulating film, and the thickness of the first γ layer is the same as the thickness of the first hole layer, and the insulating thin first to open the hole. Formed in the layer: a first anti-J is formed on the insulating film, and the first portion of the read-proof portion is 绝 _ and the first tamper-proof ,, the first, the center: the opening of the first solder-proof layer t: ' Sexual contact 塾露4方健 "Electrical contact 塾切^,% edge film and each of the W upper conductor conductors 4' and the electrical contact between the scorpion and the electrical 塾, to: The conductive double-sided bump is formed by conductive turns, so that the conductive contact surface formed by the electrical contact with the anisotropic conductive A A 43⁄4 # package substrate structure # s s # #发, 4, in the opposite side : Guided by the method of its production, the heart depends on 2, the guide electrode of the forest is convexly turned over ^ ^ 5 to make the structure and copy of the substrate, and the batch is in the first -n: The electrical contact between the package structure and the opening is formed on the surface of the electrical contact λ "", so that the read electrode is on the day, the semiconductor wafer has a power supply = corresponding to each of the electrical contacts 塾, I: 'sheng The pads are contacted between the contact pads to treat the U1184 201039415 surface treatment layer, and the material forming the surface treatment layer is selected from the group consisting of electroless nickel/gold plating, gold immersion gold, nickel immersion gold, chemical tin and organic protection. One of the groups of fluxes. According to the package substrate structure and the flip chip package structure and the method for manufacturing the same, the substrate body has a second surface corresponding to the first surface, and the second surface Forming a second circuit layer on the surface, the second circuit layer having a plurality of ball pads, forming a second solder resist layer on the second surface and the second circuit layer, and forming a plurality of solder layers in the second solder resist layer a second opening, wherein the ball-forming pad is correspondingly exposed to each of the second openings. The package substrate structure, the method for manufacturing the same, and the flip-chip package structure of the present invention are mainly applied to the first surface of the substrate body and An insulating film is formed on the first circuit layer. Forming a plurality of first openings in the insulating film to correspondingly expose the electrical contact pads of each of the first circuit layers, then forming a first solder resist layer on the insulating film, and forming an opening in the first solder resist layer, Forming a surface treatment layer on the electrical contact pad with an exposed portion of the insulating film and the electrical contact pads, and forming an anisotropic conductive layer on the insulating film and the surface treatment layer in the opening of the first solder resist layer And bonding the semiconductor wafer to the anisotropic conductive paste, so that the electrode bumps of the semiconductor wafer are pressed against the electrical contact pads of the substrate body, and the conductive paths are formed in the anisotropic conductive paste. The electrode bump is electrically connected to the electrical contact pad via the conductive path. As can be seen from the above, the present invention can effectively overcome the conventional line alignment and form the solder mask opening in the fine pitch layout. And the difficulty of filling the opening in the pre-solder, and avoiding the shortage of the solder bump bridging short circuit in the conventional reflow process 10 111184 201039415 loss; further, the thickness of the insulating film is lower than the thickness of the first circuit layer Compared with the conventional solder mask layer, the thickness is higher than that of the circuit layer, and a sufficient height difference (the circuit layer is higher than the insulating film) can be provided, so that the anisotropic conductive adhesive is easily dispersed after being filled, and the substrate is effectively coated. The electrical contact pads of the body do not cause voids, and the electrode bumps of the semiconductor wafer are correspondingly pressed onto the anisotropic conductive paste or embedded in the anisotropic conductive adhesive, thereby effectively avoiding the conventional underfill The glue is prone to voids and thus avoids reliability problems in subsequent processes. ^ In addition, compared with the prior art, the present invention does not require a solder material, and does not need to form a highly uniform solder bump. The surface of the substrate body is covered by the anisotropic conductive adhesive to cover the electrical contact. Pad, and pressing a plurality of semiconductor wafers to the anisotropic conductive paste to simultaneously position the electrode bumps of the plurality of substrate bodies with the electrical contact pads of the substrate body, that is, Large-area panel packaging can be used to save process steps and costs. In addition, according to the actual process requirements, it can also be packaged in a single package. In addition, the present invention utilizes the anisotropic conductive paste as a conductive member, and the solder bump is not required to be soldered to form a conductive bump without conventional solder reflow, and the present invention does not require the use of solder bumps. The higher electrode bumps are not formed, and the thickness of the overall package structure is effectively reduced. [Embodiment] The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. 11 111184 201039415 Please refer to FIGS. 2A to 2E , which are schematic diagrams of the package substrate structure, the method for manufacturing the same, and the flip chip package structure of the present invention. As shown in FIG. 2A, a substrate body 20 having an inner layer line (not shown) having a corresponding first surface 20a and a second surface 20b is provided on the first surface 20a of the substrate body 20 and The first circuit layer 21a and the second circuit layer 21b are respectively formed on the second surface 20b, and the conductive vias (not shown in the drawing) and the conductive blind holes are formed by the inner layer lines in the substrate body 20 (not in the figure) The first circuit layer 21a is electrically connected to the second circuit layer 21b, and the first circuit layer 21a has a plurality of electrical contact pads 211, and the second circuit layer 21b has a plurality of ball pads 212. As shown in FIG. 2B, an insulating film 22 is formed on the first surface 20a and the first circuit layer 21a, and a plurality of first openings 220 are formed in the insulating film 22, so that the electrical contact pads 211 are correspondingly exposed. Each of the first openings 220 and the thickness of the insulating film 22 is lower than the thickness of the first circuit layer 21a; wherein the thickness of the insulating film 22 is 0.1 to 5 μm; in addition, the insulating film 22 is high. Made of molecular materials. As shown in FIG. 2C, a first solder resist layer 23a is formed on the insulating film 22, and an opening 230a is formed in the first solder resist layer 23a to expose a portion of the insulating film 22 and the electrical contact pads 211. Forming a second solder resist layer 23b on the second surface 20b and the second circuit layer 21b, and forming a plurality of second openings 230b in the second solder resist layer 23b, so that the ball pad 212 is correspondingly exposed to each of the second openings 230b. As shown in FIG. 2D, a surface treatment layer 24 is formed on the electrical contact pads 211 in each of the first openings 220 of the insulating film 22; wherein the shape 12 111184 201039415 is selected as the material of the surface treatment layer 24 Free electroless nickel/gold (Ni/Au, first formed, then gold), nickel immersion gold (Electroless Ni & Immersion Gold, ENIG), nickel immersion gold (Electroless Nickel/Electroless Palladium/Immersion One of the group consisting of Gold, ENEPIG), Immersion Tin, and Organic Soldering Agent (〇SP); the present invention does not require the use of conductive bumps, and thus is more conventional than conventional techniques. The height is low. As shown in FIG. 2E, an anisotropic conductive film is formed on the insulating film 22 in the opening 230a of the first solder resist layer 23a and the electrical contact pad 211 in each of the first openings 220. , ACF) 26. The thickness of the insulating film 22 of the present invention is lower than the thickness of the first circuit layer 21a, and the present invention can provide a sufficient height difference compared to the structure in which the thickness of the conventional solder resist layer is higher than that of the circuit layer (the first circuit layer 2la) Above the insulating film 22), the anisotropic conductive paste 26 is easily dispersed after being filled, and the electrical contact 塾211 of the substrate body 20 is effectively covered to avoid voids. The anisotropic conductive adhesive (ACF, commonly known as the hetero-conducting conductive film) 26 is mainly composed of a binder and conductive particles, which can provide two kinds of bonding objects for electrical conduction only in a single direction. In the embodiment, it is electrically conductive in the vertical direction and has an insulating effect in the horizontal direction. The present invention provides a package substrate structure 'including a substrate body 2' having a first surface 2〇a; a first circuit layer 21a formed on the first surface 2〇a' and having a plurality of electrical properties The contact pad 211, the insulating film 22 is formed on the first surface 2〇a of the substrate body 2 and the first circuit layer 2u 111184 201039415, and forms a plurality of first openings 220, and the electrical contact pads 211 are formed. Correspondingly exposed to each of the first openings 220, and the thickness of the insulating film 22 is lower than the thickness of the first circuit layer 21a; the first solder resist layer 23a is formed on the insulating film 22, and the first An opening 230a is formed in the solder resist layer 23a, so that a portion of the insulating film 22 and the electrical contact pads 211 are exposed in the opening 230a; and an anisotropic conductive paste 26 is formed in the opening of the first solder resist layer 23a. The insulating film 22 and the electrical contact pad 211 in the 230a; and the surface treatment layer 24 are formed between the electrical contact pad 211 and the anisotropic conductive paste 26. According to the above package substrate structure, the material for forming the surface treatment layer 24 is selected from the group consisting of electroless nickel/gold (Ni/Au), nickel immersion gold (ENIG), nickel immersion gold (ENEPIG), and electroless tin plating ( One of a group of Immersion Tin) and Organic Soldering Agent (OSP). According to the above, the substrate body 20 has a second surface 20b opposite to the first surface 20a, and a second circuit layer 21b is formed on the second surface 20b. The second circuit layer 21b has a plurality of ball pads. The package substrate structure further includes a second solder resist layer 23b formed on the second surface 20b and the second circuit layer 21b, and the second solder resist layer 23b forms a plurality of second openings 230b, so that the implants The ball pad 212 is correspondingly exposed to each of the second openings 230b. Referring to FIGS. 3 and 3', an embodiment of a semiconductor wafer on a package substrate of the present invention; as shown, a semiconductor wafer 27 is laminated on the anisotropic conductive paste 26, the semiconductor wafer 27 having The plurality of electrode bumps 271 are arranged such that the electrode bumps 271 correspond to the respective electrical contact pads 211 to make the anisotropic conductive paste between the electrode bumps 271 and the electrical contact pads 211. 26 14184 201039415 ===电极 the electrode bump 271 by the conductive via-electrode bump factory/妾(4) 211, wherein the strip of the semiconductor wafer 27; or, if S is combined with the anisotropic conductive paste, as shown in FIG. The slope is in the anisotropy conduction =;;'. The electrode bump 271 is pressed and then embedded in the Ο Ο 2 2 invention does not need to use solder material, and does not need to form a high degree of welding "the scale is covered by the anisotropic conductive 26 to the substrate body 20 肀 guide 曰 μ a is used to cover each of the electrical contact pads 211, and a plurality of the plurality of pots are bonded to the anisotropic conductive paste 26, and can be simultaneously applied to the sheets of the wafer 27*1 - the board body 20 at the same time. The alignment enables the semiconductors to accurately correspond to the electrical process steps of each of the substrate bodies 20 for each of the semiconductor 211 electrode bumps, thereby effectively saving the shots and the cost; further, depending on the actual For the process, a single (4) iso-green conductive paste 26 can be used as the electrical component, and the solder bumps are not required to cover the electrode bumps to form the conductive bumps. Therefore, the semiconductor wafer 27 of the present invention does not need to be used. The higher bumps effectively reduce the thickness of the overall package structure. 2 «The crystal package structure, including the substrate body edge gland = surface applied on the first surface (10) to form a first 21]. θ 21a' and the first circuit layer ... has a plurality of electrical contacts 塾 'insulation (four) 22 The system is formed on the substrate body 2G and the first circuit layer 1 is formed with a plurality of first openings 22G, so that the electrical contacts are exposed to the first openings, and the thickness of the insulating film 22 is 111184 15 201039415 The system is lower than the thickness of the first circuit layer 21a... formed on the insulating film 22, and the solder resist layer 23a is a part of the insulating film 22 and the openings are formed in the electricity. The opening 23〇a; the surface treatment layer 24 is corresponding to the electrical contact 塾21 of the contact 212 exposed in the 22〇[upper; the opposite side: the opening of the first anti-mite layer 23a of each of the first opening 23 such as = glue 26 ' is formed in the physical layer of the semiconductor wafer 27, the pressure == = surface, and has a plurality of electrode bumps 271, = anisotropic conductive adhesive 26 each of the electrical contact pads 2n, Let each of the mines: the electrode bump 271 corresponds to the anisotropic conductive adhesive 26 妒 between the 塾 211 = ghost 271 and the electrical contact electrode bump 271 The conductive bump 260 is electrically connected to the electrical contact 塾= wherein the electrode bump 271 is pressed against the anisotropy 26 or embedded in the conductive contact 260 In the anisotropic conductive layer %. 〆 上 上 上 晶 晶 晶 形 形 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四 四im_iQnTm) & One of a group of organic solder resists (OSP). According to the above, the substrate body 2 has a second surface 20b opposite to the first surface, and a second circuit layer 21b is formed on the second surface 2%, and the second circuit layer 21b has a plurality of implants. The ballast 212; the package substrate structure further comprises a solder resist layer 23 formed on the second surface 2% and the second circuit layer (10), and the plurality of second openings 23 are formed in the solder resist layer 23, so that the implant The ball pad 212 is correspondingly exposed to each of the second openings 2 3 〇. According to the description of the foregoing embodiments, the present invention is characterized in that the first surface 20a of the substrate body 20 and the first circuit layer 21a are first formed with an insulating film 22, and the insulating film 22 is formed in plural. An opening 220 is formed to expose each of the electrical contact pads 211, and then a surface treatment layer 24 is formed on the electrical contact pads 211, and an anisotropic conductive paste 26 is formed on the insulating film 22 and the electrical contact pads 211. Then, the semiconductor wafer 27 is pressed onto the anisotropic conductive paste 26, so that the electrode bumps 271 of the semiconductor wafer 27 are pressed against the electrical contact pads 211 of the substrate body 20, and the anisotropic conduction is performed. A conductive via 260 is formed in the adhesive 26 to electrically connect the electrode bump 271 ® to the electrical contact pad 211 via the conductive via 260 . In the fine pitch layout, it can effectively overcome the difficulties of conventional alignment, formation of solder mask opening and pre-solder filling, and can avoid solder bump bridging short circuit in the conventional reflow process. Missing. Furthermore, the electrical contact pads 211 of the substrate body 20 are covered by the anisotropic conductive paste 26, and the electrode bumps 271 of the semiconductor wafer 27 are correspondingly pressed onto the anisotropic conductive paste 26 or embedded therein. In the anisotropic conductive adhesive 26 Q, the crucible can effectively avoid the problem that the bottom filling is easy to generate voids, thereby avoiding the reliability problem in the subsequent process. Moreover, in the present invention, the first surface 20a of the substrate body 20 is covered by the anisotropic conductive paste 26 to cover the respective electrical contact pads 211, and the plurality of semiconductor wafers 27 are pressed against the anisotropy. The conductive paste 26 is such that the semiconductor wafers 27 can simultaneously align the plurality of substrate bodies 20 of the plurality of substrate bodies 20 such that the electrode bumps 2 71 of the semiconductor wafers 27 correspond to the electrical contact pads 211 of the substrate bodies 20; Therefore, large-area panel packaging can be performed to save process steps and costs. In addition, according to the actual process, 17 111184 201039415 is required, and a single package can also be used. The above embodiments are merely illustrative of the present invention and are not intended to be used in the invention. Anyone who has (4)f original 1 and its efficacy' and a technical skill in the north can modify and tamper with the hard-door and upper-additions under the spirit and scope of the invention. Therefore, the scope of the present invention is protected by __. W should be as follows, please refer to the patent [Simplified description of the drawings] 1A to 1E are schematic cross-sectional views of the conventional flip chip package structure method; ~ 2A to 2E are the package substrate structure of the present invention and A schematic cross-sectional view of the method; and Figures 3 and 3 are schematic cross-sectional views of the flip chip package structure of the present invention. [Main component symbol description] 10 ' 20 substrate body 10a surface 112, 211 electrical contact pad 11 circuit layer 12 solder resist layer 120 opening 14 pre-solder 14a solder bump 15, 27 semiconductor wafer 151, 271 electrode bump 111184 18 201039415 155 Conductive bump 16 underfill 20a first surface 20b second surface 21a first wiring layer 21b second wiring layer 212 ball pad 22 insulating film Ο 220 first opening 23a first solder resist 230a opening 23b Second solder mask 230b second opening 24 surface treatment layer 26 anisotropic conductive adhesive 260 conductive path 19 111184