TWI508197B - 半導體封裝件及其製法 - Google Patents
半導體封裝件及其製法 Download PDFInfo
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- TWI508197B TWI508197B TW102141421A TW102141421A TWI508197B TW I508197 B TWI508197 B TW I508197B TW 102141421 A TW102141421 A TW 102141421A TW 102141421 A TW102141421 A TW 102141421A TW I508197 B TWI508197 B TW I508197B
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- 239000004065 semiconductor Substances 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000010410 layer Substances 0.000 claims description 51
- 239000008393 encapsulating agent Substances 0.000 claims description 47
- 239000012790 adhesive layer Substances 0.000 claims description 38
- 230000000903 blocking effect Effects 0.000 claims description 34
- 238000005538 encapsulation Methods 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 6
- 239000012811 non-conductive material Substances 0.000 claims description 2
- 239000002904 solvent Substances 0.000 claims description 2
- 239000003292 glue Substances 0.000 claims 1
- 239000000084 colloidal system Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000005553 drilling Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
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- H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
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- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
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- Production Of Multi-Layered Print Wiring Board (AREA)
Description
本發明提供一種封裝件及其製法,尤指一種半導體封裝件及其製法。
隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢。為了滿足半導體封裝件微型化(miniaturization)的封裝需求,遂發展出許多封裝技術。
請參照第1A圖至第1H圖,係為習知技術中形成半導體封裝件之各步驟製程的剖視圖。
如第1A圖所示,首先提供一其上形成有第一黏著層122a的第一承載板12a,第一承載板12a之材質可為玻璃、金屬及陶瓷等等。
之後,如第1B圖所示地將具有作用面132及形成在作用面132處之銲墊134的晶片13接置於第一黏著層122a上。
而後,如第1C圖所示地於第一黏著層122a上形成封裝膠體11以包覆晶片13,並在之後於封裝膠體11上接置第二承載板12b,其中,第二承載板12b係可選擇性地在
其表面上形成有第二黏著層122b,以藉由第二黏著層122b接置封裝膠體11。
之後,如第1D圖所示地將第一黏著層122a及第一承載板12a從作用面132及封裝膠體11的表面上移除。
接著如第1E圖所示地將線路重佈層15形成在作用面132及封裝膠體11的外露表面上,並使線路重佈層15電性連接晶片13。更具體而言,線路重佈層15係具有介電層150、線路(未標元件符號)、第一電性連接墊152、導電盲孔154及第二電性連接墊156,其中,介電層150係形成在作用面132及封裝膠體11的外露表面上,而介電層150內係在與該外露表面相接的一側形成有電性連接於銲墊134的第一電性連接墊152,此外第一電性連接墊152與封裝膠體11連接側之另一側上係形成有與其電性連接之導電盲孔154,而導電盲孔154與第一電性連接墊152電性連接側的另一側上則形成有第二電性連接墊156。
隨後,如第1F圖所示地將形成於第三承載板12c上的第三黏著層122c接置於線路重佈層15上。
接著,如第1G圖所示地將第二承載板12b及第二黏著層122b一併移除。
最後,如第1H圖所示地在封裝膠體11中以雷射鑽孔的方式形成封裝膠體開孔112,以外露第一電性連接墊152。後續將於該封裝膠體開孔112中形成導電材料,並藉由該導電材料電性連接另一封裝結構,而形成半導體封裝件(省略後續步驟之圖式)。
然而,於第1H圖之步驟中,由於習知技術之雷射能量不易控制或其功率不穩定,故容易使線路重佈層中之第一電性連接墊152因雷射燒蝕而造成斷路等狀況。
因此,如何克服上述習知以雷射鑽孔方式形成封裝膠體開孔容易造成線路重佈層斷路的缺點,是本領域技術人員的一大課題。
有鑒於上述習知技術之缺失,本發明提供一種半導體封裝件的製法,係包括以下步驟:將具有作用面之晶片接置於一其上形成有第一黏著層的第一承載板上,且該作用面係連接該第一黏著層;將擋止結構形成在該第一黏著層未連接該晶片之區域上;於該第一黏著層上形成包覆該晶片與擋止結構的封裝膠體,並於該封裝膠體上接置第二承載板;將該第一黏著層及該第一承載板移除,以外露該作用面與擋止結構;將電性連接該半導體晶片與連接擋止結構的線路重佈層形成於該封裝膠體外露該作用面之表面上;將一第三承載板接置於該線路重佈層上;將該第二承載板移除;形成封裝膠體開孔以外露該擋止結構;以及移除該第三承載板。
另外,本發明提供一種半導體封裝件,係包括:具有複數個封裝膠體開孔的封裝膠體;嵌埋於該封裝膠體中的晶片,且該晶片具有外露於該封裝膠體的作用面;嵌埋於該封裝膠體中的擋止結構,其係外露於該封裝膠體外露該作用面之表面,且該擋止結構之位置對應該封裝膠體開
孔,而形成該擋止結構之材料係金屬或導電膠;形成於該封裝膠體外露該作用面的表面上的線路重佈層,該線路重佈層係電性連接該晶片與擋止結構;以及形成於該封裝膠體開孔中以電性連接該擋止結構的導電材料。
本發明可藉由將擋止結構嵌埋於封裝膠體中並使其位置對應後續欲設置封裝膠體開孔之處,而使形成該封裝膠體開孔時所使用之雷射功率不穩定時不會對該線路重佈層造成損傷,從而提高生產的良率。
1‧‧‧半導體封裝件
11‧‧‧封裝膠體
112‧‧‧封裝膠體開孔
12a‧‧‧第一承載板
12b‧‧‧第二承載板
12c‧‧‧第三承載板
122a‧‧‧第一黏著層
122b‧‧‧第二黏著層
122c‧‧‧第三黏著層
13‧‧‧晶片
132‧‧‧作用面
134‧‧‧銲墊
14‧‧‧擋止結構
15‧‧‧線路重佈層
150‧‧‧介電層
152‧‧‧第一電性連接墊
154‧‧‧導電盲孔
156‧‧‧第二電性連接墊
157‧‧‧介電層開口
17a‧‧‧第一導電元件
17b‧‧‧第三導電元件
18‧‧‧導電材料
2‧‧‧封裝結構
22‧‧‧第二導電元件
第1A圖至第1H圖係說明習知技術中形成半導體封裝件之各步驟的剖視圖;第2A圖至第2J圖係說明本發明之半導體封裝件的製法之各步驟的剖視圖,其中,第2I’圖係第2I圖之另一實施態樣;以及第3A圖與第3B圖係說明本發明之半導體封裝件的製法之另一實施例之剖視圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。本發明亦可藉由其它不同的具體實施例加以施行或應用,本說明書中的各項細節亦可基於不同觀點與應用,在不悖離本發明之精神下進行各種修飾與變更。
請參閱第2A圖至第2J圖,其係說明根據本發明之半
導體封裝件之製法的剖視圖。
首先請參照第2A圖,提供一其上形成有第一黏著層122a的第一承載板12a,其中,第一承載板12a之材質可為玻璃、金屬及陶瓷等等,但本發明不限於此。之後,在第一黏著層122a上接置晶片13,而晶片13係具有接置於第一黏著層122a上的作用面132,且作用面132係形成有銲墊134。
接著請參照第2B圖,其係將擋止結構14形成在第一黏著層122a未連接晶片13之區域上,其中形成擋止結構14之材料係金屬或導電膠,而該擋止結構14可選擇性地使用膠體形態的材料來形成,進一步而言,可使用金屬膠或導電膠來形成該擋止結構14,且擋止結構14投影至第一承載板12a的圖案可為圓形或矩形,但本發明不限於此。而本發明之另一實施例中可先將擋止結構14形成在第一黏著層122a上,再將晶片13接置於第一黏著層122a未形成擋止結構14之區域上。
請參照第2C圖,其中係於該第一黏著層122a上形成封裝膠體11以包覆晶片13與擋止結構14,並在之後於封裝膠體11上接置第二承載板12b,其中,第二承載板12b係可選擇性地在其表面上形成有第二黏著層122b,以藉由第二黏著層122b接置封裝膠體11。而在本發明之另一實施例中,係將其上形成有封裝膠體11之第二承載板12b壓合至第一黏著層122a的表面上。
請參照第2D圖,其中係接著將第一黏著層122a及第
一承載板12a從作用面132、擋止結構14及封裝膠體11的表面上移除,以至少外露作用面132、銲墊134、擋止結構14及一部分封裝膠體11。
請參照第2E圖,其係將線路重佈層15形成在作用面132、擋止結構14及封裝膠體11的外露表面上,並使線路重佈層15電性連接半導體之晶片13及電性連接擋止結構14。更具體而言,線路重佈層15係具有介電層150、線路(未標示元件符號)、第一電性連接墊152、導電盲孔154及第二電性連接墊156,其中,介電層150係形成在作用面132、擋止結構14及封裝膠體11的外露表面上,而介電層150內係在與該外露表面相接的一側形成有電性連接於晶片13之銲墊134及擋止結構14的第一電性連接墊152,此外第一電性連接墊152連接銲墊134及擋止結構14之側的另一側係形成有與其電性連接之導電盲孔154,而導電盲孔154與第一電性連接墊152連接之側的另一側形成有第二電性連接墊156。並且介電層150內係在其與封裝膠體11連接側的另一側形成有介電層開口157,以將第二電性連接墊156外露。
請參照第2F圖,其係於該線路重佈層15上接置一第三承載板12c,其中,第三承載板12c係可選擇性地在其表面上形成有第三黏著層122c,以藉由第三黏著層122c接置線路重佈層15,並移除該第二承載板12b與第二黏著層122b。
請參照第2G圖,其係在封裝膠體11中以例如為雷射
鑽孔的方式形成封裝膠體開孔112,以外露擋止結構14。在此步驟中,擋止結構14可避免習知技術中雷射鑽孔時因雷射功率不穩定而過大之功率對第一電性連接墊152所造成的傷害,從而避免線路重佈層15斷路。
請參照第2H圖,其係在封裝膠體開孔112中形成第一導電元件17a,以使其與擋止結構14電性連接,而導電元件可為導電凸塊或銲球等形式,且第一導電元件17a係位於封裝膠體開孔112中,或者,第一導電元件17a可選擇性地凸出於封裝膠體開孔112外(未圖示此情況)。
請參照第2I圖,其係將第三承載板12c與第三黏著層122c從第二電性連接墊156及介電層150的表面上移除。請參照第2J圖,其係於第二電性連接墊156上接置例如銲球的第三導電元件17b,並於該封裝膠體14上方接置一封裝結構2,該封裝結構2之底部上接置複數個第二導電元件22,而封裝結構2係經由封裝膠體開孔112中的第一導電元件17a與第二導電元件22電性連接線路重佈層15。在另一實施例中,係可選擇性地不在其底部上接置複數個第二導電元件22,以使封裝結構2僅經由第一導電元件17a電性連接線路重佈層15(未圖示此情況)。
或者,本發明之半導體封裝件之製法的另一實施態樣係參照第2I’圖,其與上述之半導體封裝件之製法的相異之處係在於:直接在第2H圖之結構上接置一封裝結構2,以構成如第2I’圖之結構,之後,將第三承載板12c與第三黏著層122c從第二電性連接墊156及介電層150的表面
上移除,並在第二電性連接墊156上接置例如銲球的第三導電元件17b,以形成如第2J圖的態樣。
或者,於另一實施例中,形成擋止結構14之材料係非導電材料,故於第2G圖之步驟後,再以例如為電漿或溶劑溶解之方式(但本發明不限於此)移除擋止結構14,以外露該第一電性連接墊152,如第3A圖所示,且從而最後所形成之半導體封裝件係以第一導電元件17a直接連接第一電性連接墊152,如第3B圖所示。
本發明之半導體封裝件1係包括封裝膠體11、晶片13、擋止結構14、線路重佈層15及導電材料18。該半導體封裝件1中包含之各組成結構係詳細於下說明。
詳而言之,封裝膠體11係將晶片13及擋止結構14嵌埋於封裝膠體11之一側,並其中形成有複數個封裝膠體開孔112,其中該些封裝膠體開孔112係以雷射鑽孔方式形成,以將擋止結構14外露。
晶片13係具有外露於封裝膠體11的作用面132及銲墊134。
擋止結構14係嵌埋於封裝膠體11中,並外露於封裝膠體11外露之作用面132及銲墊134的表面,且擋止結構14之位置係對應封裝膠體開孔112,而形成擋止結構14之材料係金屬或導電膠,且該擋止結構14可選擇性地使用膠體形態的材料來形成,進一步而言,可使用金屬膠或導電膠來形成該擋止結構14。此外,擋止結構14投影至線路重佈層15的圖案係為圓形或矩形,但本發明不限於此。
線路重佈層15係形成於該封裝膠體11外露該作用面132的表面上,以電性連接該晶片13與擋止結構14,且導電材料18係形成於封裝膠體開孔112中,而導電材料18可以例如以下方式形成,如在封裝膠體開孔112中形成第一導電元件17a,以使其與第一電性連接墊152電性連接,而第一導電元件17a可為導電凸塊或銲球等形式,但本發明並不限於此,且第一導電元件17a可選擇性地位於封裝膠體開孔112中或凸出於封裝膠體開孔112外,而後復可包括封裝結構2,封裝結構2藉由位於其底部之複數個第二導電元件22而電性連接第一導電元件17a。因此,本發明之導電材料18可包括第一導電元件17a或可包括第一導電元件17a與第二導電元件22,該第一導電元件17a係形成於該封裝膠體開孔112中,該第二導電元件22係位於該封裝結構2之底部及該第一導電元件17a之間,並使該封裝結構2電性連接該第一導電元件17a。
封裝結構2係任何形式之封裝結構,並藉由導電材料18而電性連接擋止結構14,從而形成封裝結構2與線路重佈層15之間的電性連接路徑。
而在本發明之另一實施例中,線路重佈層15上可接置與其電性連接的複數第三導電元件17b,該些第三導電元件17b可為導電凸塊或銲球等形式,但本發明並不限於此。
綜上所述,相較於習知技術,由於本發明係藉由將擋止結構形成在第一黏著層未連接晶片之區域上並使封裝膠體將其包覆,該擋止結構之位置係對應後續線路重佈層之
第一電性連接墊,從而在以雷射鑽孔的方式形成封裝膠體開孔的期間避免因雷射功率不穩所致之對第一電性連接墊所造成的傷害,進而提升線路重佈層的良率與產品可靠度。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
1‧‧‧半導體封裝件
11‧‧‧封裝膠體
112‧‧‧封裝膠體開孔
13‧‧‧晶片
14‧‧‧擋止結構
15‧‧‧線路重佈層
152‧‧‧第一電性連接墊
157‧‧‧介電層開口
17a‧‧‧第一導電元件
17b‧‧‧第三導電元件
18‧‧‧導電材料
2‧‧‧封裝結構
22‧‧‧第二導電元件
Claims (15)
- 一種半導體封裝件的製法,係包括:於一其上形成有第一黏著層的第一承載板上接置具有作用面之晶片,且該作用面係連接該第一黏著層;將擋止結構形成在該第一黏著層未連接該晶片之區域上;於該第一黏著層上形成包覆該晶片與擋止結構的封裝膠體,並於該封裝膠體上接置第二承載板;移除該第一黏著層及該第一承載板,以外露該作用面與擋止結構;於該封裝膠體外露該作用面之表面上形成電性連接該半導體晶片與連接擋止結構的線路重佈層;於該線路重佈層上接置一第三承載板;移除該第二承載板;形成外露該擋止結構的封裝膠體開孔;以及移除該第三承載板。
- 如申請專利範圍第1項所述之半導體封裝件的製法,於移除該第三承載板後或於移除該第三承載板前,復包括於該封裝膠體上方接置一封裝結構,該封裝結構係經由該封裝膠體開孔電性連接該線路重佈層。
- 如申請專利範圍第2項所述之半導體封裝件的製法,復包括在形成該封裝膠體開孔後,於該封裝膠體開孔中形成第一導電元件,其係電性連接該線路重佈層且用以電性連接該封裝結構。
- 如申請專利範圍第3項所述之半導體封裝件的製法,復包括於接置該封裝結構前,於該封裝結構之底部上接置複數用以電性連接該線路重佈層的第二導電元件,且接置該封裝結構復包括使該第一導電元件電性連接該第二導電元件。
- 如申請專利範圍第1項所述之半導體封裝件的製法,復包括於移除該第三承載板後,於該線路重佈層上接置複數第三導電元件。
- 如申請專利範圍第1項所述之半導體封裝件的製法,其中,該封裝膠體開孔係藉由雷射來形成。
- 如申請專利範圍第1項所述之半導體封裝件的製法,其中,形成該擋止結構之材料係金屬或導電膠。
- 如申請專利範圍第1項所述之半導體封裝件的製法,其中,形成該擋止結構之材料係非導電材料,且於形成該封裝膠體開孔後,復包括移除該擋止結構。
- 如申請專利範圍第8項所述之半導體封裝件的製法,其中,移除該擋止結構之方式係藉由溶劑或電漿為之。
- 如申請專利範圍第1項所述之半導體封裝件的製法,其中,該擋止結構投影至該第一承載板的圖案係為圓形或矩形。
- 一種半導體封裝件,係包括:封裝膠體,係具有複數封裝膠體開孔;晶片,係嵌埋於該封裝膠體中,且具有外露於該封裝膠體的作用面; 擋止結構,係嵌埋於該封裝膠體中,並外露於該封裝膠體外露該作用面之表面,且該擋止結構之位置對應該封裝膠體開孔,形成該擋止結構之材料係金屬或導電膠;線路重佈層,係形成於該封裝膠體外露該作用面的表面上,以電性連接該晶片與擋止結構;以及導電材料,係形成於該封裝膠體開孔中,以電性連接該擋止結構。
- 如申請專利範圍第11項所述之半導體封裝件,復包括封裝結構,係位於該封裝膠體上方,且電性連接該導電材料。
- 如申請專利範圍第11項所述之半導體封裝件,其中,該導電材料復包括第一導電元件與第二導電元件,該第一導電元件係形成於該封裝膠體開孔中,該第二導電元件係位於該封裝結構之底部及該第一導電元件之間,並使該封裝結構電性連接該第一導電元件。
- 如申請專利範圍第11項所述之半導體封裝件,復包括接置於該線路重佈層上的複數第三導電元件。
- 如申請專利範圍第11項所述之半導體封裝件,其中,該擋止結構投影至該線路重佈層的圖案係為圓形或矩形。
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